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Searched full:iatu (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml33 normal controller functioning. iATU memory IO region is also required
47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
73 set of viewport CSRs mapped into the PL space. Note iATU is
92 Outbound iATU-capable memory-region which will be used to
H A Dsnps,dw-pcie.yaml42 are required for the normal controller work. iATU memory IO region is
56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
82 set of viewport CSRs mapped into the PL space. Note iATU is
101 Outbound iATU-capable memory-region which will be used to access
H A Dsnps,dw-pcie-common.yaml27 iATU/eDMA registers. The particular sub-space is selected by the
232 auto-detected based on the iATU memory writability. So there is no
242 on the iATU memory writability. There is no point having a dedicated
259 configuration space registers, Port Logic registers, DMA and iATU
H A Dbaikal,bt1-pcie.yaml18 performed by software. There four in- and four outbound iATU regions
30 DBI, DBI2 and at least 4KB outbound iATU-capable region for the
H A Dnvidia,tegra194-pcie-ep.yaml35 - description: iATU and DMA registers. This is where the iATU (internal
H A Dnvidia,tegra194-pcie.yaml34 - description: iATU and DMA registers. This is where the iATU (internal
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-designware.h68 /* Parameters for the waiting for iATU enabled routine */
131 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
132 * iATU region CSRs had been indirectly accessible by means of the dedicated
133 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
135 * iATU/eDMA CSRs space.
175 * introduced so eDMA and iATU could be accessed via a dedicated registers
194 * iATU Unroll-specific register definitions
H A Dpcie-designware.c129 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
523 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in __dw_pcie_prog_outbound_atu()
601 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
637 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_ep_inbound_atu()
820 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect()
839 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
H A Dpcie-designware-host.c655 dev_err(pci->dev, "No outbound iATU found\n"); in dw_pcie_iatu_setup()
705 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", in dw_pcie_iatu_setup()
728 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n", in dw_pcie_iatu_setup()
/openbmc/linux/drivers/accel/habanalabs/common/pci/
H A Dpci.c206 * hl_pci_iatu_write() - iatu write routine.
241 * Configure the iATU inbound region.
304 * Configure the iATU outbound region 0.
404 /* Driver must sleep in order for FW to finish the iATU configuration */ in hl_pci_init()
/openbmc/linux/include/linux/dma/
H A Dedma.h40 * iATU windows. That will be done by the controller
/openbmc/u-boot/drivers/pci/
H A Dpcie_imx.c72 /* iATU registers */
271 * iATU region setup
279 * split and defined into different regions by iATU, in imx_pcie_regions_setup()
H A Dpcie_layerscape.h33 /* iATU registers */
H A Dpcie_layerscape.c126 debug("iATU%d:\n", i); in ls_pcie_dump_atu()
H A Dpcie_dw_mvebu.c34 /* iATU registers */
/openbmc/linux/drivers/accel/habanalabs/include/common/
H A Dhl_boot_if.h282 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled.
283 * This bit if set, means the iATU has been
/openbmc/qemu/hw/pci-host/
H A Ddesignware.c493 * If no inbound iATU windows are configured, HW defaults to in designware_pcie_root_realize()
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c553 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
557 * This is needed in case the firmware doesn't initialize the iATU
657 /* Check whether FW is configuring iATU */ in goya_early_init()
2749 * iATU to point to the start address of the MMU page tables in goya_hw_init()
/openbmc/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h673 * @iatu_done_by_fw: true if iATU configuration is being done by FW.
1518 * @init_iatu: Initialize the iATU unit inside the PCI controller.
/openbmc/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c852 /* Check whether FW is configuring iATU */ in gaudi_early_init()
3921 /* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE. in gaudi_hw_init()
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c2971 * Only in pldm driver config iATU in gaudi2_early_init()
5953 /* If iATU is done by FW, the HBM bar ALWAYS points to DRAM_PHYS_BASE. in gaudi2_hw_init()