1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale i.MX6 PCI Express Root-Complex driver
4 *
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 *
7 * Based on upstream Linux kernel driver:
8 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
9 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 */
11
12 #include <common.h>
13 #include <pci.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/gpio.h>
18 #include <asm/io.h>
19 #include <linux/sizes.h>
20 #include <errno.h>
21 #include <asm/arch/sys_proto.h>
22
23 #define PCI_ACCESS_READ 0
24 #define PCI_ACCESS_WRITE 1
25
26 #ifdef CONFIG_MX6SX
27 #define MX6_DBI_ADDR 0x08ffc000
28 #define MX6_IO_ADDR 0x08000000
29 #define MX6_MEM_ADDR 0x08100000
30 #define MX6_ROOT_ADDR 0x08f00000
31 #else
32 #define MX6_DBI_ADDR 0x01ffc000
33 #define MX6_IO_ADDR 0x01000000
34 #define MX6_MEM_ADDR 0x01100000
35 #define MX6_ROOT_ADDR 0x01f00000
36 #endif
37 #define MX6_DBI_SIZE 0x4000
38 #define MX6_IO_SIZE 0x100000
39 #define MX6_MEM_SIZE 0xe00000
40 #define MX6_ROOT_SIZE 0xfc000
41
42 /* PCIe Port Logic registers (memory-mapped) */
43 #define PL_OFFSET 0x700
44 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
45 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
46 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
47 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
48 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
49 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
50 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
51
52 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
53 #define PCIE_PHY_CTRL_DATA_LOC 0
54 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
55 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
56 #define PCIE_PHY_CTRL_WR_LOC 18
57 #define PCIE_PHY_CTRL_RD_LOC 19
58
59 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
60 #define PCIE_PHY_STAT_DATA_LOC 0
61 #define PCIE_PHY_STAT_ACK_LOC 16
62
63 /* PHY registers (not memory-mapped) */
64 #define PCIE_PHY_RX_ASIC_OUT 0x100D
65
66 #define PHY_RX_OVRD_IN_LO 0x1005
67 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
68 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
69
70 #define PCIE_PHY_PUP_REQ (1 << 7)
71
72 /* iATU registers */
73 #define PCIE_ATU_VIEWPORT 0x900
74 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
75 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
76 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
77 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
78 #define PCIE_ATU_CR1 0x904
79 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
80 #define PCIE_ATU_TYPE_IO (0x2 << 0)
81 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
82 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
83 #define PCIE_ATU_CR2 0x908
84 #define PCIE_ATU_ENABLE (0x1 << 31)
85 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
86 #define PCIE_ATU_LOWER_BASE 0x90C
87 #define PCIE_ATU_UPPER_BASE 0x910
88 #define PCIE_ATU_LIMIT 0x914
89 #define PCIE_ATU_LOWER_TARGET 0x918
90 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
91 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
92 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
93 #define PCIE_ATU_UPPER_TARGET 0x91C
94
95 /*
96 * PHY access functions
97 */
pcie_phy_poll_ack(void __iomem * dbi_base,int exp_val)98 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
99 {
100 u32 val;
101 u32 max_iterations = 10;
102 u32 wait_counter = 0;
103
104 do {
105 val = readl(dbi_base + PCIE_PHY_STAT);
106 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
107 wait_counter++;
108
109 if (val == exp_val)
110 return 0;
111
112 udelay(1);
113 } while (wait_counter < max_iterations);
114
115 return -ETIMEDOUT;
116 }
117
pcie_phy_wait_ack(void __iomem * dbi_base,int addr)118 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
119 {
120 u32 val;
121 int ret;
122
123 val = addr << PCIE_PHY_CTRL_DATA_LOC;
124 writel(val, dbi_base + PCIE_PHY_CTRL);
125
126 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
127 writel(val, dbi_base + PCIE_PHY_CTRL);
128
129 ret = pcie_phy_poll_ack(dbi_base, 1);
130 if (ret)
131 return ret;
132
133 val = addr << PCIE_PHY_CTRL_DATA_LOC;
134 writel(val, dbi_base + PCIE_PHY_CTRL);
135
136 ret = pcie_phy_poll_ack(dbi_base, 0);
137 if (ret)
138 return ret;
139
140 return 0;
141 }
142
143 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
pcie_phy_read(void __iomem * dbi_base,int addr,int * data)144 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
145 {
146 u32 val, phy_ctl;
147 int ret;
148
149 ret = pcie_phy_wait_ack(dbi_base, addr);
150 if (ret)
151 return ret;
152
153 /* assert Read signal */
154 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
155 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
156
157 ret = pcie_phy_poll_ack(dbi_base, 1);
158 if (ret)
159 return ret;
160
161 val = readl(dbi_base + PCIE_PHY_STAT);
162 *data = val & 0xffff;
163
164 /* deassert Read signal */
165 writel(0x00, dbi_base + PCIE_PHY_CTRL);
166
167 ret = pcie_phy_poll_ack(dbi_base, 0);
168 if (ret)
169 return ret;
170
171 return 0;
172 }
173
pcie_phy_write(void __iomem * dbi_base,int addr,int data)174 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
175 {
176 u32 var;
177 int ret;
178
179 /* write addr */
180 /* cap addr */
181 ret = pcie_phy_wait_ack(dbi_base, addr);
182 if (ret)
183 return ret;
184
185 var = data << PCIE_PHY_CTRL_DATA_LOC;
186 writel(var, dbi_base + PCIE_PHY_CTRL);
187
188 /* capture data */
189 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
190 writel(var, dbi_base + PCIE_PHY_CTRL);
191
192 ret = pcie_phy_poll_ack(dbi_base, 1);
193 if (ret)
194 return ret;
195
196 /* deassert cap data */
197 var = data << PCIE_PHY_CTRL_DATA_LOC;
198 writel(var, dbi_base + PCIE_PHY_CTRL);
199
200 /* wait for ack de-assertion */
201 ret = pcie_phy_poll_ack(dbi_base, 0);
202 if (ret)
203 return ret;
204
205 /* assert wr signal */
206 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
207 writel(var, dbi_base + PCIE_PHY_CTRL);
208
209 /* wait for ack */
210 ret = pcie_phy_poll_ack(dbi_base, 1);
211 if (ret)
212 return ret;
213
214 /* deassert wr signal */
215 var = data << PCIE_PHY_CTRL_DATA_LOC;
216 writel(var, dbi_base + PCIE_PHY_CTRL);
217
218 /* wait for ack de-assertion */
219 ret = pcie_phy_poll_ack(dbi_base, 0);
220 if (ret)
221 return ret;
222
223 writel(0x0, dbi_base + PCIE_PHY_CTRL);
224
225 return 0;
226 }
227
imx6_pcie_link_up(void)228 static int imx6_pcie_link_up(void)
229 {
230 u32 rc, ltssm;
231 int rx_valid, temp;
232
233 /* link is debug bit 36, debug register 1 starts at bit 32 */
234 rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
235 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
236 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
237 return -EAGAIN;
238
239 /*
240 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
241 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
242 * If (MAC/LTSSM.state == Recovery.RcvrLock)
243 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
244 * to gen2 is stuck
245 */
246 pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
247 ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
248
249 if (rx_valid & 0x01)
250 return 0;
251
252 if (ltssm != 0x0d)
253 return 0;
254
255 printf("transition to gen2 is stuck, reset PHY!\n");
256
257 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
258 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
259 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
260
261 udelay(3000);
262
263 pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
264 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
265 pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
266
267 return 0;
268 }
269
270 /*
271 * iATU region setup
272 */
imx_pcie_regions_setup(void)273 static int imx_pcie_regions_setup(void)
274 {
275 /*
276 * i.MX6 defines 16MB in the AXI address map for PCIe.
277 *
278 * That address space excepted the pcie registers is
279 * split and defined into different regions by iATU,
280 * with sizes and offsets as follows:
281 *
282 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
283 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
284 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
285 */
286
287 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
288 setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
289 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
290
291 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
292 setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
293 PCI_CLASS_BRIDGE_PCI << 16);
294
295 /* Region #0 is used for Outbound CFG space access. */
296 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
297
298 writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
299 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
300 writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
301
302 writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
303 writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
304 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
305 writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
306
307 return 0;
308 }
309
310 /*
311 * PCI Express accessors
312 */
get_bus_address(pci_dev_t d,int where)313 static uint32_t get_bus_address(pci_dev_t d, int where)
314 {
315 uint32_t va_address;
316
317 /* Reconfigure Region #0 */
318 writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
319
320 if (PCI_BUS(d) < 2)
321 writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
322 else
323 writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
324
325 if (PCI_BUS(d) == 0) {
326 va_address = MX6_DBI_ADDR;
327 } else {
328 writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
329 va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
330 }
331
332 va_address += (where & ~0x3);
333
334 return va_address;
335 }
336
imx_pcie_addr_valid(pci_dev_t d)337 static int imx_pcie_addr_valid(pci_dev_t d)
338 {
339 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
340 return -EINVAL;
341 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
342 return -EINVAL;
343 return 0;
344 }
345
346 /*
347 * Replace the original ARM DABT handler with a simple jump-back one.
348 *
349 * The problem here is that if we have a PCIe bridge attached to this PCIe
350 * controller, but no PCIe device is connected to the bridges' downstream
351 * port, the attempt to read/write from/to the config space will produce
352 * a DABT. This is a behavior of the controller and can not be disabled
353 * unfortuatelly.
354 *
355 * To work around the problem, we backup the current DABT handler address
356 * and replace it with our own DABT handler, which only bounces right back
357 * into the code.
358 */
imx_pcie_fix_dabt_handler(bool set)359 static void imx_pcie_fix_dabt_handler(bool set)
360 {
361 extern uint32_t *_data_abort;
362 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
363
364 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
365 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
366
367 static uint32_t data_abort_backup;
368
369 if (set) {
370 data_abort_backup = *data_abort_addr;
371 *data_abort_addr = data_abort_bounce_addr;
372 } else {
373 *data_abort_addr = data_abort_backup;
374 }
375 }
376
imx_pcie_read_config(struct pci_controller * hose,pci_dev_t d,int where,u32 * val)377 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
378 int where, u32 *val)
379 {
380 uint32_t va_address;
381 int ret;
382
383 ret = imx_pcie_addr_valid(d);
384 if (ret) {
385 *val = 0xffffffff;
386 return 0;
387 }
388
389 va_address = get_bus_address(d, where);
390
391 /*
392 * Read the PCIe config space. We must replace the DABT handler
393 * here in case we got data abort from the PCIe controller, see
394 * imx_pcie_fix_dabt_handler() description. Note that writing the
395 * "val" with valid value is also imperative here as in case we
396 * did got DABT, the val would contain random value.
397 */
398 imx_pcie_fix_dabt_handler(true);
399 writel(0xffffffff, val);
400 *val = readl(va_address);
401 imx_pcie_fix_dabt_handler(false);
402
403 return 0;
404 }
405
imx_pcie_write_config(struct pci_controller * hose,pci_dev_t d,int where,u32 val)406 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
407 int where, u32 val)
408 {
409 uint32_t va_address = 0;
410 int ret;
411
412 ret = imx_pcie_addr_valid(d);
413 if (ret)
414 return ret;
415
416 va_address = get_bus_address(d, where);
417
418 /*
419 * Write the PCIe config space. We must replace the DABT handler
420 * here in case we got data abort from the PCIe controller, see
421 * imx_pcie_fix_dabt_handler() description.
422 */
423 imx_pcie_fix_dabt_handler(true);
424 writel(val, va_address);
425 imx_pcie_fix_dabt_handler(false);
426
427 return 0;
428 }
429
430 /*
431 * Initial bus setup
432 */
imx6_pcie_assert_core_reset(bool prepare_for_boot)433 static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
434 {
435 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
436
437 if (is_mx6dqp())
438 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
439
440 #if defined(CONFIG_MX6SX)
441 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
442
443 /* SSP_EN is not used on MX6SX anymore */
444 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
445 /* Force PCIe PHY reset */
446 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
447 /* Power up PCIe PHY */
448 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
449 #else
450 /*
451 * If the bootloader already enabled the link we need some special
452 * handling to get the core back into a state where it is safe to
453 * touch it for configuration. As there is no dedicated reset signal
454 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
455 * state before completely disabling LTSSM, which is a prerequisite
456 * for core configuration.
457 *
458 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
459 * indication that the bootloader activated the link.
460 */
461 if (is_mx6dq() && prepare_for_boot) {
462 u32 val, gpr1, gpr12;
463
464 gpr1 = readl(&iomuxc_regs->gpr[1]);
465 gpr12 = readl(&iomuxc_regs->gpr[12]);
466 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
467 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
468 val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
469 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
470 val |= PCIE_PL_PFLR_FORCE_LINK;
471
472 imx_pcie_fix_dabt_handler(true);
473 writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
474 imx_pcie_fix_dabt_handler(false);
475
476 gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
477 writel(val, &iomuxc_regs->gpr[12]);
478 }
479 }
480 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
481 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
482 #endif
483
484 return 0;
485 }
486
imx6_pcie_init_phy(void)487 static int imx6_pcie_init_phy(void)
488 {
489 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
490
491 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
492
493 clrsetbits_le32(&iomuxc_regs->gpr[12],
494 IOMUXC_GPR12_DEVICE_TYPE_MASK,
495 IOMUXC_GPR12_DEVICE_TYPE_RC);
496 clrsetbits_le32(&iomuxc_regs->gpr[12],
497 IOMUXC_GPR12_LOS_LEVEL_MASK,
498 IOMUXC_GPR12_LOS_LEVEL_9);
499
500 #ifdef CONFIG_MX6SX
501 clrsetbits_le32(&iomuxc_regs->gpr[12],
502 IOMUXC_GPR12_RX_EQ_MASK,
503 IOMUXC_GPR12_RX_EQ_2);
504 #endif
505
506 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
507 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
508 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
509 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
510 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
511 &iomuxc_regs->gpr[8]);
512
513 return 0;
514 }
515
imx6_pcie_toggle_power(void)516 __weak int imx6_pcie_toggle_power(void)
517 {
518 #ifdef CONFIG_PCIE_IMX_POWER_GPIO
519 gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
520 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
521 mdelay(20);
522 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
523 mdelay(20);
524 gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
525 #endif
526 return 0;
527 }
528
imx6_pcie_toggle_reset(void)529 __weak int imx6_pcie_toggle_reset(void)
530 {
531 /*
532 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
533 * for detailed understanding of the PCIe CR reset logic.
534 *
535 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
536 * design does not conform to the specification. You must wait at
537 * least 20 ms after de-asserting the #PERST so the EP device can
538 * do self-initialisation.
539 *
540 * In case your #PERST pin is connected to a plain GPIO pin of the
541 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
542 * configuration file and the condition below will handle the rest
543 * of the reset toggling.
544 *
545 * In case your #PERST toggling logic is more complex, for example
546 * connected via CPLD or somesuch, you can override this function
547 * in your board file and implement reset logic as needed. You must
548 * not forget to wait at least 20 ms after de-asserting #PERST in
549 * this case either though.
550 *
551 * In case your #PERST line of the PCIe EP device is not connected
552 * at all, your design is broken and you should fix your design,
553 * otherwise you will observe problems like for example the link
554 * not coming up after rebooting the system back from running Linux
555 * that uses the PCIe as well OR the PCIe link might not come up in
556 * Linux at all in the first place since it's in some non-reset
557 * state due to being previously used in U-Boot.
558 */
559 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
560 gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
561 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
562 mdelay(20);
563 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
564 mdelay(20);
565 gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
566 #else
567 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
568 #endif
569 return 0;
570 }
571
imx6_pcie_deassert_core_reset(void)572 static int imx6_pcie_deassert_core_reset(void)
573 {
574 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
575
576 imx6_pcie_toggle_power();
577
578 enable_pcie_clock();
579
580 if (is_mx6dqp())
581 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
582
583 /*
584 * Wait for the clock to settle a bit, when the clock are sourced
585 * from the CPU, we need about 30 ms to settle.
586 */
587 mdelay(50);
588
589 #if defined(CONFIG_MX6SX)
590 /* SSP_EN is not used on MX6SX anymore */
591 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
592 /* Clear PCIe PHY reset bit */
593 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
594 #else
595 /* Enable PCIe */
596 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
597 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
598 #endif
599
600 imx6_pcie_toggle_reset();
601
602 return 0;
603 }
604
imx_pcie_link_up(void)605 static int imx_pcie_link_up(void)
606 {
607 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
608 uint32_t tmp;
609 int count = 0;
610
611 imx6_pcie_assert_core_reset(false);
612 imx6_pcie_init_phy();
613 imx6_pcie_deassert_core_reset();
614
615 imx_pcie_regions_setup();
616
617 /*
618 * By default, the subordinate is set equally to the secondary
619 * bus (0x01) when the RC boots.
620 * This means that theoretically, only bus 1 is reachable from the RC.
621 * Force the PCIe RC subordinate to 0xff, otherwise no downstream
622 * devices will be detected if the enumeration is applied strictly.
623 */
624 tmp = readl(MX6_DBI_ADDR + 0x18);
625 tmp |= (0xff << 16);
626 writel(tmp, MX6_DBI_ADDR + 0x18);
627
628 /*
629 * FIXME: Force the PCIe RC to Gen1 operation
630 * The RC must be forced into Gen1 mode before bringing the link
631 * up, otherwise no downstream devices are detected. After the
632 * link is up, a managed Gen1->Gen2 transition can be initiated.
633 */
634 tmp = readl(MX6_DBI_ADDR + 0x7c);
635 tmp &= ~0xf;
636 tmp |= 0x1;
637 writel(tmp, MX6_DBI_ADDR + 0x7c);
638
639 /* LTSSM enable, starting link. */
640 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
641
642 while (!imx6_pcie_link_up()) {
643 udelay(10);
644 count++;
645 if (count >= 4000) {
646 #ifdef CONFIG_PCI_SCAN_SHOW
647 puts("PCI: pcie phy link never came up\n");
648 #endif
649 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
650 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
651 readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
652 return -EINVAL;
653 }
654 }
655
656 return 0;
657 }
658
imx_pcie_init(void)659 void imx_pcie_init(void)
660 {
661 /* Static instance of the controller. */
662 static struct pci_controller pcc;
663 struct pci_controller *hose = &pcc;
664 int ret;
665
666 memset(&pcc, 0, sizeof(pcc));
667
668 /* PCI I/O space */
669 pci_set_region(&hose->regions[0],
670 MX6_IO_ADDR, MX6_IO_ADDR,
671 MX6_IO_SIZE, PCI_REGION_IO);
672
673 /* PCI memory space */
674 pci_set_region(&hose->regions[1],
675 MX6_MEM_ADDR, MX6_MEM_ADDR,
676 MX6_MEM_SIZE, PCI_REGION_MEM);
677
678 /* System memory space */
679 pci_set_region(&hose->regions[2],
680 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
681 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
682
683 hose->region_count = 3;
684
685 pci_set_ops(hose,
686 pci_hose_read_config_byte_via_dword,
687 pci_hose_read_config_word_via_dword,
688 imx_pcie_read_config,
689 pci_hose_write_config_byte_via_dword,
690 pci_hose_write_config_word_via_dword,
691 imx_pcie_write_config);
692
693 /* Start the controller. */
694 ret = imx_pcie_link_up();
695
696 if (!ret) {
697 pci_register_hose(hose);
698 hose->last_busno = pci_hose_scan(hose);
699 }
700 }
701
imx_pcie_remove(void)702 void imx_pcie_remove(void)
703 {
704 imx6_pcie_assert_core_reset(true);
705 }
706
707 /* Probe function. */
pci_init_board(void)708 void pci_init_board(void)
709 {
710 imx_pcie_init();
711 }
712