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/openbmc/linux/sound/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Tegra System-on-Chip"
10 Say Y or M here if you want support for SoC audio on Tegra.
82 Config to enable the Inter-IC Sound (I2S) Controller which
83 implements full-duplex and bidirectional and single direction
84 point-to-point serial interfaces. It can interface with I2S
113 converts the multi-bit Pulse Code Modulation (PCM) audio input to
114 oversampled 1-bit Pulse Density Modulation (PDM) output. From the
116 that up-samples the input to the desired sampling rate by
118 the desired 1-bit output via Delta Sigma Modulation (DSM).
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
[all …]
/openbmc/linux/drivers/staging/nvec/
H A DREADME4 embedded controller (EC) via I2C bus. The EC is an I2C master while the host
5 processor is the I2C slave. Requests from the host processor to the EC are
11 that other Tegra boards (not yet mainlined, if ever) also use it.
13 [1] e.g. https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=tree;f=arch/arm/mach-tegra/nvec;hb=a…
/openbmc/linux/drivers/i2c/busses/
H A Di2c-tegra-bpmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/i2c/busses/i2c-tegra-bpmp.c
11 #include <linux/i2c.h>
19 #include <soc/tegra/bpmp-abi.h>
20 #include <soc/tegra/bpmp.h>
23 * Serialized I2C message header size is 6 bytes and includes address, flags
37 * Linux flags are translated to BPMP defined I2C flags that are used in BPMP
38 * firmware I2C driver to avoid any issues in future if Linux I2C flags are
69 * The serialized I2C format is simply the following:
70 * [addr little-endian][flags little-endian][len little-endian][data if write]
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/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt1 NVIDIA Tegra host1x
4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dpmu.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <i2c.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/ap.h>
13 #include <asm/arch-tegra/tegra_i2c.h>
14 #include <asm/arch-tegra/sys_proto.h>
46 return -1; in pmu_set_nominal()
51 debug("%s: Cannot find DVC I2C bus\n", __func__); in pmu_set_nominal()
56 debug("%s: Cannot find DVC I2C chip\n", __func__); in pmu_set_nominal()
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra DisplayPort AUX Interface
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
15 pins which can be assigned to either the DPAUX channel or to an I2C
24 pattern: "^dpaux@[0-9a-f]+$"
[all …]
H A Dnvidia,tegra20-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra HDMI Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^hdmi@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-hdmi
[all …]
H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra SOR Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
[all …]
/openbmc/u-boot/drivers/misc/
H A DKconfig45 Enable support for I2C connected Atmel's ATSHA204A
50 bool "Rockchip e-fuse support"
53 Enable (read-only) access for the e-fuse block found in Rockchip
55 or through child-nodes that are generated based on the e-fuse map
74 Enable command-line access to the Chrome OS EC (Embedded
76 a number of sub-commands for performing EC tasks such as
78 and talking to the I2C bus behind the EC (if there is one).
90 bool "Enable Chrome OS EC I2C driver"
93 Enable I2C access to the Chrome OS EC. This is used on older
95 changed to SPI. The EC will accept commands across the I2C using
[all …]
/openbmc/u-boot/drivers/i2c/
H A DKconfig2 # I2C subsystem configuration
5 menu "I2C support"
8 bool "Enable Driver Model for I2C drivers"
11 Enable driver model for I2C. The I2C uclass interface: probe, read,
15 is defined in include/i2c.h. When i2c bus driver supports the i2c
20 bool "Enable I2C compatibility layer"
23 Enable old-style I2C functions for compatibility with existing code.
29 tristate "Chrome OS EC tunnel I2C bus"
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
10 #include <asm/arch/tegra.h>
11 #include <asm/arch-tegra/clk_rst.h>
12 #include <asm/arch-tegra/pmc.h>
13 #include <asm/arch-tegra/tegra_i2c.h>
16 /* Tegra30-specific CPU init code */
21 writel(addr, &reg->cmd_addr0); in tegra_i2c_ll_write_addr()
22 writel(config, &reg->cnfg); in tegra_i2c_ll_write_addr()
29 writel(data, &reg->cmd_data1); in tegra_i2c_ll_write_data()
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/openbmc/u-boot/board/toradex/colibri_t20/
H A Dcolibri_t20.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch-tegra/board.h>
12 #include <asm/arch-tegra/tegra.h>
15 #include <i2c.h>
17 #include "../common/tdx-common.h"
36 debug("%s: Cannot find PMIC I2C chip\n", __func__); in arch_misc_init()
70 (gd->ram_size == 0x10000000) ? 256 : 512, in checkboard()
71 (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ? in checkboard()
72 ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A"); in checkboard()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,nvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,nvec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
26 - description: divider clock
27 - description: fast clock
29 clock-names:
32 - const: div-clk
[all …]
/openbmc/linux/sound/pci/hda/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "HD-Audio"
23 This option enables the HD-audio controller. Don't forget
27 will be called snd-hda-intel.
30 tristate "NVIDIA Tegra HD Audio"
36 Tegra SoCs
39 present in some NVIDIA Tegra SoCs, used to communicate audio
43 will be called snd-hda-tegra.
48 bool "Build hwdep interface for HD-audio driver"
51 Say Y here to build a hwdep interface for HD-audio driver.
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 snd-hda-intel-objs := hda_intel.o
3 snd-hda-tegra-objs := hda_tegra.o
5 snd-hda-codec-y := hda_bind.o hda_codec.o hda_jack.o hda_auto_parser.o hda_sysfs.o
6 snd-hda-codec-y += hda_controller.o
7 snd-hda-codec-$(CONFIG_SND_PROC_FS) += hda_proc.o
9 snd-hda-codec-$(CONFIG_SND_HDA_HWDEP) += hda_hwdep.o
10 snd-hda-codec-$(CONFIG_SND_HDA_INPUT_BEEP) += hda_beep.o
12 # for trace-points
13 CFLAGS_hda_controller.o := -I$(src)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dos.h1 /* SPDX-License-Identifier: MIT */
14 #include <linux/i2c.h>
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/openbmc/linux/drivers/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
84 Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
[all …]
/openbmc/u-boot/doc/device-tree-bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
3 The BPMP is a specific processor in Tegra chip, which is designed for
11 - name : Should be bpmp
12 - compatible
15 - "nvidia,tegra186-bpmp"
16 - mboxes : The phandle of mailbox controller and the mailbox specifier.
17 - shmem : List of the phandle of the TX and RX shared memory area that
19 - #clock-cells : Should be 1.
20 - #power-domain-cells : Should be 1.
21 - #reset-cells : Should be 1.
[all …]
/openbmc/u-boot/drivers/reset/
H A DKconfig9 reset controller hardware module within the chip. In U-Boot, reset
39 bool "Enable Tegra CAR-based reset driver"
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
46 bool "Enable Tegra186 BPMP-based reset driver"
49 Enable support for manipulating Tegra's on-SoC reset signals via IPC
83 though is that some reset signals, like I2C or MISC reset multiple
/openbmc/u-boot/board/toradex/colibri_t30/
H A Dcolibri_t30.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014-2016
10 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch-tegra/tegra.h>
14 #include <i2c.h>
15 #include "pinmux-config-colibri_t30.h"
16 #include "../common/tdx-common.h"
53 /* Initialize any non-default pad configs (APB_MISC_GP regs) */ in pinmux_init()
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
15 rtc0 = "/i2c@7000d000/tps6586x@34";
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
[all …]
/openbmc/u-boot/board/toradex/apalis_t30/
H A Dapalis_t30.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014-2018
10 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch-tegra/tegra.h>
15 #include <i2c.h>
17 #include "../common/tdx-common.h"
19 #include "pinmux-config-apalis_t30.h"
45 (gd->ram_size == 0x40000000) ? 1 : 2); in checkboard()
69 /* Initialize any non-default pad configs (APB_MISC_GP regs) */ in pinmux_init()
83 debug("%s: Cannot find PMIC I2C chip\n", __func__); in tegra_pcie_board_init()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Dtegra20-i2c.txt3 Added in U-Boot:
6 - clocks : Two clocks must be given, each as a phandle to the Tegra's
8 - the I2C clock to use for the peripheral
9 - the pll_p_out3 clock, which can be used for fast operation. This
10 does not change and is the same for all I2C nodes.
15 i2c@7000c400 {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 compatible = "nvidia,tegra20-i2c";

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