Home
last modified time | relevance | path

Searched +full:i2c +full:- +full:0 (Results 1 – 25 of 1076) sorted by relevance

12345678910>>...44

/openbmc/linux/drivers/i2c/busses/
H A Di2c-jz4780.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 I2C bus driver
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
15 #include <linux/i2c.h>
27 #define JZ4780_I2C_CTRL 0x00
28 #define JZ4780_I2C_TAR 0x04
29 #define JZ4780_I2C_SAR 0x08
30 #define JZ4780_I2C_DC 0x10
31 #define JZ4780_I2C_SHCNT 0x14
32 #define JZ4780_I2C_SLCNT 0x18
[all …]
H A Di2c-mt65xx.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
14 #include <linux/i2c.h>
32 #define I2C_TRANSAC_COMP (1 << 0)
33 #define I2C_TRANSAC_START (1 << 0)
36 #define I2C_DCM_DISABLE 0x0000
37 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
38 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
39 #define I2C_SOFT_RST 0x0001
40 #define I2C_HANDSHAKE_RST 0x0020
[all …]
H A Di2c-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C adapter for the PXA I2C bus access.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
37 /* I2C register field definitions */
38 #define IBMR_SDAS (1 << 0)
41 #define ICR_START (1 << 0) /* start bit */
[all …]
H A Di2c-img-scb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C adapter for the IMG Serial Control Bus (SCB) IP block.
7 * There are three ways that this I2C controller can be driven:
9 * - Raw control of the SDA and SCK signals.
15 * - Atomic commands. A low level I2C symbol (such as generate
20 * This mode of operation is used by MODE_ATOMIC, which uses an I2C
21 * state machine in the interrupt handler to compose/react to I2C
26 * in suboptimal use of the bus, with gaps between the I2C symbols while
29 * - Automatic mode. A bus address, and whether to read/write is
30 * specified, and the hardware takes care of the I2C state machine,
[all …]
H A Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
35 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
50 REG_VALUES_100KHZ = 0,
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
[all …]
H A Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
25 #include <linux/i2c.h>
33 #define DRV_NAME "mpc-i2c"
35 #define MPC_I2C_CLOCK_LEGACY 0
36 #define MPC_I2C_CLOCK_PRESERVE (~0U)
38 #define MPC_I2C_FDR 0x04
39 #define MPC_I2C_CR 0x08
[all …]
H A Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Conexant Digicolor SoCs
13 #include <linux/i2c.h>
23 #define II_CONTROL 0x0
24 #define II_CONTROL_LOCAL_RESET BIT(0)
26 #define II_CLOCKTIME 0x1
28 #define II_COMMAND 0x2
37 #define II_CMD_STATUS_NORMAL 0
42 #define II_DATA 0x3
43 #define II_INTFLAG_CLEAR 0x8
[all …]
H A Di2c-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Amlogic Meson SoCs
11 #include <linux/i2c.h>
21 /* Meson I2C register map */
22 #define REG_CTRL 0x00
23 #define REG_SLAVE_ADDR 0x04
24 #define REG_TOK_LIST0 0x08
25 #define REG_TOK_LIST1 0x0c
26 #define REG_TOK_WDATA0 0x10
27 #define REG_TOK_WDATA1 0x14
[all …]
H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/i2c.h>
25 /* I2C register address definitions */
26 #define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
27 #define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
28 #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
29 #define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
30 #define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
32 #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
[all …]
H A Di2c-octeon-core.c2 * (C) Copyright 2009-2010
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7 * This file contains the shared part of the driver for the i2c adapter in
16 #include <linux/i2c.h>
21 #include "i2c-octeon-core.h"
26 struct octeon_i2c *i2c = dev_id; in octeon_i2c_isr() local
28 i2c->int_disable(i2c); in octeon_i2c_isr()
29 wake_up(&i2c->queue); in octeon_i2c_isr()
34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c) in octeon_i2c_test_iflg() argument
36 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG); in octeon_i2c_test_iflg()
[all …]
H A Di2c-exynos5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
37 #define HSI2C_CTL 0x00
38 #define HSI2C_FIFO_CTL 0x04
39 #define HSI2C_TRAILIG_CTL 0x08
40 #define HSI2C_CLK_CTL 0x0C
41 #define HSI2C_CLK_SLOT 0x10
42 #define HSI2C_INT_ENABLE 0x20
43 #define HSI2C_INT_STATUS 0x24
[all …]
H A Di2c-lpc2k.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Code portions referenced from the i2x-pxa and i2c-pnx drivers
17 #include <linux/i2c.h>
28 #define LPC24XX_I2CONSET 0x00
29 #define LPC24XX_I2STAT 0x04
30 #define LPC24XX_I2DAT 0x08
31 #define LPC24XX_I2ADDR 0x0c
32 #define LPC24XX_I2SCLH 0x10
33 #define LPC24XX_I2SCLL 0x14
34 #define LPC24XX_I2CONCLR 0x18
[all …]
H A Di2c-ocores.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/project/i2c/overview)
19 #include <linux/i2c.h>
22 #include <linux/platform_data/i2c-ocores.h>
49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
50 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
54 #define OCI2C_PRELOW 0
61 #define OCI2C_CTRL_IEN 0x40
62 #define OCI2C_CTRL_EN 0x80
[all …]
H A Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
38 #define S3C2410_IICCON 0x00
39 #define S3C2410_IICSTAT 0x04
40 #define S3C2410_IICADD 0x08
41 #define S3C2410_IICDS 0x0C
42 #define S3C2440_IICLC 0x10
[all …]
H A Di2c-kempld.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Kontron COM modules
5 * Copyright (c) 2010-2013 Kontron Europe GmbH
8 * The driver is based on the i2c-ocores driver by Peter Korsgaard.
13 #include <linux/i2c.h>
17 #define KEMPLD_I2C_PRELOW 0x0b
18 #define KEMPLD_I2C_PREHIGH 0x0c
19 #define KEMPLD_I2C_DATA 0x0e
21 #define KEMPLD_I2C_CTRL 0x0d
22 #define I2C_CTRL_IEN 0x40
[all …]
H A Di2c-rk3x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for I2C adapter in Rockchip RK3xxx SoC
11 #include <linux/i2c.h>
29 #define REG_CON 0x00 /* control register */
30 #define REG_CLKDIV 0x04 /* clock divisor register */
31 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
32 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
33 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
34 #define REG_MRXCNT 0x14 /* number of bytes to be received */
35 #define REG_IEN 0x18 /* interrupt enable */
[all …]
H A Di2c-mchp-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip PCI1XXXX I2C adapter driver for PCIe Switch
4 * which has I2C controller in one of its downstream functions
6 * Copyright (C) 2021 - 2022 Microchip Technology Inc.
14 #include <linux/i2c.h>
15 #include <linux/i2c-smbus.h>
22 #define SMBUS_MAST_CORE_ADDR_BASE 0x00000
23 #define SMBUS_MAST_SYS_REG_ADDR_BASE 0x01000
26 #define SMB_CORE_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x00)
30 #define SMB_CORE_CTRL_ACK BIT(0)
[all …]
/openbmc/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Internal I2C bus driver for NetUP Universal Dual DVB-CI
18 #define NETUP_I2C_BUS0_ADDR 0x4800
19 #define NETUP_I2C_BUS1_ADDR 0x4840
23 #define TWI_IRQEN_COMPL 0x1
24 #define TWI_IRQEN_ANACK 0x2
25 #define TWI_IRQEN_DNACK 0x4
29 #define TWI_IRQ_TX 0x800
30 #define TWI_IRQ_RX 0x1000
33 #define TWI_TRANSFER 0x100
[all …]
/openbmc/linux/Documentation/i2c/
H A Di2c-sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Linux I2C Sysfs
10 I2C topology can be complex because of the existence of I2C MUX
11 (I2C Multiplexer). The Linux
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
14 to logical I2C bus number. This doc is aimed to fill in this gap, so the
16 the concept of logical I2C buses in the kernel, by knowing the physical I2C
17 topology and navigating through the I2C sysfs in Linux shell. This knowledge is
18 useful and essential to use ``i2c-tools`` for the purpose of development and
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/configuration/entity-manager/
H A Ddevice-driver-probe3 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/gpio/phosphor-gpio-monitor/device-util
4 source /usr/libexec/phosphor-gpio-monitor/device-util
11 if /usr/sbin/i2cget -f -y "$bus" "$addr" 2>/dev/null; then
12 return 0
24 i2cset -f -y 29 0x1d 0x2e 0xff
25 i2cset -f -y 29 0x1f 0x2e 0xff
27 if read_i2c_dev 9 0x71; then
29 echo pca9546 0x71 > /sys/bus/i2c/devices/i2c-9/new_device
30 elif read_i2c_dev 11 0x71; then
32 echo pca9546 0x71 > /sys/bus/i2c/devices/i2c-11/new_device
[all …]
/openbmc/qemu/hw/i2c/
H A Dppc4xx_i2c.c2 * PPC4xx I2C controller emulation
8 * Copyright (c) 2016-2018 BALATON Zoltan
32 #include "hw/i2c/ppc4xx_i2c.h"
38 IIC_MDBUF = 0,
56 #define IIC_CNTL_PT (1 << 0)
67 #define IIC_STS_PT (1 << 0)
73 #define IIC_EXTSTS_XFRA (1 << 0)
77 #define IIC_INTRMSK_EIMTC (1 << 0)
82 #define IIC_XTCNTLSS_SRST (1 << 0)
87 #define IIC_DIRECTCNTL_MSCL (1 << 0)
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-cmm.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,cmm-bmc", "aspeed,ast2500";
22 * PCA9548 (1-0077) provides 8 channels for connecting to
35 * PCA9548 (2-0071) provides 8 channels for connecting to
48 * PCA9548 (8-0077) provides 8 channels and the first 4
61 * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting
82 * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting
103 * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting
[all …]
H A Daspeed-bmc-facebook-minipack.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,minipack-bmc", "aspeed,ast2500";
23 * i2c switch 2-0070, pca9548, 8 child channels assigned
24 * with bus number 16-23.
36 * i2c switch 8-0070, pca9548, 8 child channels assigned
37 * with bus number 24-31.
49 * i2c switch 9-0070, pca9548, 8 child channels assigned
50 * with bus number 32-39.
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dmeson_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
9 #include <i2c.h>
14 #define REG_CTRL_START BIT(0)
24 TOKEN_END = 0,
47 struct i2c_msg *msg; /* Current I2C message */
55 static void meson_i2c_reset_tokens(struct meson_i2c *i2c) in meson_i2c_reset_tokens() argument
57 i2c->tokens[0] = 0; in meson_i2c_reset_tokens()
58 i2c->tokens[1] = 0; in meson_i2c_reset_tokens()
59 i2c->num_tokens = 0; in meson_i2c_reset_tokens()
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_i2c.c2 * QEMU PowerPC PowerNV Processor I2C model
4 * Copyright (c) 2019-2023, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
25 #include "hw/i2c/pnv_i2c_regs.h"
27 static I2CBus *pnv_i2c_get_bus(PnvI2C *i2c) in pnv_i2c_get_bus() argument
29 uint8_t port = GETFIELD(I2C_MODE_PORT_NUM, i2c->regs[I2C_MODE_REG]); in pnv_i2c_get_bus()
31 if (port >= i2c->num_busses) { in pnv_i2c_get_bus()
32 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid bus number %d/%d\n", port, in pnv_i2c_get_bus()
33 i2c->num_busses); in pnv_i2c_get_bus()
[all …]

12345678910>>...44