136169369STharun Kumar P // SPDX-License-Identifier: GPL-2.0
236169369STharun Kumar P /*
336169369STharun Kumar P * Microchip PCI1XXXX I2C adapter driver for PCIe Switch
436169369STharun Kumar P * which has I2C controller in one of its downstream functions
536169369STharun Kumar P *
636169369STharun Kumar P * Copyright (C) 2021 - 2022 Microchip Technology Inc.
736169369STharun Kumar P *
836169369STharun Kumar P * Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
936169369STharun Kumar P * Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
1036169369STharun Kumar P */
1136169369STharun Kumar P
1236169369STharun Kumar P #include <linux/bits.h>
1336169369STharun Kumar P #include <linux/delay.h>
1436169369STharun Kumar P #include <linux/i2c.h>
1536169369STharun Kumar P #include <linux/i2c-smbus.h>
1636169369STharun Kumar P #include <linux/interrupt.h>
1736169369STharun Kumar P #include <linux/kernel.h>
1836169369STharun Kumar P #include <linux/module.h>
1936169369STharun Kumar P #include <linux/pci.h>
2036169369STharun Kumar P #include <linux/types.h>
2136169369STharun Kumar P
2236169369STharun Kumar P #define SMBUS_MAST_CORE_ADDR_BASE 0x00000
2336169369STharun Kumar P #define SMBUS_MAST_SYS_REG_ADDR_BASE 0x01000
2436169369STharun Kumar P
2536169369STharun Kumar P /* SMB register space. */
2636169369STharun Kumar P #define SMB_CORE_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x00)
2736169369STharun Kumar P
2836169369STharun Kumar P #define SMB_CORE_CTRL_ESO BIT(6)
2936169369STharun Kumar P #define SMB_CORE_CTRL_FW_ACK BIT(4)
3036169369STharun Kumar P #define SMB_CORE_CTRL_ACK BIT(0)
3136169369STharun Kumar P
3236169369STharun Kumar P #define SMB_CORE_CMD_REG_OFF3 (SMBUS_MAST_CORE_ADDR_BASE + 0x0F)
3336169369STharun Kumar P #define SMB_CORE_CMD_REG_OFF2 (SMBUS_MAST_CORE_ADDR_BASE + 0x0E)
3436169369STharun Kumar P #define SMB_CORE_CMD_REG_OFF1 (SMBUS_MAST_CORE_ADDR_BASE + 0x0D)
3536169369STharun Kumar P
3636169369STharun Kumar P #define SMB_CORE_CMD_READM BIT(4)
3736169369STharun Kumar P #define SMB_CORE_CMD_STOP BIT(2)
3836169369STharun Kumar P #define SMB_CORE_CMD_START BIT(0)
3936169369STharun Kumar P
4036169369STharun Kumar P #define SMB_CORE_CMD_REG_OFF0 (SMBUS_MAST_CORE_ADDR_BASE + 0x0C)
4136169369STharun Kumar P
4236169369STharun Kumar P #define SMB_CORE_CMD_M_PROCEED BIT(1)
4336169369STharun Kumar P #define SMB_CORE_CMD_M_RUN BIT(0)
4436169369STharun Kumar P
4536169369STharun Kumar P #define SMB_CORE_SR_HOLD_TIME_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x18)
4636169369STharun Kumar P
4736169369STharun Kumar P /*
4836169369STharun Kumar P * SR_HOLD_TIME_XK_TICKS field will indicate the number of ticks of the
4936169369STharun Kumar P * baud clock required to program 'Hold Time' at X KHz.
5036169369STharun Kumar P */
51aa874cdfSTharun Kumar P #define SR_HOLD_TIME_100K_TICKS 150
5236169369STharun Kumar P #define SR_HOLD_TIME_400K_TICKS 20
53aa874cdfSTharun Kumar P #define SR_HOLD_TIME_1000K_TICKS 12
5436169369STharun Kumar P
5536169369STharun Kumar P #define SMB_CORE_COMPLETION_REG_OFF3 (SMBUS_MAST_CORE_ADDR_BASE + 0x23)
5636169369STharun Kumar P
5736169369STharun Kumar P #define COMPLETION_MDONE BIT(6)
5836169369STharun Kumar P #define COMPLETION_IDLE BIT(5)
5936169369STharun Kumar P #define COMPLETION_MNAKX BIT(0)
6036169369STharun Kumar P
6136169369STharun Kumar P #define SMB_CORE_IDLE_SCALING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x24)
6236169369STharun Kumar P
6336169369STharun Kumar P /*
6436169369STharun Kumar P * FAIR_BUS_IDLE_MIN_XK_TICKS field will indicate the number of ticks of
6536169369STharun Kumar P * the baud clock required to program 'fair idle delay' at X KHz. Fair idle
6636169369STharun Kumar P * delay establishes the MCTP T(IDLE_DELAY) period.
6736169369STharun Kumar P */
68aa874cdfSTharun Kumar P #define FAIR_BUS_IDLE_MIN_100K_TICKS 992
69aa874cdfSTharun Kumar P #define FAIR_BUS_IDLE_MIN_400K_TICKS 500
70aa874cdfSTharun Kumar P #define FAIR_BUS_IDLE_MIN_1000K_TICKS 500
7136169369STharun Kumar P
7236169369STharun Kumar P /*
7336169369STharun Kumar P * FAIR_IDLE_DELAY_XK_TICKS field will indicate the number of ticks of the
7436169369STharun Kumar P * baud clock required to satisfy the fairness protocol at X KHz.
7536169369STharun Kumar P */
76aa874cdfSTharun Kumar P #define FAIR_IDLE_DELAY_100K_TICKS 963
77aa874cdfSTharun Kumar P #define FAIR_IDLE_DELAY_400K_TICKS 156
78aa874cdfSTharun Kumar P #define FAIR_IDLE_DELAY_1000K_TICKS 156
7936169369STharun Kumar P
8036169369STharun Kumar P #define SMB_IDLE_SCALING_100K \
8136169369STharun Kumar P ((FAIR_IDLE_DELAY_100K_TICKS << 16) | FAIR_BUS_IDLE_MIN_100K_TICKS)
8236169369STharun Kumar P #define SMB_IDLE_SCALING_400K \
8336169369STharun Kumar P ((FAIR_IDLE_DELAY_400K_TICKS << 16) | FAIR_BUS_IDLE_MIN_400K_TICKS)
8436169369STharun Kumar P #define SMB_IDLE_SCALING_1000K \
8536169369STharun Kumar P ((FAIR_IDLE_DELAY_1000K_TICKS << 16) | FAIR_BUS_IDLE_MIN_1000K_TICKS)
8636169369STharun Kumar P
8736169369STharun Kumar P #define SMB_CORE_CONFIG_REG3 (SMBUS_MAST_CORE_ADDR_BASE + 0x2B)
8836169369STharun Kumar P
8936169369STharun Kumar P #define SMB_CONFIG3_ENMI BIT(6)
9036169369STharun Kumar P #define SMB_CONFIG3_ENIDI BIT(5)
9136169369STharun Kumar P
9236169369STharun Kumar P #define SMB_CORE_CONFIG_REG2 (SMBUS_MAST_CORE_ADDR_BASE + 0x2A)
9336169369STharun Kumar P #define SMB_CORE_CONFIG_REG1 (SMBUS_MAST_CORE_ADDR_BASE + 0x29)
9436169369STharun Kumar P
9536169369STharun Kumar P #define SMB_CONFIG1_ASR BIT(7)
9636169369STharun Kumar P #define SMB_CONFIG1_ENAB BIT(2)
9736169369STharun Kumar P #define SMB_CONFIG1_RESET BIT(1)
9836169369STharun Kumar P #define SMB_CONFIG1_FEN BIT(0)
9936169369STharun Kumar P
10036169369STharun Kumar P #define SMB_CORE_BUS_CLK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x2C)
10136169369STharun Kumar P
10236169369STharun Kumar P /*
10336169369STharun Kumar P * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock
10436169369STharun Kumar P * periods that make up the low phase of the I2C/SMBus bus clock at X KHz.
10536169369STharun Kumar P */
10636169369STharun Kumar P #define BUS_CLK_100K_LOW_PERIOD_TICKS 156
10736169369STharun Kumar P #define BUS_CLK_400K_LOW_PERIOD_TICKS 41
10836169369STharun Kumar P #define BUS_CLK_1000K_LOW_PERIOD_TICKS 15
10936169369STharun Kumar P
11036169369STharun Kumar P /*
11136169369STharun Kumar P * BUS_CLK_XK_HIGH_PERIOD_TICKS field defines the number of I2C Baud Clock
11236169369STharun Kumar P * periods that make up the high phase of the I2C/SMBus bus clock at X KHz.
11336169369STharun Kumar P */
11436169369STharun Kumar P #define BUS_CLK_100K_HIGH_PERIOD_TICKS 154
11536169369STharun Kumar P #define BUS_CLK_400K_HIGH_PERIOD_TICKS 35
11636169369STharun Kumar P #define BUS_CLK_1000K_HIGH_PERIOD_TICKS 14
11736169369STharun Kumar P
11836169369STharun Kumar P #define BUS_CLK_100K \
11936169369STharun Kumar P ((BUS_CLK_100K_HIGH_PERIOD_TICKS << 8) | BUS_CLK_100K_LOW_PERIOD_TICKS)
12036169369STharun Kumar P #define BUS_CLK_400K \
12136169369STharun Kumar P ((BUS_CLK_400K_HIGH_PERIOD_TICKS << 8) | BUS_CLK_400K_LOW_PERIOD_TICKS)
12236169369STharun Kumar P #define BUS_CLK_1000K \
12336169369STharun Kumar P ((BUS_CLK_1000K_HIGH_PERIOD_TICKS << 8) | BUS_CLK_1000K_LOW_PERIOD_TICKS)
12436169369STharun Kumar P
12536169369STharun Kumar P #define SMB_CORE_CLK_SYNC_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x3C)
12636169369STharun Kumar P
12736169369STharun Kumar P /*
12836169369STharun Kumar P * CLK_SYNC_XK defines the number of clock cycles to sync up to the external
12936169369STharun Kumar P * clock before comparing the internal and external clocks for clock stretching
13036169369STharun Kumar P * at X KHz.
13136169369STharun Kumar P */
13236169369STharun Kumar P #define CLK_SYNC_100K 4
13336169369STharun Kumar P #define CLK_SYNC_400K 4
13436169369STharun Kumar P #define CLK_SYNC_1000K 4
13536169369STharun Kumar P
13636169369STharun Kumar P #define SMB_CORE_DATA_TIMING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x40)
13736169369STharun Kumar P
13836169369STharun Kumar P /*
13936169369STharun Kumar P *
14036169369STharun Kumar P * FIRST_START_HOLD_XK_TICKS will indicate the number of ticks of the baud
14136169369STharun Kumar P * clock required to program 'FIRST_START_HOLD' timer at X KHz. This timer
14236169369STharun Kumar P * determines the SCLK hold time following SDAT driven low during the first
14336169369STharun Kumar P * START bit in a transfer.
14436169369STharun Kumar P */
145aa874cdfSTharun Kumar P #define FIRST_START_HOLD_100K_TICKS 23
146aa874cdfSTharun Kumar P #define FIRST_START_HOLD_400K_TICKS 8
147aa874cdfSTharun Kumar P #define FIRST_START_HOLD_1000K_TICKS 12
14836169369STharun Kumar P
14936169369STharun Kumar P /*
15036169369STharun Kumar P * STOP_SETUP_XK_TICKS will indicate the number of ticks of the baud clock
15136169369STharun Kumar P * required to program 'STOP_SETUP' timer at X KHz. This timer determines the
15236169369STharun Kumar P * SDAT setup time from the rising edge of SCLK for a STOP condition.
15336169369STharun Kumar P */
154aa874cdfSTharun Kumar P #define STOP_SETUP_100K_TICKS 150
15536169369STharun Kumar P #define STOP_SETUP_400K_TICKS 20
15636169369STharun Kumar P #define STOP_SETUP_1000K_TICKS 12
15736169369STharun Kumar P
15836169369STharun Kumar P /*
15936169369STharun Kumar P * RESTART_SETUP_XK_TICKS will indicate the number of ticks of the baud clock
16036169369STharun Kumar P * required to program 'RESTART_SETUP' timer at X KHz. This timer determines the
16136169369STharun Kumar P * SDAT setup time from the rising edge of SCLK for a repeated START condition.
16236169369STharun Kumar P */
163aa874cdfSTharun Kumar P #define RESTART_SETUP_100K_TICKS 156
16436169369STharun Kumar P #define RESTART_SETUP_400K_TICKS 20
16536169369STharun Kumar P #define RESTART_SETUP_1000K_TICKS 12
16636169369STharun Kumar P
16736169369STharun Kumar P /*
16836169369STharun Kumar P * DATA_HOLD_XK_TICKS will indicate the number of ticks of the baud clock
16936169369STharun Kumar P * required to program 'DATA_HOLD' timer at X KHz. This timer determines the
17036169369STharun Kumar P * SDAT hold time following SCLK driven low.
17136169369STharun Kumar P */
172aa874cdfSTharun Kumar P #define DATA_HOLD_100K_TICKS 12
17336169369STharun Kumar P #define DATA_HOLD_400K_TICKS 2
17436169369STharun Kumar P #define DATA_HOLD_1000K_TICKS 2
17536169369STharun Kumar P
17636169369STharun Kumar P #define DATA_TIMING_100K \
17736169369STharun Kumar P ((FIRST_START_HOLD_100K_TICKS << 24) | (STOP_SETUP_100K_TICKS << 16) | \
17836169369STharun Kumar P (RESTART_SETUP_100K_TICKS << 8) | DATA_HOLD_100K_TICKS)
17936169369STharun Kumar P #define DATA_TIMING_400K \
18036169369STharun Kumar P ((FIRST_START_HOLD_400K_TICKS << 24) | (STOP_SETUP_400K_TICKS << 16) | \
18136169369STharun Kumar P (RESTART_SETUP_400K_TICKS << 8) | DATA_HOLD_400K_TICKS)
18236169369STharun Kumar P #define DATA_TIMING_1000K \
18336169369STharun Kumar P ((FIRST_START_HOLD_1000K_TICKS << 24) | (STOP_SETUP_1000K_TICKS << 16) | \
18436169369STharun Kumar P (RESTART_SETUP_1000K_TICKS << 8) | DATA_HOLD_1000K_TICKS)
18536169369STharun Kumar P
18636169369STharun Kumar P #define SMB_CORE_TO_SCALING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x44)
18736169369STharun Kumar P
18836169369STharun Kumar P /*
18936169369STharun Kumar P * BUS_IDLE_MIN_XK_TICKS defines Bus Idle Minimum Time.
19036169369STharun Kumar P * Bus Idle Minimum time = BUS_IDLE_MIN[7:0] x Baud_Clock_Period x
19136169369STharun Kumar P * (BUS_IDLE_MIN_XK_TICKS[7] ? 4,1)
19236169369STharun Kumar P */
193aa874cdfSTharun Kumar P #define BUS_IDLE_MIN_100K_TICKS 36UL
194aa874cdfSTharun Kumar P #define BUS_IDLE_MIN_400K_TICKS 10UL
195aa874cdfSTharun Kumar P #define BUS_IDLE_MIN_1000K_TICKS 4UL
19636169369STharun Kumar P
19736169369STharun Kumar P /*
19836169369STharun Kumar P * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out.
19936169369STharun Kumar P * SMBus Controller Cumulative Time-Out duration =
20036169369STharun Kumar P * CTRL_CUM_TIME_OUT_XK_TICKS[7:0] x Baud_Clock_Period x 2048
20136169369STharun Kumar P */
202aa874cdfSTharun Kumar P #define CTRL_CUM_TIME_OUT_100K_TICKS 76
203aa874cdfSTharun Kumar P #define CTRL_CUM_TIME_OUT_400K_TICKS 76
204aa874cdfSTharun Kumar P #define CTRL_CUM_TIME_OUT_1000K_TICKS 76
20536169369STharun Kumar P
20636169369STharun Kumar P /*
20736169369STharun Kumar P * TARGET_CUM_TIME_OUT_XK_TICKS defines SMBus Target Cumulative Time-Out duration.
20836169369STharun Kumar P * SMBus Target Cumulative Time-Out duration = TARGET_CUM_TIME_OUT_XK_TICKS[7:0] x
20936169369STharun Kumar P * Baud_Clock_Period x 4096
21036169369STharun Kumar P */
211aa874cdfSTharun Kumar P #define TARGET_CUM_TIME_OUT_100K_TICKS 95
212aa874cdfSTharun Kumar P #define TARGET_CUM_TIME_OUT_400K_TICKS 95
213aa874cdfSTharun Kumar P #define TARGET_CUM_TIME_OUT_1000K_TICKS 95
21436169369STharun Kumar P
21536169369STharun Kumar P /*
21636169369STharun Kumar P * CLOCK_HIGH_TIME_OUT_XK defines Clock High time out period.
21736169369STharun Kumar P * Clock High time out period = CLOCK_HIGH_TIME_OUT_XK[7:0] x Baud_Clock_Period x 8
21836169369STharun Kumar P */
219aa874cdfSTharun Kumar P #define CLOCK_HIGH_TIME_OUT_100K_TICKS 97
220aa874cdfSTharun Kumar P #define CLOCK_HIGH_TIME_OUT_400K_TICKS 97
221aa874cdfSTharun Kumar P #define CLOCK_HIGH_TIME_OUT_1000K_TICKS 97
22236169369STharun Kumar P
22336169369STharun Kumar P #define TO_SCALING_100K \
22436169369STharun Kumar P ((BUS_IDLE_MIN_100K_TICKS << 24) | (CTRL_CUM_TIME_OUT_100K_TICKS << 16) | \
22536169369STharun Kumar P (TARGET_CUM_TIME_OUT_100K_TICKS << 8) | CLOCK_HIGH_TIME_OUT_100K_TICKS)
22636169369STharun Kumar P #define TO_SCALING_400K \
22736169369STharun Kumar P ((BUS_IDLE_MIN_400K_TICKS << 24) | (CTRL_CUM_TIME_OUT_400K_TICKS << 16) | \
22836169369STharun Kumar P (TARGET_CUM_TIME_OUT_400K_TICKS << 8) | CLOCK_HIGH_TIME_OUT_400K_TICKS)
22936169369STharun Kumar P #define TO_SCALING_1000K \
23036169369STharun Kumar P ((BUS_IDLE_MIN_1000K_TICKS << 24) | (CTRL_CUM_TIME_OUT_1000K_TICKS << 16) | \
23136169369STharun Kumar P (TARGET_CUM_TIME_OUT_1000K_TICKS << 8) | CLOCK_HIGH_TIME_OUT_1000K_TICKS)
23236169369STharun Kumar P
23336169369STharun Kumar P #define I2C_SCL_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x100)
23436169369STharun Kumar P #define I2C_SDA_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x101)
23536169369STharun Kumar P
23636169369STharun Kumar P #define I2C_FOD_EN BIT(4)
23736169369STharun Kumar P #define I2C_PULL_UP_EN BIT(3)
23836169369STharun Kumar P #define I2C_PULL_DOWN_EN BIT(2)
23936169369STharun Kumar P #define I2C_INPUT_EN BIT(1)
24036169369STharun Kumar P #define I2C_OUTPUT_EN BIT(0)
24136169369STharun Kumar P
24236169369STharun Kumar P #define SMBUS_CONTROL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x200)
24336169369STharun Kumar P
24436169369STharun Kumar P #define CTL_RESET_COUNTERS BIT(3)
24536169369STharun Kumar P #define CTL_TRANSFER_DIR BIT(2)
24636169369STharun Kumar P #define CTL_HOST_FIFO_ENTRY BIT(1)
24736169369STharun Kumar P #define CTL_RUN BIT(0)
24836169369STharun Kumar P
24936169369STharun Kumar P #define I2C_DIRN_WRITE 0
25036169369STharun Kumar P #define I2C_DIRN_READ 1
25136169369STharun Kumar P
25236169369STharun Kumar P #define SMBUS_STATUS_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x204)
25336169369STharun Kumar P
25436169369STharun Kumar P #define STA_DMA_TERM BIT(7)
25536169369STharun Kumar P #define STA_DMA_REQ BIT(6)
25636169369STharun Kumar P #define STA_THRESHOLD BIT(2)
25736169369STharun Kumar P #define STA_BUF_FULL BIT(1)
25836169369STharun Kumar P #define STA_BUF_EMPTY BIT(0)
25936169369STharun Kumar P
26036169369STharun Kumar P #define SMBUS_INTR_STAT_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x208)
26136169369STharun Kumar P
26236169369STharun Kumar P #define INTR_STAT_DMA_TERM BIT(7)
26336169369STharun Kumar P #define INTR_STAT_THRESHOLD BIT(2)
26436169369STharun Kumar P #define INTR_STAT_BUF_FULL BIT(1)
26536169369STharun Kumar P #define INTR_STAT_BUF_EMPTY BIT(0)
26636169369STharun Kumar P
26736169369STharun Kumar P #define SMBUS_INTR_MSK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x20C)
26836169369STharun Kumar P
26936169369STharun Kumar P #define INTR_MSK_DMA_TERM BIT(7)
27036169369STharun Kumar P #define INTR_MSK_THRESHOLD BIT(2)
27136169369STharun Kumar P #define INTR_MSK_BUF_FULL BIT(1)
27236169369STharun Kumar P #define INTR_MSK_BUF_EMPTY BIT(0)
27336169369STharun Kumar P
27436169369STharun Kumar P #define ALL_NW_LAYER_INTERRUPTS \
27536169369STharun Kumar P (INTR_MSK_DMA_TERM | INTR_MSK_THRESHOLD | INTR_MSK_BUF_FULL | \
27636169369STharun Kumar P INTR_MSK_BUF_EMPTY)
27736169369STharun Kumar P
27836169369STharun Kumar P #define SMBUS_MCU_COUNTER_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x214)
27936169369STharun Kumar P
28036169369STharun Kumar P #define SMBALERT_MST_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x230)
28136169369STharun Kumar P
28236169369STharun Kumar P #define SMBALERT_MST_PU BIT(0)
28336169369STharun Kumar P
28436169369STharun Kumar P #define SMBUS_GEN_INT_STAT_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x23C)
28536169369STharun Kumar P
28636169369STharun Kumar P #define SMBUS_GEN_INT_MASK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x240)
28736169369STharun Kumar P
28836169369STharun Kumar P #define SMBALERT_INTR_MASK BIT(10)
28936169369STharun Kumar P #define I2C_BUF_MSTR_INTR_MASK BIT(9)
29036169369STharun Kumar P #define I2C_INTR_MASK BIT(8)
29136169369STharun Kumar P #define SMBALERT_WAKE_INTR_MASK BIT(2)
29236169369STharun Kumar P #define I2C_BUF_MSTR_WAKE_INTR_MASK BIT(1)
29336169369STharun Kumar P #define I2C_WAKE_INTR_MASK BIT(0)
29436169369STharun Kumar P
29536169369STharun Kumar P #define ALL_HIGH_LAYER_INTR \
29636169369STharun Kumar P (SMBALERT_INTR_MASK | I2C_BUF_MSTR_INTR_MASK | I2C_INTR_MASK | \
29736169369STharun Kumar P SMBALERT_WAKE_INTR_MASK | I2C_BUF_MSTR_WAKE_INTR_MASK | \
29836169369STharun Kumar P I2C_WAKE_INTR_MASK)
29936169369STharun Kumar P
30036169369STharun Kumar P #define SMBUS_RESET_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x248)
30136169369STharun Kumar P
30236169369STharun Kumar P #define PERI_SMBUS_D3_RESET_DIS BIT(16)
30336169369STharun Kumar P
30436169369STharun Kumar P #define SMBUS_MST_BUF (SMBUS_MAST_CORE_ADDR_BASE + 0x280)
30536169369STharun Kumar P
30636169369STharun Kumar P #define SMBUS_BUF_MAX_SIZE 0x80
30736169369STharun Kumar P
30836169369STharun Kumar P #define I2C_FLAGS_DIRECT_MODE BIT(7)
30936169369STharun Kumar P #define I2C_FLAGS_POLLING_MODE BIT(6)
31036169369STharun Kumar P #define I2C_FLAGS_STOP BIT(5)
31136169369STharun Kumar P #define I2C_FLAGS_SMB_BLK_READ BIT(4)
31236169369STharun Kumar P
31336169369STharun Kumar P #define PCI1XXXX_I2C_TIMEOUT_MS 1000
31436169369STharun Kumar P
31536169369STharun Kumar P /* General Purpose Register. */
31636169369STharun Kumar P #define SMB_GPR_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0c00 + \
31736169369STharun Kumar P 0x00)
31836169369STharun Kumar P
31936169369STharun Kumar P /* Lock Register. */
32036169369STharun Kumar P #define SMB_GPR_LOCK_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0000 + \
32136169369STharun Kumar P 0x00A0)
32236169369STharun Kumar P
32336169369STharun Kumar P #define SMBUS_PERI_LOCK BIT(3)
32436169369STharun Kumar P
32536169369STharun Kumar P struct pci1xxxx_i2c {
32636169369STharun Kumar P struct completion i2c_xfer_done;
32736169369STharun Kumar P bool i2c_xfer_in_progress;
32836169369STharun Kumar P struct i2c_adapter adap;
32936169369STharun Kumar P void __iomem *i2c_base;
33036169369STharun Kumar P u32 freq;
33136169369STharun Kumar P u32 flags;
33236169369STharun Kumar P };
33336169369STharun Kumar P
set_sys_lock(struct pci1xxxx_i2c * i2c)33436169369STharun Kumar P static int set_sys_lock(struct pci1xxxx_i2c *i2c)
33536169369STharun Kumar P {
33636169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG;
33736169369STharun Kumar P u8 data;
33836169369STharun Kumar P
33936169369STharun Kumar P writel(SMBUS_PERI_LOCK, p);
34036169369STharun Kumar P data = readl(p);
34136169369STharun Kumar P if (data != SMBUS_PERI_LOCK)
34236169369STharun Kumar P return -EPERM;
34336169369STharun Kumar P
34436169369STharun Kumar P return 0;
34536169369STharun Kumar P }
34636169369STharun Kumar P
release_sys_lock(struct pci1xxxx_i2c * i2c)34736169369STharun Kumar P static int release_sys_lock(struct pci1xxxx_i2c *i2c)
34836169369STharun Kumar P {
34936169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG;
35036169369STharun Kumar P u8 data;
35136169369STharun Kumar P
35236169369STharun Kumar P data = readl(p);
35336169369STharun Kumar P if (data != SMBUS_PERI_LOCK)
35436169369STharun Kumar P return 0;
35536169369STharun Kumar P
35636169369STharun Kumar P writel(0, p);
35736169369STharun Kumar P data = readl(p);
35836169369STharun Kumar P if (data & SMBUS_PERI_LOCK)
35936169369STharun Kumar P return -EPERM;
36036169369STharun Kumar P
36136169369STharun Kumar P return 0;
36236169369STharun Kumar P }
36336169369STharun Kumar P
pci1xxxx_ack_high_level_intr(struct pci1xxxx_i2c * i2c,u16 intr_msk)36436169369STharun Kumar P static void pci1xxxx_ack_high_level_intr(struct pci1xxxx_i2c *i2c, u16 intr_msk)
36536169369STharun Kumar P {
36636169369STharun Kumar P writew(intr_msk, i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF);
36736169369STharun Kumar P }
36836169369STharun Kumar P
pci1xxxx_i2c_configure_smbalert_pin(struct pci1xxxx_i2c * i2c,bool enable)36936169369STharun Kumar P static void pci1xxxx_i2c_configure_smbalert_pin(struct pci1xxxx_i2c *i2c,
37036169369STharun Kumar P bool enable)
37136169369STharun Kumar P {
37236169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBALERT_MST_PAD_CTRL_REG_OFF;
37336169369STharun Kumar P u8 regval;
37436169369STharun Kumar P
37536169369STharun Kumar P regval = readb(p);
37636169369STharun Kumar P
37736169369STharun Kumar P if (enable)
37836169369STharun Kumar P regval |= SMBALERT_MST_PU;
37936169369STharun Kumar P else
38036169369STharun Kumar P regval &= ~SMBALERT_MST_PU;
38136169369STharun Kumar P
38236169369STharun Kumar P writeb(regval, p);
38336169369STharun Kumar P }
38436169369STharun Kumar P
pci1xxxx_i2c_send_start_stop(struct pci1xxxx_i2c * i2c,bool start)38536169369STharun Kumar P static void pci1xxxx_i2c_send_start_stop(struct pci1xxxx_i2c *i2c, bool start)
38636169369STharun Kumar P {
38736169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
38836169369STharun Kumar P u8 regval;
38936169369STharun Kumar P
39036169369STharun Kumar P regval = readb(p);
39136169369STharun Kumar P
39236169369STharun Kumar P if (start)
39336169369STharun Kumar P regval |= SMB_CORE_CMD_START;
39436169369STharun Kumar P else
39536169369STharun Kumar P regval |= SMB_CORE_CMD_STOP;
39636169369STharun Kumar P
39736169369STharun Kumar P writeb(regval, p);
39836169369STharun Kumar P }
39936169369STharun Kumar P
40036169369STharun Kumar P /*
40136169369STharun Kumar P * When accessing the core control reg, we should not do a read modified write
40236169369STharun Kumar P * as they are write '1' to clear bits. Instead we need to write with the
40336169369STharun Kumar P * specific bits that needs to be set.
40436169369STharun Kumar P */
pci1xxxx_i2c_set_clear_FW_ACK(struct pci1xxxx_i2c * i2c,bool set)40536169369STharun Kumar P static void pci1xxxx_i2c_set_clear_FW_ACK(struct pci1xxxx_i2c *i2c, bool set)
40636169369STharun Kumar P {
40736169369STharun Kumar P u8 regval;
40836169369STharun Kumar P
40936169369STharun Kumar P if (set)
41036169369STharun Kumar P regval = SMB_CORE_CTRL_FW_ACK | SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK;
41136169369STharun Kumar P else
41236169369STharun Kumar P regval = SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK;
41336169369STharun Kumar P
41436169369STharun Kumar P writeb(regval, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);
41536169369STharun Kumar P }
41636169369STharun Kumar P
pci1xxxx_i2c_buffer_write(struct pci1xxxx_i2c * i2c,u8 slaveaddr,u8 transferlen,unsigned char * buf)41736169369STharun Kumar P static void pci1xxxx_i2c_buffer_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr,
41836169369STharun Kumar P u8 transferlen, unsigned char *buf)
41936169369STharun Kumar P {
42036169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_MST_BUF;
42136169369STharun Kumar P
42236169369STharun Kumar P if (slaveaddr)
42336169369STharun Kumar P writeb(slaveaddr, p++);
42436169369STharun Kumar P
42536169369STharun Kumar P if (buf)
42636169369STharun Kumar P memcpy_toio(p, buf, transferlen);
42736169369STharun Kumar P }
42836169369STharun Kumar P
42936169369STharun Kumar P /*
43036169369STharun Kumar P * When accessing the core control reg, we should not do a read modified write
43136169369STharun Kumar P * as there are write '1' to clear bits. Instead we need to write with the
43236169369STharun Kumar P * specific bits that needs to be set.
43336169369STharun Kumar P */
pci1xxxx_i2c_enable_ESO(struct pci1xxxx_i2c * i2c)43436169369STharun Kumar P static void pci1xxxx_i2c_enable_ESO(struct pci1xxxx_i2c *i2c)
43536169369STharun Kumar P {
43636169369STharun Kumar P writeb(SMB_CORE_CTRL_ESO, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);
43736169369STharun Kumar P }
43836169369STharun Kumar P
pci1xxxx_i2c_reset_counters(struct pci1xxxx_i2c * i2c)43936169369STharun Kumar P static void pci1xxxx_i2c_reset_counters(struct pci1xxxx_i2c *i2c)
44036169369STharun Kumar P {
44136169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
44236169369STharun Kumar P u8 regval;
44336169369STharun Kumar P
44436169369STharun Kumar P regval = readb(p);
44536169369STharun Kumar P regval |= CTL_RESET_COUNTERS;
44636169369STharun Kumar P writeb(regval, p);
44736169369STharun Kumar P }
44836169369STharun Kumar P
pci1xxxx_i2c_set_transfer_dir(struct pci1xxxx_i2c * i2c,u8 direction)44936169369STharun Kumar P static void pci1xxxx_i2c_set_transfer_dir(struct pci1xxxx_i2c *i2c, u8 direction)
45036169369STharun Kumar P {
45136169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
45236169369STharun Kumar P u8 regval;
45336169369STharun Kumar P
45436169369STharun Kumar P regval = readb(p);
45536169369STharun Kumar P if (direction == I2C_DIRN_WRITE)
45636169369STharun Kumar P regval &= ~CTL_TRANSFER_DIR;
45736169369STharun Kumar P else
45836169369STharun Kumar P regval |= CTL_TRANSFER_DIR;
45936169369STharun Kumar P
46036169369STharun Kumar P writeb(regval, p);
46136169369STharun Kumar P }
46236169369STharun Kumar P
pci1xxxx_i2c_set_mcu_count(struct pci1xxxx_i2c * i2c,u8 count)46336169369STharun Kumar P static void pci1xxxx_i2c_set_mcu_count(struct pci1xxxx_i2c *i2c, u8 count)
46436169369STharun Kumar P {
46536169369STharun Kumar P writeb(count, i2c->i2c_base + SMBUS_MCU_COUNTER_REG_OFF);
46636169369STharun Kumar P }
46736169369STharun Kumar P
pci1xxxx_i2c_set_read_count(struct pci1xxxx_i2c * i2c,u8 readcount)46836169369STharun Kumar P static void pci1xxxx_i2c_set_read_count(struct pci1xxxx_i2c *i2c, u8 readcount)
46936169369STharun Kumar P {
47036169369STharun Kumar P writeb(readcount, i2c->i2c_base + SMB_CORE_CMD_REG_OFF3);
47136169369STharun Kumar P }
47236169369STharun Kumar P
pci1xxxx_i2c_set_write_count(struct pci1xxxx_i2c * i2c,u8 writecount)47336169369STharun Kumar P static void pci1xxxx_i2c_set_write_count(struct pci1xxxx_i2c *i2c, u8 writecount)
47436169369STharun Kumar P {
47536169369STharun Kumar P writeb(writecount, i2c->i2c_base + SMB_CORE_CMD_REG_OFF2);
47636169369STharun Kumar P }
47736169369STharun Kumar P
pci1xxxx_i2c_set_DMA_run(struct pci1xxxx_i2c * i2c)47836169369STharun Kumar P static void pci1xxxx_i2c_set_DMA_run(struct pci1xxxx_i2c *i2c)
47936169369STharun Kumar P {
48036169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
48136169369STharun Kumar P u8 regval;
48236169369STharun Kumar P
48336169369STharun Kumar P regval = readb(p);
48436169369STharun Kumar P regval |= CTL_RUN;
48536169369STharun Kumar P writeb(regval, p);
48636169369STharun Kumar P }
48736169369STharun Kumar P
pci1xxxx_i2c_set_mrun_proceed(struct pci1xxxx_i2c * i2c)48836169369STharun Kumar P static void pci1xxxx_i2c_set_mrun_proceed(struct pci1xxxx_i2c *i2c)
48936169369STharun Kumar P {
49036169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF0;
49136169369STharun Kumar P u8 regval;
49236169369STharun Kumar P
49336169369STharun Kumar P regval = readb(p);
49436169369STharun Kumar P regval |= SMB_CORE_CMD_M_RUN;
49536169369STharun Kumar P regval |= SMB_CORE_CMD_M_PROCEED;
49636169369STharun Kumar P writeb(regval, p);
49736169369STharun Kumar P }
49836169369STharun Kumar P
pci1xxxx_i2c_start_DMA(struct pci1xxxx_i2c * i2c)49936169369STharun Kumar P static void pci1xxxx_i2c_start_DMA(struct pci1xxxx_i2c *i2c)
50036169369STharun Kumar P {
50136169369STharun Kumar P pci1xxxx_i2c_set_DMA_run(i2c);
50236169369STharun Kumar P pci1xxxx_i2c_set_mrun_proceed(i2c);
50336169369STharun Kumar P }
50436169369STharun Kumar P
pci1xxxx_i2c_config_asr(struct pci1xxxx_i2c * i2c,bool enable)50536169369STharun Kumar P static void pci1xxxx_i2c_config_asr(struct pci1xxxx_i2c *i2c, bool enable)
50636169369STharun Kumar P {
50736169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMB_CORE_CONFIG_REG1;
50836169369STharun Kumar P u8 regval;
50936169369STharun Kumar P
51036169369STharun Kumar P regval = readb(p);
51136169369STharun Kumar P if (enable)
51236169369STharun Kumar P regval |= SMB_CONFIG1_ASR;
51336169369STharun Kumar P else
51436169369STharun Kumar P regval &= ~SMB_CONFIG1_ASR;
51536169369STharun Kumar P writeb(regval, p);
51636169369STharun Kumar P }
51736169369STharun Kumar P
pci1xxxx_i2c_isr(int irq,void * dev)51836169369STharun Kumar P static irqreturn_t pci1xxxx_i2c_isr(int irq, void *dev)
51936169369STharun Kumar P {
52036169369STharun Kumar P struct pci1xxxx_i2c *i2c = dev;
52136169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF;
52236169369STharun Kumar P void __iomem *p2 = i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF;
52336169369STharun Kumar P irqreturn_t intr_handled = IRQ_NONE;
52436169369STharun Kumar P u16 reg1;
52536169369STharun Kumar P u8 reg3;
52636169369STharun Kumar P
52736169369STharun Kumar P /*
52836169369STharun Kumar P * Read the SMBus interrupt status register to see if the
52936169369STharun Kumar P * DMA_TERM interrupt has caused this callback.
53036169369STharun Kumar P */
53136169369STharun Kumar P reg1 = readw(p1);
53236169369STharun Kumar P
53336169369STharun Kumar P if (reg1 & I2C_BUF_MSTR_INTR_MASK) {
53436169369STharun Kumar P reg3 = readb(p2);
53536169369STharun Kumar P if (reg3 & INTR_STAT_DMA_TERM) {
53636169369STharun Kumar P complete(&i2c->i2c_xfer_done);
53736169369STharun Kumar P intr_handled = IRQ_HANDLED;
53836169369STharun Kumar P writeb(INTR_STAT_DMA_TERM, p2);
53936169369STharun Kumar P }
54036169369STharun Kumar P pci1xxxx_ack_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK);
54136169369STharun Kumar P }
54236169369STharun Kumar P
54336169369STharun Kumar P if (reg1 & SMBALERT_INTR_MASK) {
54436169369STharun Kumar P intr_handled = IRQ_HANDLED;
54536169369STharun Kumar P pci1xxxx_ack_high_level_intr(i2c, SMBALERT_INTR_MASK);
54636169369STharun Kumar P }
54736169369STharun Kumar P
54836169369STharun Kumar P return intr_handled;
54936169369STharun Kumar P }
55036169369STharun Kumar P
pci1xxxx_i2c_set_count(struct pci1xxxx_i2c * i2c,u8 mcucount,u8 writecount,u8 readcount)55136169369STharun Kumar P static void pci1xxxx_i2c_set_count(struct pci1xxxx_i2c *i2c, u8 mcucount,
55236169369STharun Kumar P u8 writecount, u8 readcount)
55336169369STharun Kumar P {
55436169369STharun Kumar P pci1xxxx_i2c_set_mcu_count(i2c, mcucount);
55536169369STharun Kumar P pci1xxxx_i2c_set_write_count(i2c, writecount);
55636169369STharun Kumar P pci1xxxx_i2c_set_read_count(i2c, readcount);
55736169369STharun Kumar P }
55836169369STharun Kumar P
pci1xxxx_i2c_set_readm(struct pci1xxxx_i2c * i2c,bool enable)55936169369STharun Kumar P static void pci1xxxx_i2c_set_readm(struct pci1xxxx_i2c *i2c, bool enable)
56036169369STharun Kumar P {
56136169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
56236169369STharun Kumar P u8 regval;
56336169369STharun Kumar P
56436169369STharun Kumar P regval = readb(p);
56536169369STharun Kumar P if (enable)
56636169369STharun Kumar P regval |= SMB_CORE_CMD_READM;
56736169369STharun Kumar P else
56836169369STharun Kumar P regval &= ~SMB_CORE_CMD_READM;
56936169369STharun Kumar P
57036169369STharun Kumar P writeb(regval, p);
57136169369STharun Kumar P }
57236169369STharun Kumar P
pci1xxxx_ack_nw_layer_intr(struct pci1xxxx_i2c * i2c,u8 ack_intr_msk)57336169369STharun Kumar P static void pci1xxxx_ack_nw_layer_intr(struct pci1xxxx_i2c *i2c, u8 ack_intr_msk)
57436169369STharun Kumar P {
57536169369STharun Kumar P writeb(ack_intr_msk, i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF);
57636169369STharun Kumar P }
57736169369STharun Kumar P
pci1xxxx_config_nw_layer_intr(struct pci1xxxx_i2c * i2c,u8 intr_msk,bool enable)57836169369STharun Kumar P static void pci1xxxx_config_nw_layer_intr(struct pci1xxxx_i2c *i2c,
57936169369STharun Kumar P u8 intr_msk, bool enable)
58036169369STharun Kumar P {
58136169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_INTR_MSK_REG_OFF;
58236169369STharun Kumar P u8 regval;
58336169369STharun Kumar P
58436169369STharun Kumar P regval = readb(p);
58536169369STharun Kumar P if (enable)
58636169369STharun Kumar P regval &= ~intr_msk;
58736169369STharun Kumar P else
58836169369STharun Kumar P regval |= intr_msk;
58936169369STharun Kumar P
59036169369STharun Kumar P writeb(regval, p);
59136169369STharun Kumar P }
59236169369STharun Kumar P
pci1xxxx_i2c_config_padctrl(struct pci1xxxx_i2c * i2c,bool enable)59336169369STharun Kumar P static void pci1xxxx_i2c_config_padctrl(struct pci1xxxx_i2c *i2c, bool enable)
59436169369STharun Kumar P {
59536169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + I2C_SCL_PAD_CTRL_REG_OFF;
59636169369STharun Kumar P void __iomem *p2 = i2c->i2c_base + I2C_SDA_PAD_CTRL_REG_OFF;
59736169369STharun Kumar P u8 regval;
59836169369STharun Kumar P
59936169369STharun Kumar P regval = readb(p1);
60036169369STharun Kumar P if (enable)
60136169369STharun Kumar P regval |= I2C_INPUT_EN | I2C_OUTPUT_EN;
60236169369STharun Kumar P else
60336169369STharun Kumar P regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN);
60436169369STharun Kumar P
60536169369STharun Kumar P writeb(regval, p1);
60636169369STharun Kumar P
60736169369STharun Kumar P regval = readb(p2);
60836169369STharun Kumar P if (enable)
60936169369STharun Kumar P regval |= I2C_INPUT_EN | I2C_OUTPUT_EN;
61036169369STharun Kumar P else
61136169369STharun Kumar P regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN);
61236169369STharun Kumar P
61336169369STharun Kumar P writeb(regval, p2);
61436169369STharun Kumar P }
61536169369STharun Kumar P
pci1xxxx_i2c_set_mode(struct pci1xxxx_i2c * i2c)61636169369STharun Kumar P static void pci1xxxx_i2c_set_mode(struct pci1xxxx_i2c *i2c)
61736169369STharun Kumar P {
61836169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
61936169369STharun Kumar P u8 regval;
62036169369STharun Kumar P
62136169369STharun Kumar P regval = readb(p);
62236169369STharun Kumar P if (i2c->flags & I2C_FLAGS_DIRECT_MODE)
62336169369STharun Kumar P regval &= ~CTL_HOST_FIFO_ENTRY;
62436169369STharun Kumar P else
62536169369STharun Kumar P regval |= CTL_HOST_FIFO_ENTRY;
62636169369STharun Kumar P
62736169369STharun Kumar P writeb(regval, p);
62836169369STharun Kumar P }
62936169369STharun Kumar P
pci1xxxx_i2c_config_high_level_intr(struct pci1xxxx_i2c * i2c,u16 intr_msk,bool enable)63036169369STharun Kumar P static void pci1xxxx_i2c_config_high_level_intr(struct pci1xxxx_i2c *i2c,
63136169369STharun Kumar P u16 intr_msk, bool enable)
63236169369STharun Kumar P {
63336169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_GEN_INT_MASK_REG_OFF;
63436169369STharun Kumar P u16 regval;
63536169369STharun Kumar P
63636169369STharun Kumar P regval = readw(p);
63736169369STharun Kumar P if (enable)
63836169369STharun Kumar P regval &= ~intr_msk;
63936169369STharun Kumar P else
64036169369STharun Kumar P regval |= intr_msk;
64136169369STharun Kumar P writew(regval, p);
64236169369STharun Kumar P }
64336169369STharun Kumar P
pci1xxxx_i2c_configure_core_reg(struct pci1xxxx_i2c * i2c,bool enable)64436169369STharun Kumar P static void pci1xxxx_i2c_configure_core_reg(struct pci1xxxx_i2c *i2c, bool enable)
64536169369STharun Kumar P {
64636169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + SMB_CORE_CONFIG_REG1;
64736169369STharun Kumar P void __iomem *p3 = i2c->i2c_base + SMB_CORE_CONFIG_REG3;
64836169369STharun Kumar P u8 reg1;
64936169369STharun Kumar P u8 reg3;
65036169369STharun Kumar P
65136169369STharun Kumar P reg1 = readb(p1);
65236169369STharun Kumar P reg3 = readb(p3);
65336169369STharun Kumar P if (enable) {
65436169369STharun Kumar P reg1 |= SMB_CONFIG1_ENAB | SMB_CONFIG1_FEN;
65536169369STharun Kumar P reg3 |= SMB_CONFIG3_ENMI | SMB_CONFIG3_ENIDI;
65636169369STharun Kumar P } else {
65736169369STharun Kumar P reg1 &= ~(SMB_CONFIG1_ENAB | SMB_CONFIG1_FEN);
65836169369STharun Kumar P reg3 &= ~(SMB_CONFIG3_ENMI | SMB_CONFIG3_ENIDI);
65936169369STharun Kumar P }
66036169369STharun Kumar P
66136169369STharun Kumar P writeb(reg1, p1);
66236169369STharun Kumar P writeb(reg3, p3);
66336169369STharun Kumar P }
66436169369STharun Kumar P
pci1xxxx_i2c_set_freq(struct pci1xxxx_i2c * i2c)66536169369STharun Kumar P static void pci1xxxx_i2c_set_freq(struct pci1xxxx_i2c *i2c)
66636169369STharun Kumar P {
66736169369STharun Kumar P void __iomem *bp = i2c->i2c_base;
66836169369STharun Kumar P void __iomem *p_idle_scaling = bp + SMB_CORE_IDLE_SCALING_REG_OFF;
66936169369STharun Kumar P void __iomem *p_data_timing = bp + SMB_CORE_DATA_TIMING_REG_OFF;
67036169369STharun Kumar P void __iomem *p_hold_time = bp + SMB_CORE_SR_HOLD_TIME_REG_OFF;
67136169369STharun Kumar P void __iomem *p_to_scaling = bp + SMB_CORE_TO_SCALING_REG_OFF;
67236169369STharun Kumar P void __iomem *p_clk_sync = bp + SMB_CORE_CLK_SYNC_REG_OFF;
67336169369STharun Kumar P void __iomem *p_clk_reg = bp + SMB_CORE_BUS_CLK_REG_OFF;
67436169369STharun Kumar P
67536169369STharun Kumar P switch (i2c->freq) {
67636169369STharun Kumar P case I2C_MAX_STANDARD_MODE_FREQ:
67736169369STharun Kumar P writeb(SR_HOLD_TIME_100K_TICKS, p_hold_time);
67836169369STharun Kumar P writel(SMB_IDLE_SCALING_100K, p_idle_scaling);
67936169369STharun Kumar P writew(BUS_CLK_100K, p_clk_reg);
68036169369STharun Kumar P writel(CLK_SYNC_100K, p_clk_sync);
68136169369STharun Kumar P writel(DATA_TIMING_100K, p_data_timing);
68236169369STharun Kumar P writel(TO_SCALING_100K, p_to_scaling);
68336169369STharun Kumar P break;
68436169369STharun Kumar P
68536169369STharun Kumar P case I2C_MAX_FAST_MODE_PLUS_FREQ:
68636169369STharun Kumar P writeb(SR_HOLD_TIME_1000K_TICKS, p_hold_time);
68736169369STharun Kumar P writel(SMB_IDLE_SCALING_1000K, p_idle_scaling);
68836169369STharun Kumar P writew(BUS_CLK_1000K, p_clk_reg);
68936169369STharun Kumar P writel(CLK_SYNC_1000K, p_clk_sync);
69036169369STharun Kumar P writel(DATA_TIMING_1000K, p_data_timing);
69136169369STharun Kumar P writel(TO_SCALING_1000K, p_to_scaling);
69236169369STharun Kumar P break;
69336169369STharun Kumar P
69436169369STharun Kumar P case I2C_MAX_FAST_MODE_FREQ:
69536169369STharun Kumar P default:
69636169369STharun Kumar P writeb(SR_HOLD_TIME_400K_TICKS, p_hold_time);
69736169369STharun Kumar P writel(SMB_IDLE_SCALING_400K, p_idle_scaling);
69836169369STharun Kumar P writew(BUS_CLK_400K, p_clk_reg);
69936169369STharun Kumar P writel(CLK_SYNC_400K, p_clk_sync);
70036169369STharun Kumar P writel(DATA_TIMING_400K, p_data_timing);
70136169369STharun Kumar P writel(TO_SCALING_400K, p_to_scaling);
70236169369STharun Kumar P break;
70336169369STharun Kumar P }
70436169369STharun Kumar P }
70536169369STharun Kumar P
pci1xxxx_i2c_init(struct pci1xxxx_i2c * i2c)70636169369STharun Kumar P static void pci1xxxx_i2c_init(struct pci1xxxx_i2c *i2c)
70736169369STharun Kumar P {
70836169369STharun Kumar P void __iomem *p2 = i2c->i2c_base + SMBUS_STATUS_REG_OFF;
70936169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + SMB_GPR_REG;
71036169369STharun Kumar P u8 regval;
7114a74e79bSColin Ian King int ret;
71236169369STharun Kumar P
71336169369STharun Kumar P ret = set_sys_lock(i2c);
71436169369STharun Kumar P if (ret == -EPERM) {
71536169369STharun Kumar P /*
71636169369STharun Kumar P * Configure I2C Fast Mode as default frequency if unable
71736169369STharun Kumar P * to acquire sys lock.
71836169369STharun Kumar P */
71936169369STharun Kumar P regval = 0;
72036169369STharun Kumar P } else {
72136169369STharun Kumar P regval = readl(p1);
72236169369STharun Kumar P release_sys_lock(i2c);
72336169369STharun Kumar P }
72436169369STharun Kumar P
72536169369STharun Kumar P switch (regval) {
72636169369STharun Kumar P case 0:
72736169369STharun Kumar P i2c->freq = I2C_MAX_FAST_MODE_FREQ;
72836169369STharun Kumar P pci1xxxx_i2c_set_freq(i2c);
72936169369STharun Kumar P break;
73036169369STharun Kumar P case 1:
73136169369STharun Kumar P i2c->freq = I2C_MAX_STANDARD_MODE_FREQ;
73236169369STharun Kumar P pci1xxxx_i2c_set_freq(i2c);
73336169369STharun Kumar P break;
73436169369STharun Kumar P case 2:
73536169369STharun Kumar P i2c->freq = I2C_MAX_FAST_MODE_PLUS_FREQ;
73636169369STharun Kumar P pci1xxxx_i2c_set_freq(i2c);
73736169369STharun Kumar P break;
73836169369STharun Kumar P case 3:
73936169369STharun Kumar P default:
74036169369STharun Kumar P break;
74136169369STharun Kumar P }
74236169369STharun Kumar P
74336169369STharun Kumar P pci1xxxx_i2c_config_padctrl(i2c, true);
74436169369STharun Kumar P i2c->flags |= I2C_FLAGS_DIRECT_MODE;
74536169369STharun Kumar P pci1xxxx_i2c_set_mode(i2c);
74636169369STharun Kumar P
74736169369STharun Kumar P /*
74836169369STharun Kumar P * Added as a precaution since BUF_EMPTY in status register
74936169369STharun Kumar P * also trigered an Interrupt.
75036169369STharun Kumar P */
75136169369STharun Kumar P writeb(STA_BUF_EMPTY, p2);
75236169369STharun Kumar P
75336169369STharun Kumar P /* Configure core I2c control registers. */
75436169369STharun Kumar P pci1xxxx_i2c_configure_core_reg(i2c, true);
75536169369STharun Kumar P
75636169369STharun Kumar P /*
75736169369STharun Kumar P * Enable pull-up for the SMB alert pin which is just used for
75836169369STharun Kumar P * wakeup right now.
75936169369STharun Kumar P */
76036169369STharun Kumar P pci1xxxx_i2c_configure_smbalert_pin(i2c, true);
76136169369STharun Kumar P }
76236169369STharun Kumar P
pci1xxxx_i2c_clear_flags(struct pci1xxxx_i2c * i2c)76336169369STharun Kumar P static void pci1xxxx_i2c_clear_flags(struct pci1xxxx_i2c *i2c)
76436169369STharun Kumar P {
76536169369STharun Kumar P u8 regval;
76636169369STharun Kumar P
76736169369STharun Kumar P /* Reset the internal buffer counters. */
76836169369STharun Kumar P pci1xxxx_i2c_reset_counters(i2c);
76936169369STharun Kumar P
77036169369STharun Kumar P /* Clear low level interrupts. */
77136169369STharun Kumar P regval = COMPLETION_MNAKX | COMPLETION_IDLE | COMPLETION_MDONE;
77236169369STharun Kumar P writeb(regval, i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3);
77336169369STharun Kumar P reinit_completion(&i2c->i2c_xfer_done);
77436169369STharun Kumar P pci1xxxx_ack_nw_layer_intr(i2c, ALL_NW_LAYER_INTERRUPTS);
77536169369STharun Kumar P pci1xxxx_ack_high_level_intr(i2c, ALL_HIGH_LAYER_INTR);
77636169369STharun Kumar P }
77736169369STharun Kumar P
pci1xxxx_i2c_read(struct pci1xxxx_i2c * i2c,u8 slaveaddr,unsigned char * buf,u16 total_len)77836169369STharun Kumar P static int pci1xxxx_i2c_read(struct pci1xxxx_i2c *i2c, u8 slaveaddr,
77936169369STharun Kumar P unsigned char *buf, u16 total_len)
78036169369STharun Kumar P {
78136169369STharun Kumar P void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3;
78236169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
78336169369STharun Kumar P void __iomem *p3 = i2c->i2c_base + SMBUS_MST_BUF;
78436169369STharun Kumar P unsigned long time_left;
78536169369STharun Kumar P u16 remainingbytes;
78636169369STharun Kumar P u8 transferlen;
78736169369STharun Kumar P int retval = 0;
78836169369STharun Kumar P u8 read_count;
78936169369STharun Kumar P u32 regval;
79036169369STharun Kumar P u16 count;
79136169369STharun Kumar P
79236169369STharun Kumar P /* Enable I2C host controller by setting the ESO bit in the CONTROL REG. */
79336169369STharun Kumar P pci1xxxx_i2c_enable_ESO(i2c);
79436169369STharun Kumar P pci1xxxx_i2c_clear_flags(i2c);
79536169369STharun Kumar P pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, true);
79636169369STharun Kumar P pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, true);
79736169369STharun Kumar P
79836169369STharun Kumar P /*
79936169369STharun Kumar P * The I2C transfer could be more than 128 bytes. Our Core is
80036169369STharun Kumar P * capable of only sending 128 at a time.
80136169369STharun Kumar P * As far as the I2C read is concerned, initailly send the
80236169369STharun Kumar P * read slave address along with the number of bytes to read in
80336169369STharun Kumar P * ReadCount. After sending the slave address the interrupt
80436169369STharun Kumar P * is generated. On seeing the ACK for the slave address, reverse the
80536169369STharun Kumar P * buffer direction and run the DMA to initiate Read from slave.
80636169369STharun Kumar P */
80736169369STharun Kumar P for (count = 0; count < total_len; count += transferlen) {
80836169369STharun Kumar P
80936169369STharun Kumar P /*
81036169369STharun Kumar P * Before start of any transaction clear the existing
81136169369STharun Kumar P * START/STOP conditions.
81236169369STharun Kumar P */
81336169369STharun Kumar P writeb(0, p1);
81436169369STharun Kumar P remainingbytes = total_len - count;
81536169369STharun Kumar P transferlen = min_t(u16, remainingbytes, SMBUS_BUF_MAX_SIZE);
81636169369STharun Kumar P
81736169369STharun Kumar P /*
81836169369STharun Kumar P * Send STOP bit for the last chunk in the transaction.
81936169369STharun Kumar P * For I2C read transaction of more than BUF_SIZE, NACK should
82036169369STharun Kumar P * only be sent for the last read.
82136169369STharun Kumar P * Hence a bit FW_ACK is set for all the read chunks except for
82236169369STharun Kumar P * the last chunk. For the last chunk NACK should be sent and
82336169369STharun Kumar P * FW_ACK is cleared Send STOP only when I2C_FLAGS_STOP bit is
82436169369STharun Kumar P * set in the flags and only for the last transaction.
82536169369STharun Kumar P */
82636169369STharun Kumar P if ((count + transferlen >= total_len) &&
82736169369STharun Kumar P (i2c->flags & I2C_FLAGS_STOP)) {
82836169369STharun Kumar P pci1xxxx_i2c_set_clear_FW_ACK(i2c, false);
82936169369STharun Kumar P pci1xxxx_i2c_send_start_stop(i2c, 0);
83036169369STharun Kumar P } else {
83136169369STharun Kumar P pci1xxxx_i2c_set_clear_FW_ACK(i2c, true);
83236169369STharun Kumar P }
83336169369STharun Kumar P
83436169369STharun Kumar P /* Send START bit for the first transaction. */
83536169369STharun Kumar P if (count == 0) {
83636169369STharun Kumar P pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE);
83736169369STharun Kumar P pci1xxxx_i2c_send_start_stop(i2c, 1);
83836169369STharun Kumar P
83936169369STharun Kumar P /* Write I2c buffer with just the slave addr. */
84036169369STharun Kumar P pci1xxxx_i2c_buffer_write(i2c, slaveaddr, 0, NULL);
84136169369STharun Kumar P
84236169369STharun Kumar P /* Set the count. Readcount is the transfer bytes. */
84336169369STharun Kumar P pci1xxxx_i2c_set_count(i2c, 1, 1, transferlen);
84436169369STharun Kumar P
84536169369STharun Kumar P /*
84636169369STharun Kumar P * Set the Auto_start_read bit so that the HW itself
84736169369STharun Kumar P * will take care of the read phase.
84836169369STharun Kumar P */
84936169369STharun Kumar P pci1xxxx_i2c_config_asr(i2c, true);
85036169369STharun Kumar P if (i2c->flags & I2C_FLAGS_SMB_BLK_READ)
85136169369STharun Kumar P pci1xxxx_i2c_set_readm(i2c, true);
85236169369STharun Kumar P } else {
85336169369STharun Kumar P pci1xxxx_i2c_set_count(i2c, 0, 0, transferlen);
85436169369STharun Kumar P pci1xxxx_i2c_config_asr(i2c, false);
85536169369STharun Kumar P pci1xxxx_i2c_clear_flags(i2c);
85636169369STharun Kumar P pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_READ);
85736169369STharun Kumar P }
85836169369STharun Kumar P
85936169369STharun Kumar P /* Start the DMA. */
86036169369STharun Kumar P pci1xxxx_i2c_start_DMA(i2c);
86136169369STharun Kumar P
86236169369STharun Kumar P /* Wait for the DMA_TERM interrupt. */
86336169369STharun Kumar P time_left = wait_for_completion_timeout(&i2c->i2c_xfer_done,
86436169369STharun Kumar P msecs_to_jiffies(PCI1XXXX_I2C_TIMEOUT_MS));
86536169369STharun Kumar P if (time_left == 0) {
86636169369STharun Kumar P /* Reset the I2C core to release the bus lock. */
86736169369STharun Kumar P pci1xxxx_i2c_init(i2c);
86836169369STharun Kumar P retval = -ETIMEDOUT;
86936169369STharun Kumar P goto cleanup;
87036169369STharun Kumar P }
87136169369STharun Kumar P
87236169369STharun Kumar P /* Read the completion reg to know the reason for DMA_TERM. */
87336169369STharun Kumar P regval = readb(p2);
87436169369STharun Kumar P
87536169369STharun Kumar P /* Slave did not respond. */
87636169369STharun Kumar P if (regval & COMPLETION_MNAKX) {
87736169369STharun Kumar P writeb(COMPLETION_MNAKX, p2);
87836169369STharun Kumar P retval = -ETIMEDOUT;
87936169369STharun Kumar P goto cleanup;
88036169369STharun Kumar P }
88136169369STharun Kumar P
88236169369STharun Kumar P if (i2c->flags & I2C_FLAGS_SMB_BLK_READ) {
88336169369STharun Kumar P buf[0] = readb(p3);
88436169369STharun Kumar P read_count = buf[0];
88536169369STharun Kumar P memcpy_fromio(&buf[1], p3 + 1, read_count);
88636169369STharun Kumar P } else {
88736169369STharun Kumar P memcpy_fromio(&buf[count], p3, transferlen);
88836169369STharun Kumar P }
88936169369STharun Kumar P }
89036169369STharun Kumar P
89136169369STharun Kumar P cleanup:
89236169369STharun Kumar P /* Disable all the interrupts. */
89336169369STharun Kumar P pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, false);
89436169369STharun Kumar P pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, false);
89536169369STharun Kumar P pci1xxxx_i2c_config_asr(i2c, false);
89636169369STharun Kumar P return retval;
89736169369STharun Kumar P }
89836169369STharun Kumar P
pci1xxxx_i2c_write(struct pci1xxxx_i2c * i2c,u8 slaveaddr,unsigned char * buf,u16 total_len)89936169369STharun Kumar P static int pci1xxxx_i2c_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr,
90036169369STharun Kumar P unsigned char *buf, u16 total_len)
90136169369STharun Kumar P {
90236169369STharun Kumar P void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3;
90336169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
90436169369STharun Kumar P unsigned long time_left;
90536169369STharun Kumar P u16 remainingbytes;
90636169369STharun Kumar P u8 actualwritelen;
90736169369STharun Kumar P u8 transferlen;
90836169369STharun Kumar P int retval = 0;
90936169369STharun Kumar P u32 regval;
91036169369STharun Kumar P u16 count;
91136169369STharun Kumar P
91236169369STharun Kumar P /* Enable I2C host controller by setting the ESO bit in the CONTROL REG. */
91336169369STharun Kumar P pci1xxxx_i2c_enable_ESO(i2c);
91436169369STharun Kumar P
91536169369STharun Kumar P /* Set the Buffer direction. */
91636169369STharun Kumar P pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE);
91736169369STharun Kumar P pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, true);
91836169369STharun Kumar P pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, true);
91936169369STharun Kumar P
92036169369STharun Kumar P /*
92136169369STharun Kumar P * The i2c transfer could be more than 128 bytes. Our Core is
92236169369STharun Kumar P * capable of only sending 128 at a time.
92336169369STharun Kumar P */
92436169369STharun Kumar P for (count = 0; count < total_len; count += transferlen) {
92536169369STharun Kumar P /*
92636169369STharun Kumar P * Before start of any transaction clear the existing
92736169369STharun Kumar P * START/STOP conditions.
92836169369STharun Kumar P */
92936169369STharun Kumar P writeb(0, p1);
93036169369STharun Kumar P pci1xxxx_i2c_clear_flags(i2c);
93136169369STharun Kumar P remainingbytes = total_len - count;
93236169369STharun Kumar P
93336169369STharun Kumar P /* If it is the starting of the transaction send START. */
93436169369STharun Kumar P if (count == 0) {
93536169369STharun Kumar P pci1xxxx_i2c_send_start_stop(i2c, 1);
93636169369STharun Kumar P
93736169369STharun Kumar P /* -1 for the slave address. */
93836169369STharun Kumar P transferlen = min_t(u16, SMBUS_BUF_MAX_SIZE - 1,
93936169369STharun Kumar P remainingbytes);
94036169369STharun Kumar P pci1xxxx_i2c_buffer_write(i2c, slaveaddr,
94136169369STharun Kumar P transferlen, &buf[count]);
94236169369STharun Kumar P /*
94336169369STharun Kumar P * The actual number of bytes written on the I2C bus
94436169369STharun Kumar P * is including the slave address.
94536169369STharun Kumar P */
94636169369STharun Kumar P actualwritelen = transferlen + 1;
94736169369STharun Kumar P } else {
94836169369STharun Kumar P transferlen = min_t(u16, SMBUS_BUF_MAX_SIZE, remainingbytes);
94936169369STharun Kumar P pci1xxxx_i2c_buffer_write(i2c, 0, transferlen, &buf[count]);
95036169369STharun Kumar P actualwritelen = transferlen;
95136169369STharun Kumar P }
95236169369STharun Kumar P
95336169369STharun Kumar P pci1xxxx_i2c_set_count(i2c, actualwritelen, actualwritelen, 0);
95436169369STharun Kumar P
95536169369STharun Kumar P /*
95636169369STharun Kumar P * Send STOP only when I2C_FLAGS_STOP bit is set in the flags and
95736169369STharun Kumar P * only for the last transaction.
95836169369STharun Kumar P */
95936169369STharun Kumar P if (remainingbytes <= transferlen &&
96036169369STharun Kumar P (i2c->flags & I2C_FLAGS_STOP))
96136169369STharun Kumar P pci1xxxx_i2c_send_start_stop(i2c, 0);
96236169369STharun Kumar P
96336169369STharun Kumar P pci1xxxx_i2c_start_DMA(i2c);
96436169369STharun Kumar P
96536169369STharun Kumar P /*
96636169369STharun Kumar P * Wait for the DMA_TERM interrupt.
96736169369STharun Kumar P */
96836169369STharun Kumar P time_left = wait_for_completion_timeout(&i2c->i2c_xfer_done,
96936169369STharun Kumar P msecs_to_jiffies(PCI1XXXX_I2C_TIMEOUT_MS));
97036169369STharun Kumar P if (time_left == 0) {
97136169369STharun Kumar P /* Reset the I2C core to release the bus lock. */
97236169369STharun Kumar P pci1xxxx_i2c_init(i2c);
97336169369STharun Kumar P retval = -ETIMEDOUT;
97436169369STharun Kumar P goto cleanup;
97536169369STharun Kumar P }
97636169369STharun Kumar P
97736169369STharun Kumar P regval = readb(p2);
97836169369STharun Kumar P if (regval & COMPLETION_MNAKX) {
97936169369STharun Kumar P writeb(COMPLETION_MNAKX, p2);
98036169369STharun Kumar P retval = -ETIMEDOUT;
98136169369STharun Kumar P goto cleanup;
98236169369STharun Kumar P }
98336169369STharun Kumar P }
98436169369STharun Kumar P cleanup:
98536169369STharun Kumar P /* Disable all the interrupts. */
98636169369STharun Kumar P pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, false);
98736169369STharun Kumar P pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, false);
98836169369STharun Kumar P
98936169369STharun Kumar P return retval;
99036169369STharun Kumar P }
99136169369STharun Kumar P
pci1xxxx_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)99236169369STharun Kumar P static int pci1xxxx_i2c_xfer(struct i2c_adapter *adap,
99336169369STharun Kumar P struct i2c_msg *msgs, int num)
99436169369STharun Kumar P {
99536169369STharun Kumar P struct pci1xxxx_i2c *i2c = i2c_get_adapdata(adap);
99636169369STharun Kumar P u8 slaveaddr;
99736169369STharun Kumar P int retval;
99836169369STharun Kumar P u32 i;
99936169369STharun Kumar P
100036169369STharun Kumar P i2c->i2c_xfer_in_progress = true;
100136169369STharun Kumar P for (i = 0; i < num; i++) {
100236169369STharun Kumar P slaveaddr = i2c_8bit_addr_from_msg(&msgs[i]);
100336169369STharun Kumar P
100436169369STharun Kumar P /*
100536169369STharun Kumar P * Send the STOP bit if the transfer is the final one or
100636169369STharun Kumar P * if the I2C_M_STOP flag is set.
100736169369STharun Kumar P */
100836169369STharun Kumar P if ((i == num - 1) || (msgs[i].flags & I2C_M_STOP))
100936169369STharun Kumar P i2c->flags |= I2C_FLAGS_STOP;
101036169369STharun Kumar P else
101136169369STharun Kumar P i2c->flags &= ~I2C_FLAGS_STOP;
101236169369STharun Kumar P
101336169369STharun Kumar P if (msgs[i].flags & I2C_M_RECV_LEN)
101436169369STharun Kumar P i2c->flags |= I2C_FLAGS_SMB_BLK_READ;
101536169369STharun Kumar P else
101636169369STharun Kumar P i2c->flags &= ~I2C_FLAGS_SMB_BLK_READ;
101736169369STharun Kumar P
101836169369STharun Kumar P if (msgs[i].flags & I2C_M_RD)
101936169369STharun Kumar P retval = pci1xxxx_i2c_read(i2c, slaveaddr,
102036169369STharun Kumar P msgs[i].buf, msgs[i].len);
102136169369STharun Kumar P else
102236169369STharun Kumar P retval = pci1xxxx_i2c_write(i2c, slaveaddr,
102336169369STharun Kumar P msgs[i].buf, msgs[i].len);
102436169369STharun Kumar P
102536169369STharun Kumar P if (retval < 0)
102636169369STharun Kumar P break;
102736169369STharun Kumar P }
102836169369STharun Kumar P i2c->i2c_xfer_in_progress = false;
102936169369STharun Kumar P
103036169369STharun Kumar P if (retval < 0)
103136169369STharun Kumar P return retval;
103236169369STharun Kumar P
103336169369STharun Kumar P return num;
103436169369STharun Kumar P }
103536169369STharun Kumar P
103636169369STharun Kumar P /*
103736169369STharun Kumar P * List of supported functions by the driver.
103836169369STharun Kumar P */
pci1xxxx_i2c_get_funcs(struct i2c_adapter * adap)103936169369STharun Kumar P static u32 pci1xxxx_i2c_get_funcs(struct i2c_adapter *adap)
104036169369STharun Kumar P {
104136169369STharun Kumar P return I2C_FUNC_I2C | I2C_FUNC_PROTOCOL_MANGLING |
104236169369STharun Kumar P I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
104336169369STharun Kumar P I2C_FUNC_SMBUS_BYTE |
104436169369STharun Kumar P I2C_FUNC_SMBUS_BYTE_DATA |
104536169369STharun Kumar P I2C_FUNC_SMBUS_WORD_DATA |
104636169369STharun Kumar P I2C_FUNC_SMBUS_PROC_CALL |
104736169369STharun Kumar P I2C_FUNC_SMBUS_BLOCK_DATA;
104836169369STharun Kumar P }
104936169369STharun Kumar P
105036169369STharun Kumar P static const struct i2c_algorithm pci1xxxx_i2c_algo = {
105136169369STharun Kumar P .master_xfer = pci1xxxx_i2c_xfer,
105236169369STharun Kumar P .functionality = pci1xxxx_i2c_get_funcs,
105336169369STharun Kumar P };
105436169369STharun Kumar P
105536169369STharun Kumar P static const struct i2c_adapter_quirks pci1xxxx_i2c_quirks = {
105636169369STharun Kumar P .flags = I2C_AQ_NO_ZERO_LEN,
105736169369STharun Kumar P };
105836169369STharun Kumar P
105936169369STharun Kumar P static const struct i2c_adapter pci1xxxx_i2c_ops = {
106036169369STharun Kumar P .owner = THIS_MODULE,
106136169369STharun Kumar P .name = "PCI1xxxx I2C Adapter",
106236169369STharun Kumar P .algo = &pci1xxxx_i2c_algo,
106336169369STharun Kumar P .quirks = &pci1xxxx_i2c_quirks,
106436169369STharun Kumar P };
106536169369STharun Kumar P
pci1xxxx_i2c_suspend(struct device * dev)106636169369STharun Kumar P static int pci1xxxx_i2c_suspend(struct device *dev)
106736169369STharun Kumar P {
106836169369STharun Kumar P struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev);
106936169369STharun Kumar P void __iomem *p = i2c->i2c_base + SMBUS_RESET_REG;
107036169369STharun Kumar P struct pci_dev *pdev = to_pci_dev(dev);
107136169369STharun Kumar P u32 regval;
107236169369STharun Kumar P
107336169369STharun Kumar P i2c_mark_adapter_suspended(&i2c->adap);
107436169369STharun Kumar P
107536169369STharun Kumar P /*
107636169369STharun Kumar P * If the system is put into 'suspend' state when the I2C transfer is in
107736169369STharun Kumar P * progress, wait until the transfer completes.
107836169369STharun Kumar P */
107936169369STharun Kumar P while (i2c->i2c_xfer_in_progress)
108036169369STharun Kumar P msleep(20);
108136169369STharun Kumar P
108236169369STharun Kumar P pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, true);
108336169369STharun Kumar P
108436169369STharun Kumar P /*
108536169369STharun Kumar P * Enable the PERST_DIS bit to mask the PERST from resetting the core
108636169369STharun Kumar P * registers.
108736169369STharun Kumar P */
108836169369STharun Kumar P regval = readl(p);
108936169369STharun Kumar P regval |= PERI_SMBUS_D3_RESET_DIS;
109036169369STharun Kumar P writel(regval, p);
109136169369STharun Kumar P
109236169369STharun Kumar P /* Enable PCI wake in the PMCSR register. */
109336169369STharun Kumar P device_set_wakeup_enable(dev, true);
109436169369STharun Kumar P pci_wake_from_d3(pdev, true);
109536169369STharun Kumar P
109636169369STharun Kumar P return 0;
109736169369STharun Kumar P }
109836169369STharun Kumar P
pci1xxxx_i2c_resume(struct device * dev)109936169369STharun Kumar P static int pci1xxxx_i2c_resume(struct device *dev)
110036169369STharun Kumar P {
110136169369STharun Kumar P struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev);
110236169369STharun Kumar P void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF;
110336169369STharun Kumar P void __iomem *p2 = i2c->i2c_base + SMBUS_RESET_REG;
110436169369STharun Kumar P struct pci_dev *pdev = to_pci_dev(dev);
110536169369STharun Kumar P u32 regval;
110636169369STharun Kumar P
110736169369STharun Kumar P regval = readw(p1);
110836169369STharun Kumar P writew(regval, p1);
110936169369STharun Kumar P pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, false);
111036169369STharun Kumar P regval = readl(p2);
111136169369STharun Kumar P regval &= ~PERI_SMBUS_D3_RESET_DIS;
111236169369STharun Kumar P writel(regval, p2);
111336169369STharun Kumar P i2c_mark_adapter_resumed(&i2c->adap);
111436169369STharun Kumar P pci_wake_from_d3(pdev, false);
111536169369STharun Kumar P return 0;
111636169369STharun Kumar P }
111736169369STharun Kumar P
111836169369STharun Kumar P static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_i2c_pm_ops, pci1xxxx_i2c_suspend,
111936169369STharun Kumar P pci1xxxx_i2c_resume);
112036169369STharun Kumar P
pci1xxxx_i2c_shutdown(void * data)1121*7ebfd881SSimon Horman static void pci1xxxx_i2c_shutdown(void *data)
112236169369STharun Kumar P {
1123*7ebfd881SSimon Horman struct pci1xxxx_i2c *i2c = data;
1124*7ebfd881SSimon Horman
112536169369STharun Kumar P pci1xxxx_i2c_config_padctrl(i2c, false);
112636169369STharun Kumar P pci1xxxx_i2c_configure_core_reg(i2c, false);
112736169369STharun Kumar P }
112836169369STharun Kumar P
pci1xxxx_i2c_probe_pci(struct pci_dev * pdev,const struct pci_device_id * ent)112936169369STharun Kumar P static int pci1xxxx_i2c_probe_pci(struct pci_dev *pdev,
113036169369STharun Kumar P const struct pci_device_id *ent)
113136169369STharun Kumar P {
113236169369STharun Kumar P struct device *dev = &pdev->dev;
113336169369STharun Kumar P struct pci1xxxx_i2c *i2c;
113436169369STharun Kumar P int ret;
113536169369STharun Kumar P
113636169369STharun Kumar P i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
113736169369STharun Kumar P if (!i2c)
113836169369STharun Kumar P return -ENOMEM;
113936169369STharun Kumar P
114036169369STharun Kumar P pci_set_drvdata(pdev, i2c);
114136169369STharun Kumar P i2c->i2c_xfer_in_progress = false;
114236169369STharun Kumar P
114336169369STharun Kumar P ret = pcim_enable_device(pdev);
114436169369STharun Kumar P if (ret)
114536169369STharun Kumar P return ret;
114636169369STharun Kumar P
114736169369STharun Kumar P pci_set_master(pdev);
114836169369STharun Kumar P
114936169369STharun Kumar P /*
115036169369STharun Kumar P * We are getting the base address of the SMB core. SMB core uses
115136169369STharun Kumar P * BAR0 and size is 32K.
115236169369STharun Kumar P */
115336169369STharun Kumar P ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
115436169369STharun Kumar P if (ret < 0)
115536169369STharun Kumar P return ret;
115636169369STharun Kumar P
115736169369STharun Kumar P i2c->i2c_base = pcim_iomap_table(pdev)[0];
115836169369STharun Kumar P init_completion(&i2c->i2c_xfer_done);
115936169369STharun Kumar P pci1xxxx_i2c_init(i2c);
116036169369STharun Kumar P
1161*7ebfd881SSimon Horman ret = devm_add_action(dev, pci1xxxx_i2c_shutdown, i2c);
116236169369STharun Kumar P if (ret)
116336169369STharun Kumar P return ret;
116436169369STharun Kumar P
116536169369STharun Kumar P ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
116636169369STharun Kumar P if (ret < 0)
116736169369STharun Kumar P return ret;
116836169369STharun Kumar P
116936169369STharun Kumar P ret = devm_request_irq(dev, pci_irq_vector(pdev, 0), pci1xxxx_i2c_isr,
117036169369STharun Kumar P 0, pci_name(pdev), i2c);
117136169369STharun Kumar P if (ret)
117236169369STharun Kumar P return ret;
117336169369STharun Kumar P
117436169369STharun Kumar P i2c->adap = pci1xxxx_i2c_ops;
117536169369STharun Kumar P i2c->adap.dev.parent = dev;
117636169369STharun Kumar P
117736169369STharun Kumar P snprintf(i2c->adap.name, sizeof(i2c->adap.name),
117836169369STharun Kumar P "MCHP PCI1xxxx i2c adapter at %s", pci_name(pdev));
117936169369STharun Kumar P
118036169369STharun Kumar P i2c_set_adapdata(&i2c->adap, i2c);
118136169369STharun Kumar P
118236169369STharun Kumar P ret = devm_i2c_add_adapter(dev, &i2c->adap);
118336169369STharun Kumar P if (ret)
118436169369STharun Kumar P return dev_err_probe(dev, ret, "i2c add adapter failed\n");
118536169369STharun Kumar P
118636169369STharun Kumar P return 0;
118736169369STharun Kumar P }
118836169369STharun Kumar P
118936169369STharun Kumar P static const struct pci_device_id pci1xxxx_i2c_pci_id_table[] = {
119036169369STharun Kumar P { PCI_VDEVICE(EFAR, 0xA003) },
119136169369STharun Kumar P { PCI_VDEVICE(EFAR, 0xA013) },
119236169369STharun Kumar P { PCI_VDEVICE(EFAR, 0xA023) },
119336169369STharun Kumar P { PCI_VDEVICE(EFAR, 0xA033) },
119436169369STharun Kumar P { PCI_VDEVICE(EFAR, 0xA043) },
119536169369STharun Kumar P { }
119636169369STharun Kumar P };
119736169369STharun Kumar P MODULE_DEVICE_TABLE(pci, pci1xxxx_i2c_pci_id_table);
119836169369STharun Kumar P
119936169369STharun Kumar P static struct pci_driver pci1xxxx_i2c_pci_driver = {
120036169369STharun Kumar P .name = "i2c-mchp-pci1xxxx",
120136169369STharun Kumar P .id_table = pci1xxxx_i2c_pci_id_table,
120236169369STharun Kumar P .probe = pci1xxxx_i2c_probe_pci,
120336169369STharun Kumar P .driver = {
120436169369STharun Kumar P .pm = pm_sleep_ptr(&pci1xxxx_i2c_pm_ops),
120536169369STharun Kumar P },
120636169369STharun Kumar P };
120736169369STharun Kumar P module_pci_driver(pci1xxxx_i2c_pci_driver);
120836169369STharun Kumar P
120936169369STharun Kumar P MODULE_LICENSE("GPL");
121036169369STharun Kumar P MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>");
121136169369STharun Kumar P MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
121236169369STharun Kumar P MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx I2C bus driver");
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