11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e1d5b659SRichard Röjfors /*
3e1d5b659SRichard Röjfors * i2c-xiic.c
4e1d5b659SRichard Röjfors * Copyright (c) 2002-2007 Xilinx Inc.
5e1d5b659SRichard Röjfors * Copyright (c) 2009-2010 Intel Corporation
6e1d5b659SRichard Röjfors *
7e1d5b659SRichard Röjfors * This code was implemented by Mocean Laboratories AB when porting linux
8e1d5b659SRichard Röjfors * to the automotive development board Russellville. The copyright holder
9e1d5b659SRichard Röjfors * as seen in the header is Intel corporation.
10e1d5b659SRichard Röjfors * Mocean Laboratories forked off the GNU/Linux platform work into a
1125985edcSLucas De Marchi * separate company called Pelagicore AB, which committed the code to the
12e1d5b659SRichard Röjfors * kernel.
13e1d5b659SRichard Röjfors */
14e1d5b659SRichard Röjfors
15e1d5b659SRichard Röjfors /* Supports:
16e1d5b659SRichard Röjfors * Xilinx IIC
17e1d5b659SRichard Röjfors */
18e1d5b659SRichard Röjfors #include <linux/kernel.h>
19e1d5b659SRichard Röjfors #include <linux/module.h>
20e1d5b659SRichard Röjfors #include <linux/errno.h>
21168e722dSKedareswara rao Appana #include <linux/err.h>
2202ca6c40SRandy Dunlap #include <linux/delay.h>
23e1d5b659SRichard Röjfors #include <linux/platform_device.h>
24e1d5b659SRichard Röjfors #include <linux/i2c.h>
25e1d5b659SRichard Röjfors #include <linux/interrupt.h>
26fdacc3c7SMarek Vasut #include <linux/completion.h>
277072b75cSWolfram Sang #include <linux/platform_data/i2c-xiic.h>
28e1d5b659SRichard Röjfors #include <linux/io.h>
295a0e3ad6STejun Heo #include <linux/slab.h>
304edd65e6SSachin Kamat #include <linux/of.h>
3136ecbcabSShubhrajyoti Datta #include <linux/clk.h>
3236ecbcabSShubhrajyoti Datta #include <linux/pm_runtime.h>
33e1d5b659SRichard Röjfors
34e1d5b659SRichard Röjfors #define DRIVER_NAME "xiic-i2c"
352fd5cf35SRaviteja Narayanam #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
36e4c1ff77SRaviteja Narayanam #define SMBUS_BLOCK_READ_MIN_LEN 3
37e1d5b659SRichard Röjfors
38e1d5b659SRichard Röjfors enum xilinx_i2c_state {
39e1d5b659SRichard Röjfors STATE_DONE,
40e1d5b659SRichard Röjfors STATE_ERROR,
41e1d5b659SRichard Röjfors STATE_START
42e1d5b659SRichard Röjfors };
43e1d5b659SRichard Röjfors
4448ef3ca9SThomas Gessler enum xiic_endian {
4548ef3ca9SThomas Gessler LITTLE,
4648ef3ca9SThomas Gessler BIG
4748ef3ca9SThomas Gessler };
4848ef3ca9SThomas Gessler
496d8ffbe6SRaviteja Narayanam enum i2c_scl_freq {
506d8ffbe6SRaviteja Narayanam REG_VALUES_100KHZ = 0,
516d8ffbe6SRaviteja Narayanam REG_VALUES_400KHZ = 1,
526d8ffbe6SRaviteja Narayanam REG_VALUES_1MHZ = 2
536d8ffbe6SRaviteja Narayanam };
546d8ffbe6SRaviteja Narayanam
55e1d5b659SRichard Röjfors /**
56e1d5b659SRichard Röjfors * struct xiic_i2c - Internal representation of the XIIC I2C bus
57bcc156e2SShubhrajyoti Datta * @dev: Pointer to device structure
58e1d5b659SRichard Röjfors * @base: Memory base of the HW registers
59fdacc3c7SMarek Vasut * @completion: Completion for callers
60e1d5b659SRichard Röjfors * @adap: Kernel adapter representation
61e1d5b659SRichard Röjfors * @tx_msg: Messages from above to be sent
62e1d5b659SRichard Röjfors * @lock: Mutual exclusion
63e1d5b659SRichard Röjfors * @tx_pos: Current pos in TX message
64e1d5b659SRichard Röjfors * @nmsgs: Number of messages in tx_msg
65e1d5b659SRichard Röjfors * @rx_msg: Current RX message
66e1d5b659SRichard Röjfors * @rx_pos: Position within current RX message
67bea6ff02SShubhrajyoti Datta * @endianness: big/little-endian byte order
68bcc156e2SShubhrajyoti Datta * @clk: Pointer to AXI4-lite input clock
699106e45cSJaakko Laine * @state: See STATE_
709e3b184bSJaakko Laine * @singlemaster: Indicates bus is single master
71acea4e44SRaviteja Narayanam * @dynamic: Mode of controller
72813eac4fSRaviteja Narayanam * @prev_msg_tx: Previous message is Tx
732fd5cf35SRaviteja Narayanam * @quirks: To hold platform specific bug info
74e4c1ff77SRaviteja Narayanam * @smbus_block_read: Flag to handle block read
756d8ffbe6SRaviteja Narayanam * @input_clk: Input clock to I2C controller
766d8ffbe6SRaviteja Narayanam * @i2c_clk: I2C SCL frequency
77e1d5b659SRichard Röjfors */
78e1d5b659SRichard Röjfors struct xiic_i2c {
7936ecbcabSShubhrajyoti Datta struct device *dev;
80e1d5b659SRichard Röjfors void __iomem *base;
81fdacc3c7SMarek Vasut struct completion completion;
82e1d5b659SRichard Röjfors struct i2c_adapter adap;
83e1d5b659SRichard Röjfors struct i2c_msg *tx_msg;
8477c68019SLars-Peter Clausen struct mutex lock;
85e1d5b659SRichard Röjfors unsigned int tx_pos;
86e1d5b659SRichard Röjfors unsigned int nmsgs;
87e1d5b659SRichard Röjfors struct i2c_msg *rx_msg;
88e1d5b659SRichard Röjfors int rx_pos;
8948ef3ca9SThomas Gessler enum xiic_endian endianness;
9036ecbcabSShubhrajyoti Datta struct clk *clk;
919106e45cSJaakko Laine enum xilinx_i2c_state state;
929e3b184bSJaakko Laine bool singlemaster;
93acea4e44SRaviteja Narayanam bool dynamic;
94813eac4fSRaviteja Narayanam bool prev_msg_tx;
952fd5cf35SRaviteja Narayanam u32 quirks;
96e4c1ff77SRaviteja Narayanam bool smbus_block_read;
976d8ffbe6SRaviteja Narayanam unsigned long input_clk;
986d8ffbe6SRaviteja Narayanam unsigned int i2c_clk;
992fd5cf35SRaviteja Narayanam };
1002fd5cf35SRaviteja Narayanam
1012fd5cf35SRaviteja Narayanam struct xiic_version_data {
1022fd5cf35SRaviteja Narayanam u32 quirks;
103e1d5b659SRichard Röjfors };
104e1d5b659SRichard Röjfors
1056d8ffbe6SRaviteja Narayanam /**
1066d8ffbe6SRaviteja Narayanam * struct timing_regs - AXI I2C timing registers that depend on I2C spec
1076d8ffbe6SRaviteja Narayanam * @tsusta: setup time for a repeated START condition
1086d8ffbe6SRaviteja Narayanam * @tsusto: setup time for a STOP condition
1096d8ffbe6SRaviteja Narayanam * @thdsta: hold time for a repeated START condition
1106d8ffbe6SRaviteja Narayanam * @tsudat: setup time for data
1116d8ffbe6SRaviteja Narayanam * @tbuf: bus free time between STOP and START
1126d8ffbe6SRaviteja Narayanam */
1136d8ffbe6SRaviteja Narayanam struct timing_regs {
1146d8ffbe6SRaviteja Narayanam unsigned int tsusta;
1156d8ffbe6SRaviteja Narayanam unsigned int tsusto;
1166d8ffbe6SRaviteja Narayanam unsigned int thdsta;
1176d8ffbe6SRaviteja Narayanam unsigned int tsudat;
1186d8ffbe6SRaviteja Narayanam unsigned int tbuf;
1196d8ffbe6SRaviteja Narayanam };
1206d8ffbe6SRaviteja Narayanam
1216d8ffbe6SRaviteja Narayanam /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
1226d8ffbe6SRaviteja Narayanam static const struct timing_regs timing_reg_values[] = {
1236d8ffbe6SRaviteja Narayanam { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */
1246d8ffbe6SRaviteja Narayanam { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */
1256d8ffbe6SRaviteja Narayanam { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */
1266d8ffbe6SRaviteja Narayanam };
1276d8ffbe6SRaviteja Narayanam
128e1d5b659SRichard Röjfors #define XIIC_MSB_OFFSET 0
129e1d5b659SRichard Röjfors #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
130e1d5b659SRichard Röjfors
131e1d5b659SRichard Röjfors /*
132e1d5b659SRichard Röjfors * Register offsets in bytes from RegisterBase. Three is added to the
133e1d5b659SRichard Röjfors * base offset to access LSB (IBM style) of the word
134e1d5b659SRichard Röjfors */
135e1d5b659SRichard Röjfors #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */
136e1d5b659SRichard Röjfors #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */
137e1d5b659SRichard Röjfors #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */
138e1d5b659SRichard Röjfors #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */
139e1d5b659SRichard Röjfors #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */
140e1d5b659SRichard Röjfors #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
141e1d5b659SRichard Röjfors #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
142e1d5b659SRichard Röjfors #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */
143e1d5b659SRichard Röjfors #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
144e1d5b659SRichard Röjfors #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */
145e1d5b659SRichard Röjfors
1466d8ffbe6SRaviteja Narayanam /*
1476d8ffbe6SRaviteja Narayanam * Timing register offsets from RegisterBase. These are used only for
1486d8ffbe6SRaviteja Narayanam * setting i2c clock frequency for the line.
1496d8ffbe6SRaviteja Narayanam */
1506d8ffbe6SRaviteja Narayanam #define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */
1516d8ffbe6SRaviteja Narayanam #define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */
1526d8ffbe6SRaviteja Narayanam #define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */
1536d8ffbe6SRaviteja Narayanam #define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */
1546d8ffbe6SRaviteja Narayanam #define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */
1556d8ffbe6SRaviteja Narayanam #define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */
1566d8ffbe6SRaviteja Narayanam #define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */
1576d8ffbe6SRaviteja Narayanam #define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */
1586d8ffbe6SRaviteja Narayanam
159e1d5b659SRichard Röjfors /* Control Register masks */
160e1d5b659SRichard Röjfors #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
161e1d5b659SRichard Röjfors #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
162e1d5b659SRichard Röjfors #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
163e1d5b659SRichard Röjfors #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
164e1d5b659SRichard Röjfors #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
165e1d5b659SRichard Röjfors #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
166e1d5b659SRichard Röjfors #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
167e1d5b659SRichard Röjfors
168e1d5b659SRichard Röjfors /* Status Register masks */
169e1d5b659SRichard Röjfors #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
170e1d5b659SRichard Röjfors #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
171e1d5b659SRichard Röjfors #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
172e1d5b659SRichard Röjfors #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
173e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
174e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
175e1d5b659SRichard Röjfors #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
176e1d5b659SRichard Röjfors #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
177e1d5b659SRichard Röjfors
178e1d5b659SRichard Röjfors /* Interrupt Status Register masks Interrupt occurs when... */
179e1d5b659SRichard Röjfors #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
180e1d5b659SRichard Röjfors #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
181e1d5b659SRichard Röjfors #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
182e1d5b659SRichard Röjfors #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
183e1d5b659SRichard Röjfors #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
184e1d5b659SRichard Röjfors #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
185e1d5b659SRichard Röjfors #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
186e1d5b659SRichard Röjfors #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
187e1d5b659SRichard Röjfors
188e1d5b659SRichard Röjfors /* The following constants specify the depth of the FIFOs */
189e1d5b659SRichard Röjfors #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
190e1d5b659SRichard Röjfors #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
191e1d5b659SRichard Röjfors
192e1d5b659SRichard Röjfors /* The following constants specify groups of interrupts that are typically
193e1d5b659SRichard Röjfors * enabled or disables at the same time
194e1d5b659SRichard Röjfors */
195e1d5b659SRichard Röjfors #define XIIC_TX_INTERRUPTS \
196e1d5b659SRichard Röjfors (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
197e1d5b659SRichard Röjfors
198e1d5b659SRichard Röjfors #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
199e1d5b659SRichard Röjfors
200e1d5b659SRichard Röjfors /*
201e1d5b659SRichard Röjfors * Tx Fifo upper bit masks.
202e1d5b659SRichard Röjfors */
203e1d5b659SRichard Röjfors #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
204e1d5b659SRichard Röjfors #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
205e1d5b659SRichard Röjfors
206acea4e44SRaviteja Narayanam /* Dynamic mode constants */
207acea4e44SRaviteja Narayanam #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */
208acea4e44SRaviteja Narayanam
209e1d5b659SRichard Röjfors /*
210e1d5b659SRichard Röjfors * The following constants define the register offsets for the Interrupt
211e1d5b659SRichard Röjfors * registers. There are some holes in the memory map for reserved addresses
212e1d5b659SRichard Röjfors * to allow other registers to be added and still match the memory map of the
213e1d5b659SRichard Röjfors * interrupt controller registers
214e1d5b659SRichard Röjfors */
215e1d5b659SRichard Röjfors #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
216e1d5b659SRichard Röjfors #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
217e1d5b659SRichard Röjfors #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
218e1d5b659SRichard Röjfors #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
219e1d5b659SRichard Röjfors
220e1d5b659SRichard Röjfors #define XIIC_RESET_MASK 0xAUL
221e1d5b659SRichard Röjfors
22236ecbcabSShubhrajyoti Datta #define XIIC_PM_TIMEOUT 1000 /* ms */
223b4c119dbSShubhrajyoti Datta /* timeout waiting for the controller to respond */
224b4c119dbSShubhrajyoti Datta #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
225fdacc3c7SMarek Vasut /* timeout waiting for the controller finish transfers */
226fdacc3c7SMarek Vasut #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000))
227fdacc3c7SMarek Vasut
228e1d5b659SRichard Röjfors /*
229e1d5b659SRichard Röjfors * The following constant is used for the device global interrupt enable
230e1d5b659SRichard Röjfors * register, to enable all interrupts for the device, this is the only bit
231e1d5b659SRichard Röjfors * in the register
232e1d5b659SRichard Röjfors */
233e1d5b659SRichard Röjfors #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
234e1d5b659SRichard Röjfors
235e1d5b659SRichard Röjfors #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
236e1d5b659SRichard Röjfors #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
237e1d5b659SRichard Röjfors
238c119e7d0SMarek Vasut static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
239e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c);
240e1d5b659SRichard Röjfors
24148ef3ca9SThomas Gessler /*
24248ef3ca9SThomas Gessler * For the register read and write functions, a little-endian and big-endian
24348ef3ca9SThomas Gessler * version are necessary. Endianness is detected during the probe function.
24448ef3ca9SThomas Gessler * Only the least significant byte [doublet] of the register are ever
24548ef3ca9SThomas Gessler * accessed. This requires an offset of 3 [2] from the base address for
24648ef3ca9SThomas Gessler * big-endian systems.
24748ef3ca9SThomas Gessler */
24848ef3ca9SThomas Gessler
xiic_setreg8(struct xiic_i2c * i2c,int reg,u8 value)249e1d5b659SRichard Röjfors static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
250e1d5b659SRichard Röjfors {
25148ef3ca9SThomas Gessler if (i2c->endianness == LITTLE)
252e1d5b659SRichard Röjfors iowrite8(value, i2c->base + reg);
25348ef3ca9SThomas Gessler else
25448ef3ca9SThomas Gessler iowrite8(value, i2c->base + reg + 3);
255e1d5b659SRichard Röjfors }
256e1d5b659SRichard Röjfors
xiic_getreg8(struct xiic_i2c * i2c,int reg)257e1d5b659SRichard Röjfors static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
258e1d5b659SRichard Röjfors {
25948ef3ca9SThomas Gessler u8 ret;
26048ef3ca9SThomas Gessler
26148ef3ca9SThomas Gessler if (i2c->endianness == LITTLE)
26248ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg);
26348ef3ca9SThomas Gessler else
26448ef3ca9SThomas Gessler ret = ioread8(i2c->base + reg + 3);
26548ef3ca9SThomas Gessler return ret;
266e1d5b659SRichard Röjfors }
267e1d5b659SRichard Röjfors
xiic_setreg16(struct xiic_i2c * i2c,int reg,u16 value)268e1d5b659SRichard Röjfors static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
269e1d5b659SRichard Röjfors {
27048ef3ca9SThomas Gessler if (i2c->endianness == LITTLE)
271e1d5b659SRichard Röjfors iowrite16(value, i2c->base + reg);
27248ef3ca9SThomas Gessler else
27348ef3ca9SThomas Gessler iowrite16be(value, i2c->base + reg + 2);
274e1d5b659SRichard Röjfors }
275e1d5b659SRichard Röjfors
xiic_setreg32(struct xiic_i2c * i2c,int reg,int value)276e1d5b659SRichard Röjfors static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
277e1d5b659SRichard Röjfors {
27848ef3ca9SThomas Gessler if (i2c->endianness == LITTLE)
279e1d5b659SRichard Röjfors iowrite32(value, i2c->base + reg);
28048ef3ca9SThomas Gessler else
28148ef3ca9SThomas Gessler iowrite32be(value, i2c->base + reg);
282e1d5b659SRichard Röjfors }
283e1d5b659SRichard Röjfors
xiic_getreg32(struct xiic_i2c * i2c,int reg)284e1d5b659SRichard Röjfors static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
285e1d5b659SRichard Röjfors {
28648ef3ca9SThomas Gessler u32 ret;
28748ef3ca9SThomas Gessler
28848ef3ca9SThomas Gessler if (i2c->endianness == LITTLE)
28948ef3ca9SThomas Gessler ret = ioread32(i2c->base + reg);
29048ef3ca9SThomas Gessler else
29148ef3ca9SThomas Gessler ret = ioread32be(i2c->base + reg);
29248ef3ca9SThomas Gessler return ret;
293e1d5b659SRichard Röjfors }
294e1d5b659SRichard Röjfors
xiic_irq_dis(struct xiic_i2c * i2c,u32 mask)295e1d5b659SRichard Röjfors static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
296e1d5b659SRichard Röjfors {
297e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
298b822039bSMichal Simek
299e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
300e1d5b659SRichard Röjfors }
301e1d5b659SRichard Röjfors
xiic_irq_en(struct xiic_i2c * i2c,u32 mask)302e1d5b659SRichard Röjfors static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
303e1d5b659SRichard Röjfors {
304e1d5b659SRichard Röjfors u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
305b822039bSMichal Simek
306e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
307e1d5b659SRichard Röjfors }
308e1d5b659SRichard Röjfors
xiic_irq_clr(struct xiic_i2c * i2c,u32 mask)309e1d5b659SRichard Röjfors static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
310e1d5b659SRichard Röjfors {
311e1d5b659SRichard Röjfors u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
312b822039bSMichal Simek
313e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
314e1d5b659SRichard Röjfors }
315e1d5b659SRichard Röjfors
xiic_irq_clr_en(struct xiic_i2c * i2c,u32 mask)316e1d5b659SRichard Röjfors static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
317e1d5b659SRichard Röjfors {
318e1d5b659SRichard Röjfors xiic_irq_clr(i2c, mask);
319e1d5b659SRichard Röjfors xiic_irq_en(i2c, mask);
320e1d5b659SRichard Röjfors }
321e1d5b659SRichard Röjfors
xiic_clear_rx_fifo(struct xiic_i2c * i2c)322b4c119dbSShubhrajyoti Datta static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
323e1d5b659SRichard Röjfors {
324e1d5b659SRichard Röjfors u8 sr;
325b4c119dbSShubhrajyoti Datta unsigned long timeout;
326b4c119dbSShubhrajyoti Datta
327b4c119dbSShubhrajyoti Datta timeout = jiffies + XIIC_I2C_TIMEOUT;
328e1d5b659SRichard Röjfors for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
329e1d5b659SRichard Röjfors !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
330b4c119dbSShubhrajyoti Datta sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
331e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
332b4c119dbSShubhrajyoti Datta if (time_after(jiffies, timeout)) {
333b4c119dbSShubhrajyoti Datta dev_err(i2c->dev, "Failed to clear rx fifo\n");
334b4c119dbSShubhrajyoti Datta return -ETIMEDOUT;
335b4c119dbSShubhrajyoti Datta }
336e1d5b659SRichard Röjfors }
337e1d5b659SRichard Röjfors
338b4c119dbSShubhrajyoti Datta return 0;
339b4c119dbSShubhrajyoti Datta }
340b4c119dbSShubhrajyoti Datta
xiic_wait_tx_empty(struct xiic_i2c * i2c)341813eac4fSRaviteja Narayanam static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
342813eac4fSRaviteja Narayanam {
343813eac4fSRaviteja Narayanam u8 isr;
344813eac4fSRaviteja Narayanam unsigned long timeout;
345813eac4fSRaviteja Narayanam
346813eac4fSRaviteja Narayanam timeout = jiffies + XIIC_I2C_TIMEOUT;
347813eac4fSRaviteja Narayanam for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
348813eac4fSRaviteja Narayanam !(isr & XIIC_INTR_TX_EMPTY_MASK);
349813eac4fSRaviteja Narayanam isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
350813eac4fSRaviteja Narayanam if (time_after(jiffies, timeout)) {
351813eac4fSRaviteja Narayanam dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
352813eac4fSRaviteja Narayanam return -ETIMEDOUT;
353813eac4fSRaviteja Narayanam }
354813eac4fSRaviteja Narayanam }
355813eac4fSRaviteja Narayanam
356813eac4fSRaviteja Narayanam return 0;
357813eac4fSRaviteja Narayanam }
358813eac4fSRaviteja Narayanam
3596d8ffbe6SRaviteja Narayanam /**
3606d8ffbe6SRaviteja Narayanam * xiic_setclk - Sets the configured clock rate
3616d8ffbe6SRaviteja Narayanam * @i2c: Pointer to the xiic device structure
3626d8ffbe6SRaviteja Narayanam *
3636d8ffbe6SRaviteja Narayanam * The timing register values are calculated according to the input clock
3646d8ffbe6SRaviteja Narayanam * frequency and configured scl frequency. For details, please refer the
3656d8ffbe6SRaviteja Narayanam * AXI I2C PG and NXP I2C Spec.
3666d8ffbe6SRaviteja Narayanam * Supported frequencies are 100KHz, 400KHz and 1MHz.
3676d8ffbe6SRaviteja Narayanam *
3686d8ffbe6SRaviteja Narayanam * Return: 0 on success (Supported frequency selected or not configurable in SW)
3696d8ffbe6SRaviteja Narayanam * -EINVAL on failure (scl frequency not supported or THIGH is 0)
3706d8ffbe6SRaviteja Narayanam */
xiic_setclk(struct xiic_i2c * i2c)3716d8ffbe6SRaviteja Narayanam static int xiic_setclk(struct xiic_i2c *i2c)
3726d8ffbe6SRaviteja Narayanam {
3736d8ffbe6SRaviteja Narayanam unsigned int clk_in_mhz;
3746d8ffbe6SRaviteja Narayanam unsigned int index = 0;
3756d8ffbe6SRaviteja Narayanam u32 reg_val;
3766d8ffbe6SRaviteja Narayanam
3776d8ffbe6SRaviteja Narayanam dev_dbg(i2c->adap.dev.parent,
3786d8ffbe6SRaviteja Narayanam "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
3796d8ffbe6SRaviteja Narayanam __func__, i2c->input_clk, i2c->i2c_clk);
3806d8ffbe6SRaviteja Narayanam
3816d8ffbe6SRaviteja Narayanam /* If not specified in DT, do not configure in SW. Rely only on Vivado design */
3826d8ffbe6SRaviteja Narayanam if (!i2c->i2c_clk || !i2c->input_clk)
3836d8ffbe6SRaviteja Narayanam return 0;
3846d8ffbe6SRaviteja Narayanam
3856d8ffbe6SRaviteja Narayanam clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
3866d8ffbe6SRaviteja Narayanam
3876d8ffbe6SRaviteja Narayanam switch (i2c->i2c_clk) {
3886d8ffbe6SRaviteja Narayanam case I2C_MAX_FAST_MODE_PLUS_FREQ:
3896d8ffbe6SRaviteja Narayanam index = REG_VALUES_1MHZ;
3906d8ffbe6SRaviteja Narayanam break;
3916d8ffbe6SRaviteja Narayanam case I2C_MAX_FAST_MODE_FREQ:
3926d8ffbe6SRaviteja Narayanam index = REG_VALUES_400KHZ;
3936d8ffbe6SRaviteja Narayanam break;
3946d8ffbe6SRaviteja Narayanam case I2C_MAX_STANDARD_MODE_FREQ:
3956d8ffbe6SRaviteja Narayanam index = REG_VALUES_100KHZ;
3966d8ffbe6SRaviteja Narayanam break;
3976d8ffbe6SRaviteja Narayanam default:
3986d8ffbe6SRaviteja Narayanam dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
3996d8ffbe6SRaviteja Narayanam return -EINVAL;
4006d8ffbe6SRaviteja Narayanam }
4016d8ffbe6SRaviteja Narayanam
4026d8ffbe6SRaviteja Narayanam /*
4036d8ffbe6SRaviteja Narayanam * Value to be stored in a register is the number of clock cycles required
4046d8ffbe6SRaviteja Narayanam * for the time duration. So the time is divided by the input clock time
4056d8ffbe6SRaviteja Narayanam * period to get the number of clock cycles required. Refer Xilinx AXI I2C
4066d8ffbe6SRaviteja Narayanam * PG document and I2C specification for further details.
4076d8ffbe6SRaviteja Narayanam */
4086d8ffbe6SRaviteja Narayanam
4096d8ffbe6SRaviteja Narayanam /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */
4106d8ffbe6SRaviteja Narayanam reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
4116d8ffbe6SRaviteja Narayanam if (reg_val == 0)
4126d8ffbe6SRaviteja Narayanam return -EINVAL;
4136d8ffbe6SRaviteja Narayanam
4146d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
4156d8ffbe6SRaviteja Narayanam
4166d8ffbe6SRaviteja Narayanam /* TLOW - Value same as THIGH */
4176d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
4186d8ffbe6SRaviteja Narayanam
4196d8ffbe6SRaviteja Narayanam /* TSUSTA */
4206d8ffbe6SRaviteja Narayanam reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;
4216d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
4226d8ffbe6SRaviteja Narayanam
4236d8ffbe6SRaviteja Narayanam /* TSUSTO */
4246d8ffbe6SRaviteja Narayanam reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;
4256d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
4266d8ffbe6SRaviteja Narayanam
4276d8ffbe6SRaviteja Narayanam /* THDSTA */
4286d8ffbe6SRaviteja Narayanam reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;
4296d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
4306d8ffbe6SRaviteja Narayanam
4316d8ffbe6SRaviteja Narayanam /* TSUDAT */
4326d8ffbe6SRaviteja Narayanam reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;
4336d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
4346d8ffbe6SRaviteja Narayanam
4356d8ffbe6SRaviteja Narayanam /* TBUF */
4366d8ffbe6SRaviteja Narayanam reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;
4376d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
4386d8ffbe6SRaviteja Narayanam
4396d8ffbe6SRaviteja Narayanam /* THDDAT */
4406d8ffbe6SRaviteja Narayanam xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
4416d8ffbe6SRaviteja Narayanam
4426d8ffbe6SRaviteja Narayanam return 0;
4436d8ffbe6SRaviteja Narayanam }
4446d8ffbe6SRaviteja Narayanam
xiic_reinit(struct xiic_i2c * i2c)445b4c119dbSShubhrajyoti Datta static int xiic_reinit(struct xiic_i2c *i2c)
446e1d5b659SRichard Röjfors {
447b4c119dbSShubhrajyoti Datta int ret;
448b4c119dbSShubhrajyoti Datta
449e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
450e1d5b659SRichard Röjfors
4516d8ffbe6SRaviteja Narayanam ret = xiic_setclk(i2c);
4526d8ffbe6SRaviteja Narayanam if (ret)
4536d8ffbe6SRaviteja Narayanam return ret;
4546d8ffbe6SRaviteja Narayanam
455e1d5b659SRichard Röjfors /* Set receive Fifo depth to maximum (zero based). */
456e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
457e1d5b659SRichard Röjfors
458e1d5b659SRichard Röjfors /* Reset Tx Fifo. */
459e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
460e1d5b659SRichard Röjfors
461e1d5b659SRichard Röjfors /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
462e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
463e1d5b659SRichard Röjfors
464e1d5b659SRichard Röjfors /* make sure RX fifo is empty */
465b4c119dbSShubhrajyoti Datta ret = xiic_clear_rx_fifo(i2c);
466b4c119dbSShubhrajyoti Datta if (ret)
467b4c119dbSShubhrajyoti Datta return ret;
468e1d5b659SRichard Röjfors
469e1d5b659SRichard Röjfors /* Enable interrupts */
470e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
471e1d5b659SRichard Röjfors
472542e2a9bSShubhrajyoti Datta xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
473b4c119dbSShubhrajyoti Datta
474b4c119dbSShubhrajyoti Datta return 0;
475e1d5b659SRichard Röjfors }
476e1d5b659SRichard Röjfors
xiic_deinit(struct xiic_i2c * i2c)477e1d5b659SRichard Röjfors static void xiic_deinit(struct xiic_i2c *i2c)
478e1d5b659SRichard Röjfors {
479e1d5b659SRichard Röjfors u8 cr;
480e1d5b659SRichard Röjfors
481e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
482e1d5b659SRichard Röjfors
483e1d5b659SRichard Röjfors /* Disable IIC Device. */
484e1d5b659SRichard Röjfors cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
485e1d5b659SRichard Röjfors xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
486e1d5b659SRichard Röjfors }
487e1d5b659SRichard Röjfors
xiic_smbus_block_read_setup(struct xiic_i2c * i2c)488e4c1ff77SRaviteja Narayanam static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
489e4c1ff77SRaviteja Narayanam {
490e4c1ff77SRaviteja Narayanam u8 rxmsg_len, rfd_set = 0;
491e4c1ff77SRaviteja Narayanam
492e4c1ff77SRaviteja Narayanam /*
493e4c1ff77SRaviteja Narayanam * Clear the I2C_M_RECV_LEN flag to avoid setting
494e4c1ff77SRaviteja Narayanam * message length again
495e4c1ff77SRaviteja Narayanam */
496e4c1ff77SRaviteja Narayanam i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
497e4c1ff77SRaviteja Narayanam
498e4c1ff77SRaviteja Narayanam /* Set smbus_block_read flag to identify in isr */
499e4c1ff77SRaviteja Narayanam i2c->smbus_block_read = true;
500e4c1ff77SRaviteja Narayanam
501e4c1ff77SRaviteja Narayanam /* Read byte from rx fifo and set message length */
502e4c1ff77SRaviteja Narayanam rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
503e4c1ff77SRaviteja Narayanam
504e4c1ff77SRaviteja Narayanam i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
505e4c1ff77SRaviteja Narayanam
506e4c1ff77SRaviteja Narayanam /* Check if received length is valid */
507e4c1ff77SRaviteja Narayanam if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) {
508e4c1ff77SRaviteja Narayanam /* Set Receive fifo depth */
509e4c1ff77SRaviteja Narayanam if (rxmsg_len > IIC_RX_FIFO_DEPTH) {
510e4c1ff77SRaviteja Narayanam /*
511e4c1ff77SRaviteja Narayanam * When Rx msg len greater than or equal to Rx fifo capacity
512e4c1ff77SRaviteja Narayanam * Receive fifo depth should set to Rx fifo capacity minus 1
513e4c1ff77SRaviteja Narayanam */
514e4c1ff77SRaviteja Narayanam rfd_set = IIC_RX_FIFO_DEPTH - 1;
515e4c1ff77SRaviteja Narayanam i2c->rx_msg->len = rxmsg_len + 1;
516e4c1ff77SRaviteja Narayanam } else if ((rxmsg_len == 1) ||
517e4c1ff77SRaviteja Narayanam (rxmsg_len == 0)) {
518e4c1ff77SRaviteja Narayanam /*
519e4c1ff77SRaviteja Narayanam * Minimum of 3 bytes required to exit cleanly. 1 byte
520e4c1ff77SRaviteja Narayanam * already received, Second byte is being received. Have
521e4c1ff77SRaviteja Narayanam * to set NACK in read_rx before receiving the last byte
522e4c1ff77SRaviteja Narayanam */
523e4c1ff77SRaviteja Narayanam rfd_set = 0;
524e4c1ff77SRaviteja Narayanam i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
525e4c1ff77SRaviteja Narayanam } else {
526e4c1ff77SRaviteja Narayanam /*
527e4c1ff77SRaviteja Narayanam * When Rx msg len less than Rx fifo capacity
528e4c1ff77SRaviteja Narayanam * Receive fifo depth should set to Rx msg len minus 2
529e4c1ff77SRaviteja Narayanam */
530e4c1ff77SRaviteja Narayanam rfd_set = rxmsg_len - 2;
531e4c1ff77SRaviteja Narayanam i2c->rx_msg->len = rxmsg_len + 1;
532e4c1ff77SRaviteja Narayanam }
533e4c1ff77SRaviteja Narayanam xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
534e4c1ff77SRaviteja Narayanam
535e4c1ff77SRaviteja Narayanam return;
536e4c1ff77SRaviteja Narayanam }
537e4c1ff77SRaviteja Narayanam
538e4c1ff77SRaviteja Narayanam /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */
539e4c1ff77SRaviteja Narayanam i2c->tx_msg->len = 3;
540e4c1ff77SRaviteja Narayanam i2c->smbus_block_read = false;
541e4c1ff77SRaviteja Narayanam dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
542e4c1ff77SRaviteja Narayanam }
543e4c1ff77SRaviteja Narayanam
xiic_read_rx(struct xiic_i2c * i2c)544e1d5b659SRichard Röjfors static void xiic_read_rx(struct xiic_i2c *i2c)
545e1d5b659SRichard Röjfors {
546acea4e44SRaviteja Narayanam u8 bytes_in_fifo, cr = 0, bytes_to_read = 0;
547acea4e44SRaviteja Narayanam u32 bytes_rem = 0;
548e1d5b659SRichard Röjfors int i;
549e1d5b659SRichard Röjfors
550e1d5b659SRichard Röjfors bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
551e1d5b659SRichard Röjfors
552f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent,
553acea4e44SRaviteja Narayanam "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n",
554e1d5b659SRichard Röjfors __func__, bytes_in_fifo, xiic_rx_space(i2c),
555e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
556e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
557e1d5b659SRichard Röjfors
558e1d5b659SRichard Röjfors if (bytes_in_fifo > xiic_rx_space(i2c))
559e1d5b659SRichard Röjfors bytes_in_fifo = xiic_rx_space(i2c);
560e1d5b659SRichard Röjfors
561acea4e44SRaviteja Narayanam bytes_to_read = bytes_in_fifo;
562acea4e44SRaviteja Narayanam
563acea4e44SRaviteja Narayanam if (!i2c->dynamic) {
564acea4e44SRaviteja Narayanam bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
565acea4e44SRaviteja Narayanam
566e4c1ff77SRaviteja Narayanam /* Set msg length if smbus_block_read */
567e4c1ff77SRaviteja Narayanam if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
568e4c1ff77SRaviteja Narayanam xiic_smbus_block_read_setup(i2c);
569e4c1ff77SRaviteja Narayanam return;
570e4c1ff77SRaviteja Narayanam }
571e4c1ff77SRaviteja Narayanam
572acea4e44SRaviteja Narayanam if (bytes_rem > IIC_RX_FIFO_DEPTH) {
573acea4e44SRaviteja Narayanam bytes_to_read = bytes_in_fifo;
574acea4e44SRaviteja Narayanam } else if (bytes_rem > 1) {
575acea4e44SRaviteja Narayanam bytes_to_read = bytes_rem - 1;
576acea4e44SRaviteja Narayanam } else if (bytes_rem == 1) {
577acea4e44SRaviteja Narayanam bytes_to_read = 1;
578acea4e44SRaviteja Narayanam /* Set NACK in CR to indicate slave transmitter */
579acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
580acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
581acea4e44SRaviteja Narayanam XIIC_CR_NO_ACK_MASK);
582acea4e44SRaviteja Narayanam } else if (bytes_rem == 0) {
583acea4e44SRaviteja Narayanam bytes_to_read = bytes_in_fifo;
584acea4e44SRaviteja Narayanam
585acea4e44SRaviteja Narayanam /* Generate stop on the bus if it is last message */
586acea4e44SRaviteja Narayanam if (i2c->nmsgs == 1) {
587acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
588acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
589acea4e44SRaviteja Narayanam ~XIIC_CR_MSMS_MASK);
590acea4e44SRaviteja Narayanam }
591acea4e44SRaviteja Narayanam
592acea4e44SRaviteja Narayanam /* Make TXACK=0, clean up for next transaction */
593acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
594acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
595acea4e44SRaviteja Narayanam ~XIIC_CR_NO_ACK_MASK);
596acea4e44SRaviteja Narayanam }
597acea4e44SRaviteja Narayanam }
598acea4e44SRaviteja Narayanam
599acea4e44SRaviteja Narayanam /* Read the fifo */
600acea4e44SRaviteja Narayanam for (i = 0; i < bytes_to_read; i++) {
601e1d5b659SRichard Röjfors i2c->rx_msg->buf[i2c->rx_pos++] =
602e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
603acea4e44SRaviteja Narayanam }
604e1d5b659SRichard Röjfors
605acea4e44SRaviteja Narayanam if (i2c->dynamic) {
606acea4e44SRaviteja Narayanam u8 bytes;
607acea4e44SRaviteja Narayanam
608acea4e44SRaviteja Narayanam /* Receive remaining bytes if less than fifo depth */
609acea4e44SRaviteja Narayanam bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH);
610acea4e44SRaviteja Narayanam bytes--;
611acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
612acea4e44SRaviteja Narayanam }
613e1d5b659SRichard Röjfors }
614e1d5b659SRichard Röjfors
xiic_tx_fifo_space(struct xiic_i2c * i2c)615e1d5b659SRichard Röjfors static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
616e1d5b659SRichard Röjfors {
617e1d5b659SRichard Röjfors /* return the actual space left in the FIFO */
618e1d5b659SRichard Röjfors return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
619e1d5b659SRichard Röjfors }
620e1d5b659SRichard Röjfors
xiic_fill_tx_fifo(struct xiic_i2c * i2c)621e1d5b659SRichard Röjfors static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
622e1d5b659SRichard Röjfors {
623e1d5b659SRichard Röjfors u8 fifo_space = xiic_tx_fifo_space(i2c);
624e1d5b659SRichard Röjfors int len = xiic_tx_space(i2c);
625e1d5b659SRichard Röjfors
626e1d5b659SRichard Röjfors len = (len > fifo_space) ? fifo_space : len;
627e1d5b659SRichard Röjfors
628e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
629e1d5b659SRichard Röjfors __func__, len, fifo_space);
630e1d5b659SRichard Röjfors
631e1d5b659SRichard Röjfors while (len--) {
632e1d5b659SRichard Röjfors u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
633b822039bSMichal Simek
634b822039bSMichal Simek if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
635e1d5b659SRichard Röjfors /* last message in transfer -> STOP */
636acea4e44SRaviteja Narayanam if (i2c->dynamic) {
637e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK;
638acea4e44SRaviteja Narayanam } else {
639acea4e44SRaviteja Narayanam u8 cr;
640317b56c9SRaviteja Narayanam int status;
641317b56c9SRaviteja Narayanam
642317b56c9SRaviteja Narayanam /* Wait till FIFO is empty so STOP is sent last */
643317b56c9SRaviteja Narayanam status = xiic_wait_tx_empty(i2c);
644317b56c9SRaviteja Narayanam if (status)
645317b56c9SRaviteja Narayanam return;
646317b56c9SRaviteja Narayanam
647acea4e44SRaviteja Narayanam /* Write to CR to stop */
648acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
649acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
650acea4e44SRaviteja Narayanam ~XIIC_CR_MSMS_MASK);
651acea4e44SRaviteja Narayanam }
652e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
653c39e8e43SSteven A. Falco }
654e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
655e1d5b659SRichard Röjfors }
656e1d5b659SRichard Röjfors }
657e1d5b659SRichard Röjfors
xiic_wakeup(struct xiic_i2c * i2c,enum xilinx_i2c_state code)658e749e4fcSShubhrajyoti Datta static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
659e1d5b659SRichard Röjfors {
660e1d5b659SRichard Röjfors i2c->tx_msg = NULL;
661e1d5b659SRichard Röjfors i2c->rx_msg = NULL;
662e1d5b659SRichard Röjfors i2c->nmsgs = 0;
663e1d5b659SRichard Röjfors i2c->state = code;
664fdacc3c7SMarek Vasut complete(&i2c->completion);
665e1d5b659SRichard Röjfors }
666e1d5b659SRichard Röjfors
xiic_process(int irq,void * dev_id)667fcc2fac6SShubhrajyoti Datta static irqreturn_t xiic_process(int irq, void *dev_id)
668e1d5b659SRichard Röjfors {
669fcc2fac6SShubhrajyoti Datta struct xiic_i2c *i2c = dev_id;
670e1d5b659SRichard Röjfors u32 pend, isr, ier;
671e1d5b659SRichard Röjfors u32 clr = 0;
672743e227aSMarek Vasut int xfer_more = 0;
673743e227aSMarek Vasut int wakeup_req = 0;
674e749e4fcSShubhrajyoti Datta enum xilinx_i2c_state wakeup_code = STATE_DONE;
6758fa9c938SShubhrajyoti Datta int ret;
676e1d5b659SRichard Röjfors
677e1d5b659SRichard Röjfors /* Get the interrupt Status from the IPIF. There is no clearing of
678e1d5b659SRichard Röjfors * interrupts in the IPIF. Interrupts must be cleared at the source.
679e1d5b659SRichard Röjfors * To find which interrupts are pending; AND interrupts pending with
680e1d5b659SRichard Röjfors * interrupts masked.
681e1d5b659SRichard Röjfors */
68277c68019SLars-Peter Clausen mutex_lock(&i2c->lock);
683e1d5b659SRichard Röjfors isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
684e1d5b659SRichard Röjfors ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
685e1d5b659SRichard Röjfors pend = isr & ier;
686e1d5b659SRichard Röjfors
687f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
688f1e9f89aSKedareswara rao Appana __func__, ier, isr, pend);
689f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
690f1e9f89aSKedareswara rao Appana __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
691e1d5b659SRichard Röjfors i2c->tx_msg, i2c->nmsgs);
692acea4e44SRaviteja Narayanam dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n",
693acea4e44SRaviteja Narayanam __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
694acea4e44SRaviteja Narayanam xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
695e1d5b659SRichard Röjfors
696e1d5b659SRichard Röjfors /* Service requesting interrupt */
697e1d5b659SRichard Röjfors if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
698e1d5b659SRichard Röjfors ((pend & XIIC_INTR_TX_ERROR_MASK) &&
699e1d5b659SRichard Röjfors !(pend & XIIC_INTR_RX_FULL_MASK))) {
700e1d5b659SRichard Röjfors /* bus arbritration lost, or...
701e1d5b659SRichard Röjfors * Transmit error _OR_ RX completed
702e1d5b659SRichard Röjfors * if this happens when RX_FULL is not set
703e1d5b659SRichard Röjfors * this is probably a TX error
704e1d5b659SRichard Röjfors */
705e1d5b659SRichard Röjfors
706e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
707e1d5b659SRichard Röjfors
708e1d5b659SRichard Röjfors /* dynamic mode seem to suffer from problems if we just flushes
709e1d5b659SRichard Röjfors * fifos and the next message is a TX with len 0 (only addr)
710e1d5b659SRichard Röjfors * reset the IP instead of just flush fifos
711e1d5b659SRichard Röjfors */
7128fa9c938SShubhrajyoti Datta ret = xiic_reinit(i2c);
713*59851fb0SDaniel Scally if (ret < 0)
7148fa9c938SShubhrajyoti Datta dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
715e1d5b659SRichard Röjfors
716743e227aSMarek Vasut if (i2c->rx_msg) {
717743e227aSMarek Vasut wakeup_req = 1;
718743e227aSMarek Vasut wakeup_code = STATE_ERROR;
719743e227aSMarek Vasut }
720743e227aSMarek Vasut if (i2c->tx_msg) {
721743e227aSMarek Vasut wakeup_req = 1;
722743e227aSMarek Vasut wakeup_code = STATE_ERROR;
723743e227aSMarek Vasut }
724cb6e45c9SRobert Hancock /* don't try to handle other events */
725cb6e45c9SRobert Hancock goto out;
7267f9906bdSShubhrajyoti Datta }
7277f9906bdSShubhrajyoti Datta if (pend & XIIC_INTR_RX_FULL_MASK) {
728e1d5b659SRichard Röjfors /* Receive register/FIFO is full */
729e1d5b659SRichard Röjfors
7307f9906bdSShubhrajyoti Datta clr |= XIIC_INTR_RX_FULL_MASK;
731e1d5b659SRichard Röjfors if (!i2c->rx_msg) {
732e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent,
7331ee7cdbfSColin Ian King "%s unexpected RX IRQ\n", __func__);
734e1d5b659SRichard Röjfors xiic_clear_rx_fifo(i2c);
735e1d5b659SRichard Röjfors goto out;
736e1d5b659SRichard Röjfors }
737e1d5b659SRichard Röjfors
738e1d5b659SRichard Röjfors xiic_read_rx(i2c);
739e1d5b659SRichard Röjfors if (xiic_rx_space(i2c) == 0) {
740e1d5b659SRichard Röjfors /* this is the last part of the message */
741e1d5b659SRichard Röjfors i2c->rx_msg = NULL;
742e1d5b659SRichard Röjfors
743e1d5b659SRichard Röjfors /* also clear TX error if there (RX complete) */
744e1d5b659SRichard Röjfors clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
745e1d5b659SRichard Röjfors
746e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent,
747e1d5b659SRichard Röjfors "%s end of message, nmsgs: %d\n",
748e1d5b659SRichard Röjfors __func__, i2c->nmsgs);
749e1d5b659SRichard Röjfors
750e1d5b659SRichard Röjfors /* send next message if this wasn't the last,
751e1d5b659SRichard Röjfors * otherwise the transfer will be finialise when
752e1d5b659SRichard Röjfors * receiving the bus not busy interrupt
753e1d5b659SRichard Röjfors */
754e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) {
755e1d5b659SRichard Röjfors i2c->nmsgs--;
756e1d5b659SRichard Röjfors i2c->tx_msg++;
757e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent,
758e1d5b659SRichard Röjfors "%s will start next...\n", __func__);
759743e227aSMarek Vasut xfer_more = 1;
760e1d5b659SRichard Röjfors }
761e1d5b659SRichard Röjfors }
7627f9906bdSShubhrajyoti Datta }
7637f9906bdSShubhrajyoti Datta if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
764d36b6910SAl Viro /* Transmit register/FIFO is empty or ½ empty */
765e1d5b659SRichard Röjfors
7667f9906bdSShubhrajyoti Datta clr |= (pend &
7677f9906bdSShubhrajyoti Datta (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
768e1d5b659SRichard Röjfors
769e1d5b659SRichard Röjfors if (!i2c->tx_msg) {
770e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent,
7711ee7cdbfSColin Ian King "%s unexpected TX IRQ\n", __func__);
772e1d5b659SRichard Röjfors goto out;
773e1d5b659SRichard Röjfors }
774e1d5b659SRichard Röjfors
775e1d5b659SRichard Röjfors xiic_fill_tx_fifo(i2c);
776e1d5b659SRichard Röjfors
777e1d5b659SRichard Röjfors /* current message sent and there is space in the fifo */
778e1d5b659SRichard Röjfors if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
779e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent,
780e1d5b659SRichard Röjfors "%s end of message sent, nmsgs: %d\n",
781e1d5b659SRichard Röjfors __func__, i2c->nmsgs);
782e1d5b659SRichard Röjfors if (i2c->nmsgs > 1) {
783e1d5b659SRichard Röjfors i2c->nmsgs--;
784e1d5b659SRichard Röjfors i2c->tx_msg++;
785743e227aSMarek Vasut xfer_more = 1;
786e1d5b659SRichard Röjfors } else {
787e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
788e1d5b659SRichard Röjfors
789e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent,
790e1d5b659SRichard Röjfors "%s Got TX IRQ but no more to do...\n",
791e1d5b659SRichard Röjfors __func__);
792e1d5b659SRichard Röjfors }
793e1d5b659SRichard Röjfors } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
794e1d5b659SRichard Röjfors /* current frame is sent and is last,
795e1d5b659SRichard Röjfors * make sure to disable tx half
796e1d5b659SRichard Röjfors */
797e1d5b659SRichard Röjfors xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
798e1d5b659SRichard Röjfors }
7994bca93abSRaviteja Narayanam
8004bca93abSRaviteja Narayanam if (pend & XIIC_INTR_BNB_MASK) {
8014bca93abSRaviteja Narayanam /* IIC bus has transitioned to not busy */
8024bca93abSRaviteja Narayanam clr |= XIIC_INTR_BNB_MASK;
8034bca93abSRaviteja Narayanam
8044bca93abSRaviteja Narayanam /* The bus is not busy, disable BusNotBusy interrupt */
8054bca93abSRaviteja Narayanam xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
8064bca93abSRaviteja Narayanam
807e4c1ff77SRaviteja Narayanam if (i2c->tx_msg && i2c->smbus_block_read) {
808e4c1ff77SRaviteja Narayanam i2c->smbus_block_read = false;
809e4c1ff77SRaviteja Narayanam /* Set requested message len=1 to indicate STATE_DONE */
810e4c1ff77SRaviteja Narayanam i2c->tx_msg->len = 1;
811e4c1ff77SRaviteja Narayanam }
812e4c1ff77SRaviteja Narayanam
8134bca93abSRaviteja Narayanam if (!i2c->tx_msg)
8144bca93abSRaviteja Narayanam goto out;
8154bca93abSRaviteja Narayanam
8164bca93abSRaviteja Narayanam wakeup_req = 1;
8174bca93abSRaviteja Narayanam
8184bca93abSRaviteja Narayanam if (i2c->nmsgs == 1 && !i2c->rx_msg &&
8194bca93abSRaviteja Narayanam xiic_tx_space(i2c) == 0)
8204bca93abSRaviteja Narayanam wakeup_code = STATE_DONE;
8214bca93abSRaviteja Narayanam else
8224bca93abSRaviteja Narayanam wakeup_code = STATE_ERROR;
8234bca93abSRaviteja Narayanam }
8244bca93abSRaviteja Narayanam
825e1d5b659SRichard Röjfors out:
826e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
827e1d5b659SRichard Röjfors
828e1d5b659SRichard Röjfors xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
829743e227aSMarek Vasut if (xfer_more)
830743e227aSMarek Vasut __xiic_start_xfer(i2c);
831743e227aSMarek Vasut if (wakeup_req)
832743e227aSMarek Vasut xiic_wakeup(i2c, wakeup_code);
833743e227aSMarek Vasut
834743e227aSMarek Vasut WARN_ON(xfer_more && wakeup_req);
835743e227aSMarek Vasut
83677c68019SLars-Peter Clausen mutex_unlock(&i2c->lock);
837fcc2fac6SShubhrajyoti Datta return IRQ_HANDLED;
838e1d5b659SRichard Röjfors }
839e1d5b659SRichard Röjfors
xiic_bus_busy(struct xiic_i2c * i2c)840e1d5b659SRichard Röjfors static int xiic_bus_busy(struct xiic_i2c *i2c)
841e1d5b659SRichard Röjfors {
842e1d5b659SRichard Röjfors u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
843e1d5b659SRichard Röjfors
844e1d5b659SRichard Röjfors return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
845e1d5b659SRichard Röjfors }
846e1d5b659SRichard Röjfors
xiic_busy(struct xiic_i2c * i2c)847e1d5b659SRichard Röjfors static int xiic_busy(struct xiic_i2c *i2c)
848e1d5b659SRichard Röjfors {
849e1d5b659SRichard Röjfors int tries = 3;
850e1d5b659SRichard Röjfors int err;
851e1d5b659SRichard Röjfors
852294b29f1SMarek Vasut if (i2c->tx_msg || i2c->rx_msg)
853e1d5b659SRichard Röjfors return -EBUSY;
854e1d5b659SRichard Röjfors
8559e3b184bSJaakko Laine /* In single master mode bus can only be busy, when in use by this
8569e3b184bSJaakko Laine * driver. If the register indicates bus being busy for some reason we
8579e3b184bSJaakko Laine * should ignore it, since bus will never be released and i2c will be
8589e3b184bSJaakko Laine * stuck forever.
8599e3b184bSJaakko Laine */
8609e3b184bSJaakko Laine if (i2c->singlemaster) {
8619e3b184bSJaakko Laine return 0;
8629e3b184bSJaakko Laine }
8639e3b184bSJaakko Laine
864e1d5b659SRichard Röjfors /* for instance if previous transfer was terminated due to TX error
865e1d5b659SRichard Röjfors * it might be that the bus is on it's way to become available
866e1d5b659SRichard Röjfors * give it at most 3 ms to wake
867e1d5b659SRichard Röjfors */
868e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c);
869e1d5b659SRichard Röjfors while (err && tries--) {
870b33aa252SShubhrajyoti Datta msleep(1);
871e1d5b659SRichard Röjfors err = xiic_bus_busy(i2c);
872e1d5b659SRichard Röjfors }
873e1d5b659SRichard Röjfors
874e1d5b659SRichard Röjfors return err;
875e1d5b659SRichard Röjfors }
876e1d5b659SRichard Röjfors
xiic_start_recv(struct xiic_i2c * i2c)877e1d5b659SRichard Röjfors static void xiic_start_recv(struct xiic_i2c *i2c)
878e1d5b659SRichard Röjfors {
8793c9fedf9SShubhrajyoti Datta u16 rx_watermark;
880acea4e44SRaviteja Narayanam u8 cr = 0, rfd_set = 0;
881e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
882acea4e44SRaviteja Narayanam
883acea4e44SRaviteja Narayanam dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
884acea4e44SRaviteja Narayanam __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
885acea4e44SRaviteja Narayanam xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
886acea4e44SRaviteja Narayanam
887acea4e44SRaviteja Narayanam /* Disable Tx interrupts */
888acea4e44SRaviteja Narayanam xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK);
889acea4e44SRaviteja Narayanam
890acea4e44SRaviteja Narayanam if (i2c->dynamic) {
891acea4e44SRaviteja Narayanam u8 bytes;
892acea4e44SRaviteja Narayanam u16 val;
893e1d5b659SRichard Röjfors
894e1d5b659SRichard Röjfors /* Clear and enable Rx full interrupt. */
895acea4e44SRaviteja Narayanam xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
896acea4e44SRaviteja Narayanam XIIC_INTR_TX_ERROR_MASK);
897e1d5b659SRichard Röjfors
898acea4e44SRaviteja Narayanam /*
899acea4e44SRaviteja Narayanam * We want to get all but last byte, because the TX_ERROR IRQ
900acea4e44SRaviteja Narayanam * is used to indicate error ACK on the address, and
901acea4e44SRaviteja Narayanam * negative ack on the last received byte, so to not mix
902acea4e44SRaviteja Narayanam * them receive all but last.
903e1d5b659SRichard Röjfors * In the case where there is only one byte to receive
904e1d5b659SRichard Röjfors * we can check if ERROR and RX full is set at the same time
905e1d5b659SRichard Röjfors */
906e1d5b659SRichard Röjfors rx_watermark = msg->len;
907acea4e44SRaviteja Narayanam bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH);
908e1d5b659SRichard Röjfors
909acea4e44SRaviteja Narayanam if (rx_watermark > 0)
910acea4e44SRaviteja Narayanam bytes--;
911acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
912acea4e44SRaviteja Narayanam
913e1d5b659SRichard Röjfors /* write the address */
914e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
915acea4e44SRaviteja Narayanam i2c_8bit_addr_from_msg(msg) |
916acea4e44SRaviteja Narayanam XIIC_TX_DYN_START_MASK);
917acea4e44SRaviteja Narayanam
918acea4e44SRaviteja Narayanam /* If last message, include dynamic stop bit with length */
919acea4e44SRaviteja Narayanam val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
920acea4e44SRaviteja Narayanam val |= msg->len;
921acea4e44SRaviteja Narayanam
922acea4e44SRaviteja Narayanam xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
923e1d5b659SRichard Röjfors
924e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
925acea4e44SRaviteja Narayanam } else {
926813eac4fSRaviteja Narayanam /*
927813eac4fSRaviteja Narayanam * If previous message is Tx, make sure that Tx FIFO is empty
928813eac4fSRaviteja Narayanam * before starting a new transfer as the repeated start in
929813eac4fSRaviteja Narayanam * standard mode can corrupt the transaction if there are
930813eac4fSRaviteja Narayanam * still bytes to be transmitted in FIFO
931813eac4fSRaviteja Narayanam */
932813eac4fSRaviteja Narayanam if (i2c->prev_msg_tx) {
933813eac4fSRaviteja Narayanam int status;
934813eac4fSRaviteja Narayanam
935813eac4fSRaviteja Narayanam status = xiic_wait_tx_empty(i2c);
936813eac4fSRaviteja Narayanam if (status)
937813eac4fSRaviteja Narayanam return;
938813eac4fSRaviteja Narayanam }
939813eac4fSRaviteja Narayanam
940acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
941acea4e44SRaviteja Narayanam
942acea4e44SRaviteja Narayanam /* Set Receive fifo depth */
943acea4e44SRaviteja Narayanam rx_watermark = msg->len;
944acea4e44SRaviteja Narayanam if (rx_watermark > IIC_RX_FIFO_DEPTH) {
945acea4e44SRaviteja Narayanam rfd_set = IIC_RX_FIFO_DEPTH - 1;
946acea4e44SRaviteja Narayanam } else if (rx_watermark == 1) {
947acea4e44SRaviteja Narayanam rfd_set = rx_watermark - 1;
948e4c1ff77SRaviteja Narayanam
949e4c1ff77SRaviteja Narayanam /* Set No_ACK, except for smbus_block_read */
950e4c1ff77SRaviteja Narayanam if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
951acea4e44SRaviteja Narayanam /* Handle single byte transfer separately */
952acea4e44SRaviteja Narayanam cr |= XIIC_CR_NO_ACK_MASK;
953e4c1ff77SRaviteja Narayanam }
954acea4e44SRaviteja Narayanam } else if (rx_watermark == 0) {
955acea4e44SRaviteja Narayanam rfd_set = rx_watermark;
956acea4e44SRaviteja Narayanam } else {
957acea4e44SRaviteja Narayanam rfd_set = rx_watermark - 2;
958acea4e44SRaviteja Narayanam }
959acea4e44SRaviteja Narayanam /* Check if RSTA should be set */
960acea4e44SRaviteja Narayanam if (cr & XIIC_CR_MSMS_MASK) {
961acea4e44SRaviteja Narayanam /* Already a master, RSTA should be set */
962acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
963acea4e44SRaviteja Narayanam XIIC_CR_REPEATED_START_MASK) &
964acea4e44SRaviteja Narayanam ~(XIIC_CR_DIR_IS_TX_MASK));
965acea4e44SRaviteja Narayanam }
966acea4e44SRaviteja Narayanam
967acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
968acea4e44SRaviteja Narayanam
969acea4e44SRaviteja Narayanam /* Clear and enable Rx full and transmit complete interrupts */
970acea4e44SRaviteja Narayanam xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
971acea4e44SRaviteja Narayanam XIIC_INTR_TX_ERROR_MASK);
972acea4e44SRaviteja Narayanam
973acea4e44SRaviteja Narayanam /* Write the address */
974e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
975acea4e44SRaviteja Narayanam i2c_8bit_addr_from_msg(msg));
976acea4e44SRaviteja Narayanam
977acea4e44SRaviteja Narayanam /* Write to Control Register,to start transaction in Rx mode */
978acea4e44SRaviteja Narayanam if ((cr & XIIC_CR_MSMS_MASK) == 0) {
979acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
980acea4e44SRaviteja Narayanam XIIC_CR_MSMS_MASK)
981acea4e44SRaviteja Narayanam & ~(XIIC_CR_DIR_IS_TX_MASK));
982acea4e44SRaviteja Narayanam }
983acea4e44SRaviteja Narayanam dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
984acea4e44SRaviteja Narayanam __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
985acea4e44SRaviteja Narayanam xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
986acea4e44SRaviteja Narayanam }
987ae7304c3SShubhrajyoti Datta
988e1d5b659SRichard Röjfors if (i2c->nmsgs == 1)
989e1d5b659SRichard Röjfors /* very last, enable bus not busy as well */
990e1d5b659SRichard Röjfors xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
991e1d5b659SRichard Röjfors
992e1d5b659SRichard Röjfors /* the message is tx:ed */
993e1d5b659SRichard Röjfors i2c->tx_pos = msg->len;
994acea4e44SRaviteja Narayanam
995acea4e44SRaviteja Narayanam /* Enable interrupts */
996acea4e44SRaviteja Narayanam xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
997813eac4fSRaviteja Narayanam
998813eac4fSRaviteja Narayanam i2c->prev_msg_tx = false;
999e1d5b659SRichard Röjfors }
1000e1d5b659SRichard Röjfors
xiic_start_send(struct xiic_i2c * i2c)1001e1d5b659SRichard Röjfors static void xiic_start_send(struct xiic_i2c *i2c)
1002e1d5b659SRichard Röjfors {
1003acea4e44SRaviteja Narayanam u8 cr = 0;
1004acea4e44SRaviteja Narayanam u16 data;
1005e1d5b659SRichard Röjfors struct i2c_msg *msg = i2c->tx_msg;
1006e1d5b659SRichard Röjfors
1007f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
1008f1e9f89aSKedareswara rao Appana __func__, msg, msg->len);
1009f1e9f89aSKedareswara rao Appana dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
1010f1e9f89aSKedareswara rao Appana __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1011e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1012e1d5b659SRichard Röjfors
1013acea4e44SRaviteja Narayanam if (i2c->dynamic) {
1014e1d5b659SRichard Röjfors /* write the address */
1015acea4e44SRaviteja Narayanam data = i2c_8bit_addr_from_msg(msg) |
1016e1d5b659SRichard Röjfors XIIC_TX_DYN_START_MASK;
1017acea4e44SRaviteja Narayanam
1018acea4e44SRaviteja Narayanam if (i2c->nmsgs == 1 && msg->len == 0)
1019e1d5b659SRichard Röjfors /* no data and last message -> add STOP */
1020e1d5b659SRichard Röjfors data |= XIIC_TX_DYN_STOP_MASK;
1021e1d5b659SRichard Röjfors
1022e1d5b659SRichard Röjfors xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1023e1d5b659SRichard Röjfors
1024acea4e44SRaviteja Narayanam /* Clear any pending Tx empty, Tx Error and then enable them */
1025acea4e44SRaviteja Narayanam xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1026acea4e44SRaviteja Narayanam XIIC_INTR_TX_ERROR_MASK |
1027d12e4bbbSMarek Vasut XIIC_INTR_BNB_MASK |
1028d12e4bbbSMarek Vasut ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
1029d12e4bbbSMarek Vasut XIIC_INTR_TX_HALF_MASK : 0));
1030d12e4bbbSMarek Vasut
1031d12e4bbbSMarek Vasut xiic_fill_tx_fifo(i2c);
1032acea4e44SRaviteja Narayanam } else {
1033813eac4fSRaviteja Narayanam /*
1034813eac4fSRaviteja Narayanam * If previous message is Tx, make sure that Tx FIFO is empty
1035813eac4fSRaviteja Narayanam * before starting a new transfer as the repeated start in
1036813eac4fSRaviteja Narayanam * standard mode can corrupt the transaction if there are
1037813eac4fSRaviteja Narayanam * still bytes to be transmitted in FIFO
1038813eac4fSRaviteja Narayanam */
1039813eac4fSRaviteja Narayanam if (i2c->prev_msg_tx) {
1040813eac4fSRaviteja Narayanam int status;
1041813eac4fSRaviteja Narayanam
1042813eac4fSRaviteja Narayanam status = xiic_wait_tx_empty(i2c);
1043813eac4fSRaviteja Narayanam if (status)
1044813eac4fSRaviteja Narayanam return;
1045813eac4fSRaviteja Narayanam }
1046acea4e44SRaviteja Narayanam /* Check if RSTA should be set */
1047acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1048acea4e44SRaviteja Narayanam if (cr & XIIC_CR_MSMS_MASK) {
1049acea4e44SRaviteja Narayanam /* Already a master, RSTA should be set */
1050acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1051acea4e44SRaviteja Narayanam XIIC_CR_REPEATED_START_MASK |
1052acea4e44SRaviteja Narayanam XIIC_CR_DIR_IS_TX_MASK) &
1053acea4e44SRaviteja Narayanam ~(XIIC_CR_NO_ACK_MASK));
1054acea4e44SRaviteja Narayanam }
1055acea4e44SRaviteja Narayanam
1056acea4e44SRaviteja Narayanam /* Write address to FIFO */
1057acea4e44SRaviteja Narayanam data = i2c_8bit_addr_from_msg(msg);
1058acea4e44SRaviteja Narayanam xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1059acea4e44SRaviteja Narayanam
1060acea4e44SRaviteja Narayanam /* Fill fifo */
1061acea4e44SRaviteja Narayanam xiic_fill_tx_fifo(i2c);
1062acea4e44SRaviteja Narayanam
1063acea4e44SRaviteja Narayanam if ((cr & XIIC_CR_MSMS_MASK) == 0) {
1064acea4e44SRaviteja Narayanam /* Start Tx by writing to CR */
1065acea4e44SRaviteja Narayanam cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1066acea4e44SRaviteja Narayanam xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
1067acea4e44SRaviteja Narayanam XIIC_CR_MSMS_MASK |
1068acea4e44SRaviteja Narayanam XIIC_CR_DIR_IS_TX_MASK);
1069acea4e44SRaviteja Narayanam }
1070acea4e44SRaviteja Narayanam
1071acea4e44SRaviteja Narayanam /* Clear any pending Tx empty, Tx Error and then enable them */
1072acea4e44SRaviteja Narayanam xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1073acea4e44SRaviteja Narayanam XIIC_INTR_TX_ERROR_MASK |
1074acea4e44SRaviteja Narayanam XIIC_INTR_BNB_MASK);
1075acea4e44SRaviteja Narayanam }
1076813eac4fSRaviteja Narayanam i2c->prev_msg_tx = true;
1077e1d5b659SRichard Röjfors }
1078e1d5b659SRichard Röjfors
__xiic_start_xfer(struct xiic_i2c * i2c)1079e1d5b659SRichard Röjfors static void __xiic_start_xfer(struct xiic_i2c *i2c)
1080e1d5b659SRichard Röjfors {
1081e1d5b659SRichard Röjfors int fifo_space = xiic_tx_fifo_space(i2c);
1082b822039bSMichal Simek
1083e1d5b659SRichard Röjfors dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1084e1d5b659SRichard Röjfors __func__, i2c->tx_msg, fifo_space);
1085e1d5b659SRichard Röjfors
1086e1d5b659SRichard Röjfors if (!i2c->tx_msg)
1087e1d5b659SRichard Röjfors return;
1088e1d5b659SRichard Röjfors
1089e1d5b659SRichard Röjfors i2c->rx_pos = 0;
1090e1d5b659SRichard Röjfors i2c->tx_pos = 0;
1091e1d5b659SRichard Röjfors i2c->state = STATE_START;
1092e1d5b659SRichard Röjfors if (i2c->tx_msg->flags & I2C_M_RD) {
1093e1d5b659SRichard Röjfors /* we dont date putting several reads in the FIFO */
1094e1d5b659SRichard Röjfors xiic_start_recv(i2c);
1095e1d5b659SRichard Röjfors } else {
1096e1d5b659SRichard Röjfors xiic_start_send(i2c);
1097e1d5b659SRichard Röjfors }
1098e1d5b659SRichard Röjfors }
1099e1d5b659SRichard Röjfors
xiic_start_xfer(struct xiic_i2c * i2c,struct i2c_msg * msgs,int num)1100c119e7d0SMarek Vasut static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
1101e1d5b659SRichard Röjfors {
11022fd5cf35SRaviteja Narayanam bool broken_read, max_read_len, smbus_blk_read;
11032fd5cf35SRaviteja Narayanam int ret, count;
1104c119e7d0SMarek Vasut
110577c68019SLars-Peter Clausen mutex_lock(&i2c->lock);
1106b4c119dbSShubhrajyoti Datta
1107c119e7d0SMarek Vasut ret = xiic_busy(i2c);
1108c119e7d0SMarek Vasut if (ret)
1109c119e7d0SMarek Vasut goto out;
1110c119e7d0SMarek Vasut
1111c119e7d0SMarek Vasut i2c->tx_msg = msgs;
1112c119e7d0SMarek Vasut i2c->rx_msg = NULL;
1113c119e7d0SMarek Vasut i2c->nmsgs = num;
1114fdacc3c7SMarek Vasut init_completion(&i2c->completion);
1115c119e7d0SMarek Vasut
11162fd5cf35SRaviteja Narayanam /* Decide standard mode or Dynamic mode */
11172fd5cf35SRaviteja Narayanam i2c->dynamic = true;
11182fd5cf35SRaviteja Narayanam
11192fd5cf35SRaviteja Narayanam /* Initialize prev message type */
11202fd5cf35SRaviteja Narayanam i2c->prev_msg_tx = false;
11212fd5cf35SRaviteja Narayanam
11222fd5cf35SRaviteja Narayanam /*
11232fd5cf35SRaviteja Narayanam * Scan through nmsgs, use dynamic mode when none of the below three
11242fd5cf35SRaviteja Narayanam * conditions occur. We need standard mode even if one condition holds
11252fd5cf35SRaviteja Narayanam * true in the entire array of messages in a single transfer.
11262fd5cf35SRaviteja Narayanam * If read transaction as dynamic mode is broken for delayed reads
11272fd5cf35SRaviteja Narayanam * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions.
11282fd5cf35SRaviteja Narayanam * If read length is > 255 bytes.
11292fd5cf35SRaviteja Narayanam * If smbus_block_read transaction.
11302fd5cf35SRaviteja Narayanam */
11312fd5cf35SRaviteja Narayanam for (count = 0; count < i2c->nmsgs; count++) {
11322fd5cf35SRaviteja Narayanam broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
11332fd5cf35SRaviteja Narayanam (i2c->tx_msg[count].flags & I2C_M_RD);
11342fd5cf35SRaviteja Narayanam max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
11352fd5cf35SRaviteja Narayanam (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
11362fd5cf35SRaviteja Narayanam smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
11372fd5cf35SRaviteja Narayanam
11382fd5cf35SRaviteja Narayanam if (broken_read || max_read_len || smbus_blk_read) {
11392fd5cf35SRaviteja Narayanam i2c->dynamic = false;
11402fd5cf35SRaviteja Narayanam break;
11412fd5cf35SRaviteja Narayanam }
11422fd5cf35SRaviteja Narayanam }
11432fd5cf35SRaviteja Narayanam
1144b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c);
1145b4c119dbSShubhrajyoti Datta if (!ret)
1146e1d5b659SRichard Röjfors __xiic_start_xfer(i2c);
1147b4c119dbSShubhrajyoti Datta
1148c119e7d0SMarek Vasut out:
114977c68019SLars-Peter Clausen mutex_unlock(&i2c->lock);
1150b4c119dbSShubhrajyoti Datta
1151b4c119dbSShubhrajyoti Datta return ret;
1152e1d5b659SRichard Röjfors }
1153e1d5b659SRichard Röjfors
xiic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1154e1d5b659SRichard Röjfors static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1155e1d5b659SRichard Röjfors {
1156e1d5b659SRichard Röjfors struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1157e1d5b659SRichard Röjfors int err;
1158e1d5b659SRichard Röjfors
1159e1d5b659SRichard Röjfors dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
1160e1d5b659SRichard Röjfors xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
1161e1d5b659SRichard Röjfors
1162a85c5c7aSQinglang Miao err = pm_runtime_resume_and_get(i2c->dev);
116336ecbcabSShubhrajyoti Datta if (err < 0)
116436ecbcabSShubhrajyoti Datta return err;
116536ecbcabSShubhrajyoti Datta
1166c119e7d0SMarek Vasut err = xiic_start_xfer(i2c, msgs, num);
1167b4c119dbSShubhrajyoti Datta if (err < 0) {
1168b4c119dbSShubhrajyoti Datta dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
1169d663d93bSLars-Peter Clausen goto out;
1170b4c119dbSShubhrajyoti Datta }
1171e1d5b659SRichard Röjfors
1172fdacc3c7SMarek Vasut err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
1173c119e7d0SMarek Vasut mutex_lock(&i2c->lock);
1174fdacc3c7SMarek Vasut if (err == 0) { /* Timeout */
1175e1d5b659SRichard Röjfors i2c->tx_msg = NULL;
1176e1d5b659SRichard Röjfors i2c->rx_msg = NULL;
1177e1d5b659SRichard Röjfors i2c->nmsgs = 0;
117836ecbcabSShubhrajyoti Datta err = -ETIMEDOUT;
1179fdacc3c7SMarek Vasut } else {
1180fdacc3c7SMarek Vasut err = (i2c->state == STATE_DONE) ? num : -EIO;
1181e1d5b659SRichard Röjfors }
1182c119e7d0SMarek Vasut mutex_unlock(&i2c->lock);
1183d663d93bSLars-Peter Clausen
1184d663d93bSLars-Peter Clausen out:
118536ecbcabSShubhrajyoti Datta pm_runtime_mark_last_busy(i2c->dev);
118636ecbcabSShubhrajyoti Datta pm_runtime_put_autosuspend(i2c->dev);
118736ecbcabSShubhrajyoti Datta return err;
1188e1d5b659SRichard Röjfors }
1189e1d5b659SRichard Röjfors
xiic_func(struct i2c_adapter * adap)1190e1d5b659SRichard Röjfors static u32 xiic_func(struct i2c_adapter *adap)
1191e1d5b659SRichard Röjfors {
1192e4c1ff77SRaviteja Narayanam return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
1193e1d5b659SRichard Röjfors }
1194e1d5b659SRichard Röjfors
1195e1d5b659SRichard Röjfors static const struct i2c_algorithm xiic_algorithm = {
1196e1d5b659SRichard Röjfors .master_xfer = xiic_xfer,
1197e1d5b659SRichard Röjfors .functionality = xiic_func,
1198e1d5b659SRichard Röjfors };
1199e1d5b659SRichard Röjfors
1200329430ccSBhumika Goyal static const struct i2c_adapter xiic_adapter = {
1201e1d5b659SRichard Röjfors .owner = THIS_MODULE,
12024db5beedSWolfram Sang .class = I2C_CLASS_DEPRECATED,
1203e1d5b659SRichard Röjfors .algo = &xiic_algorithm,
1204e1d5b659SRichard Röjfors };
1205e1d5b659SRichard Röjfors
120658c043d9SKrzysztof Kozlowski #if defined(CONFIG_OF)
12072fd5cf35SRaviteja Narayanam static const struct xiic_version_data xiic_2_00 = {
12082fd5cf35SRaviteja Narayanam .quirks = DYNAMIC_MODE_READ_BROKEN_BIT,
12092fd5cf35SRaviteja Narayanam };
12102fd5cf35SRaviteja Narayanam
12112fd5cf35SRaviteja Narayanam static const struct of_device_id xiic_of_match[] = {
12122fd5cf35SRaviteja Narayanam { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
12139b97cd61SRaviteja Narayanam { .compatible = "xlnx,axi-iic-2.1", },
12142fd5cf35SRaviteja Narayanam {},
12152fd5cf35SRaviteja Narayanam };
12162fd5cf35SRaviteja Narayanam MODULE_DEVICE_TABLE(of, xiic_of_match);
12172fd5cf35SRaviteja Narayanam #endif
12182fd5cf35SRaviteja Narayanam
xiic_i2c_probe(struct platform_device * pdev)12190b255e92SBill Pemberton static int xiic_i2c_probe(struct platform_device *pdev)
1220e1d5b659SRichard Röjfors {
1221e1d5b659SRichard Röjfors struct xiic_i2c *i2c;
1222e1d5b659SRichard Röjfors struct xiic_i2c_platform_data *pdata;
12232fd5cf35SRaviteja Narayanam const struct of_device_id *match;
1224e1d5b659SRichard Röjfors struct resource *res;
1225e1d5b659SRichard Röjfors int ret, irq;
1226e1d5b659SRichard Röjfors u8 i;
122748ef3ca9SThomas Gessler u32 sr;
1228e1d5b659SRichard Röjfors
1229168e722dSKedareswara rao Appana i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1230e1d5b659SRichard Röjfors if (!i2c)
1231e1d5b659SRichard Röjfors return -ENOMEM;
1232e1d5b659SRichard Röjfors
12332fd5cf35SRaviteja Narayanam match = of_match_node(xiic_of_match, pdev->dev.of_node);
12342fd5cf35SRaviteja Narayanam if (match && match->data) {
12352fd5cf35SRaviteja Narayanam const struct xiic_version_data *data = match->data;
12362fd5cf35SRaviteja Narayanam
12372fd5cf35SRaviteja Narayanam i2c->quirks = data->quirks;
12382fd5cf35SRaviteja Narayanam }
12392fd5cf35SRaviteja Narayanam
12400cc98416SYang Li i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1241168e722dSKedareswara rao Appana if (IS_ERR(i2c->base))
1242168e722dSKedareswara rao Appana return PTR_ERR(i2c->base);
1243e1d5b659SRichard Röjfors
1244168e722dSKedareswara rao Appana irq = platform_get_irq(pdev, 0);
1245168e722dSKedareswara rao Appana if (irq < 0)
1246168e722dSKedareswara rao Appana return irq;
1247168e722dSKedareswara rao Appana
1248168e722dSKedareswara rao Appana pdata = dev_get_platdata(&pdev->dev);
1249e1d5b659SRichard Röjfors
1250e1d5b659SRichard Röjfors /* hook up driver to tree */
1251e1d5b659SRichard Röjfors platform_set_drvdata(pdev, i2c);
1252e1d5b659SRichard Röjfors i2c->adap = xiic_adapter;
1253e1d5b659SRichard Röjfors i2c_set_adapdata(&i2c->adap, i2c);
1254e1d5b659SRichard Röjfors i2c->adap.dev.parent = &pdev->dev;
12553ac0b337SLars-Peter Clausen i2c->adap.dev.of_node = pdev->dev.of_node;
12561d366c2fSRobert Hancock snprintf(i2c->adap.name, sizeof(i2c->adap.name),
12571d366c2fSRobert Hancock DRIVER_NAME " %s", pdev->name);
1258e1d5b659SRichard Röjfors
125977c68019SLars-Peter Clausen mutex_init(&i2c->lock);
1260168e722dSKedareswara rao Appana
12618390dc74SAndi Shyti i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL);
12629dbba3f8SKrzysztof Kozlowski if (IS_ERR(i2c->clk))
12639dbba3f8SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
12648390dc74SAndi Shyti "failed to enable input clock.\n");
12659dbba3f8SKrzysztof Kozlowski
126636ecbcabSShubhrajyoti Datta i2c->dev = &pdev->dev;
126736ecbcabSShubhrajyoti Datta pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
126836ecbcabSShubhrajyoti Datta pm_runtime_use_autosuspend(i2c->dev);
126936ecbcabSShubhrajyoti Datta pm_runtime_set_active(i2c->dev);
127010b17004SShubhrajyoti Datta pm_runtime_enable(i2c->dev);
12716d8ffbe6SRaviteja Narayanam
12726d8ffbe6SRaviteja Narayanam /* SCL frequency configuration */
12736d8ffbe6SRaviteja Narayanam i2c->input_clk = clk_get_rate(i2c->clk);
12746d8ffbe6SRaviteja Narayanam ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
12756d8ffbe6SRaviteja Narayanam &i2c->i2c_clk);
12766d8ffbe6SRaviteja Narayanam /* If clock-frequency not specified in DT, do not configure in SW */
12776d8ffbe6SRaviteja Narayanam if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
12786d8ffbe6SRaviteja Narayanam i2c->i2c_clk = 0;
12796d8ffbe6SRaviteja Narayanam
1280861dcffeSMarek Vasut ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1281fcc2fac6SShubhrajyoti Datta xiic_process, IRQF_ONESHOT,
1282fcc2fac6SShubhrajyoti Datta pdev->name, i2c);
1283fcc2fac6SShubhrajyoti Datta
1284168e722dSKedareswara rao Appana if (ret < 0) {
1285e1d5b659SRichard Röjfors dev_err(&pdev->dev, "Cannot claim IRQ\n");
12868390dc74SAndi Shyti goto err_pm_disable;
1287e1d5b659SRichard Röjfors }
1288e1d5b659SRichard Röjfors
12899e3b184bSJaakko Laine i2c->singlemaster =
12909e3b184bSJaakko Laine of_property_read_bool(pdev->dev.of_node, "single-master");
12919e3b184bSJaakko Laine
129248ef3ca9SThomas Gessler /*
129348ef3ca9SThomas Gessler * Detect endianness
129448ef3ca9SThomas Gessler * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
129548ef3ca9SThomas Gessler * set, assume that the endianness was wrong and swap.
129648ef3ca9SThomas Gessler */
129748ef3ca9SThomas Gessler i2c->endianness = LITTLE;
129848ef3ca9SThomas Gessler xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
129948ef3ca9SThomas Gessler /* Reset is cleared in xiic_reinit */
130048ef3ca9SThomas Gessler sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
130148ef3ca9SThomas Gessler if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
130248ef3ca9SThomas Gessler i2c->endianness = BIG;
130348ef3ca9SThomas Gessler
1304b4c119dbSShubhrajyoti Datta ret = xiic_reinit(i2c);
1305b4c119dbSShubhrajyoti Datta if (ret < 0) {
1306b4c119dbSShubhrajyoti Datta dev_err(&pdev->dev, "Cannot xiic_reinit\n");
13078390dc74SAndi Shyti goto err_pm_disable;
1308b4c119dbSShubhrajyoti Datta }
1309617bdcbcSMichal Simek
1310e1d5b659SRichard Röjfors /* add i2c adapter to i2c tree */
1311e1d5b659SRichard Röjfors ret = i2c_add_adapter(&i2c->adap);
1312e1d5b659SRichard Röjfors if (ret) {
1313168e722dSKedareswara rao Appana xiic_deinit(i2c);
13148390dc74SAndi Shyti goto err_pm_disable;
1315e1d5b659SRichard Röjfors }
1316e1d5b659SRichard Röjfors
13173ac0b337SLars-Peter Clausen if (pdata) {
1318e1d5b659SRichard Röjfors /* add in known devices to the bus */
1319e1d5b659SRichard Röjfors for (i = 0; i < pdata->num_devices; i++)
1320bf255befSWolfram Sang i2c_new_client_device(&i2c->adap, pdata->devices + i);
13213ac0b337SLars-Peter Clausen }
13223ac0b337SLars-Peter Clausen
13236d8ffbe6SRaviteja Narayanam dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n",
13246d8ffbe6SRaviteja Narayanam (unsigned long)res->start, irq, i2c->i2c_clk);
13256d8ffbe6SRaviteja Narayanam
1326e1d5b659SRichard Röjfors return 0;
132736ecbcabSShubhrajyoti Datta
13288390dc74SAndi Shyti err_pm_disable:
132936ecbcabSShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev);
133036ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev);
13318390dc74SAndi Shyti
133236ecbcabSShubhrajyoti Datta return ret;
1333e1d5b659SRichard Röjfors }
1334e1d5b659SRichard Röjfors
xiic_i2c_remove(struct platform_device * pdev)1335e190a0c3SUwe Kleine-König static void xiic_i2c_remove(struct platform_device *pdev)
1336e1d5b659SRichard Röjfors {
1337e1d5b659SRichard Röjfors struct xiic_i2c *i2c = platform_get_drvdata(pdev);
133836ecbcabSShubhrajyoti Datta int ret;
1339e1d5b659SRichard Röjfors
1340e1d5b659SRichard Röjfors /* remove adapter & data */
1341e1d5b659SRichard Röjfors i2c_del_adapter(&i2c->adap);
1342e1d5b659SRichard Röjfors
1343810199f7SUwe Kleine-König ret = pm_runtime_get_sync(i2c->dev);
134410b17004SShubhrajyoti Datta
1345810199f7SUwe Kleine-König if (ret < 0)
1346810199f7SUwe Kleine-König dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n",
1347810199f7SUwe Kleine-König ERR_PTR(ret));
1348810199f7SUwe Kleine-König else
1349e1d5b659SRichard Röjfors xiic_deinit(i2c);
1350810199f7SUwe Kleine-König
135110b17004SShubhrajyoti Datta pm_runtime_put_sync(i2c->dev);
135236ecbcabSShubhrajyoti Datta pm_runtime_disable(&pdev->dev);
135310b17004SShubhrajyoti Datta pm_runtime_set_suspended(&pdev->dev);
135410b17004SShubhrajyoti Datta pm_runtime_dont_use_autosuspend(&pdev->dev);
1355e1d5b659SRichard Röjfors }
1356e1d5b659SRichard Röjfors
xiic_i2c_runtime_suspend(struct device * dev)135774d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
135836ecbcabSShubhrajyoti Datta {
13599242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev);
136036ecbcabSShubhrajyoti Datta
136136ecbcabSShubhrajyoti Datta clk_disable(i2c->clk);
136236ecbcabSShubhrajyoti Datta
136336ecbcabSShubhrajyoti Datta return 0;
136436ecbcabSShubhrajyoti Datta }
136536ecbcabSShubhrajyoti Datta
xiic_i2c_runtime_resume(struct device * dev)136674d23319SMoritz Fischer static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
136736ecbcabSShubhrajyoti Datta {
13689242e72aSMasahiro Yamada struct xiic_i2c *i2c = dev_get_drvdata(dev);
136936ecbcabSShubhrajyoti Datta int ret;
137036ecbcabSShubhrajyoti Datta
137136ecbcabSShubhrajyoti Datta ret = clk_enable(i2c->clk);
137236ecbcabSShubhrajyoti Datta if (ret) {
137336ecbcabSShubhrajyoti Datta dev_err(dev, "Cannot enable clock.\n");
137436ecbcabSShubhrajyoti Datta return ret;
137536ecbcabSShubhrajyoti Datta }
137636ecbcabSShubhrajyoti Datta
137736ecbcabSShubhrajyoti Datta return 0;
137836ecbcabSShubhrajyoti Datta }
137936ecbcabSShubhrajyoti Datta
138036ecbcabSShubhrajyoti Datta static const struct dev_pm_ops xiic_dev_pm_ops = {
138174d23319SMoritz Fischer SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
138274d23319SMoritz Fischer xiic_i2c_runtime_resume, NULL)
138336ecbcabSShubhrajyoti Datta };
1384b822039bSMichal Simek
1385e1d5b659SRichard Röjfors static struct platform_driver xiic_i2c_driver = {
1386e1d5b659SRichard Röjfors .probe = xiic_i2c_probe,
1387e190a0c3SUwe Kleine-König .remove_new = xiic_i2c_remove,
1388e1d5b659SRichard Röjfors .driver = {
1389e1d5b659SRichard Röjfors .name = DRIVER_NAME,
13903ac0b337SLars-Peter Clausen .of_match_table = of_match_ptr(xiic_of_match),
139136ecbcabSShubhrajyoti Datta .pm = &xiic_dev_pm_ops,
1392e1d5b659SRichard Röjfors },
1393e1d5b659SRichard Röjfors };
1394e1d5b659SRichard Röjfors
1395a3664b51SAxel Lin module_platform_driver(xiic_i2c_driver);
1396e1d5b659SRichard Röjfors
1397b8caf0a0SMartin Tůma MODULE_ALIAS("platform:" DRIVER_NAME);
1398e1d5b659SRichard Röjfors MODULE_AUTHOR("info@mocean-labs.com");
1399e1d5b659SRichard Röjfors MODULE_DESCRIPTION("Xilinx I2C bus driver");
1400e1d5b659SRichard Röjfors MODULE_LICENSE("GPL v2");
1401