2  * (C) Copyright 2009-2010
5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7  * This file contains the shared part of the driver for the i2c adapter in
16 #include <linux/i2c.h>
21 #include "i2c-octeon-core.h"
26 	struct octeon_i2c *i2c = dev_id;  in octeon_i2c_isr()  local
28 	i2c->int_disable(i2c);  in octeon_i2c_isr()
29 	wake_up(&i2c->queue);  in octeon_i2c_isr()
34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)  in octeon_i2c_test_iflg()  argument
36 	return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);  in octeon_i2c_test_iflg()
40  * octeon_i2c_wait - wait for the IFLG to be set
41  * @i2c: The struct octeon_i2c
43  * Returns 0 on success, otherwise a negative errno.
45 static int octeon_i2c_wait(struct octeon_i2c *i2c)  in octeon_i2c_wait()  argument
53 	if (i2c->broken_irq_mode) {  in octeon_i2c_wait()
54 		u64 end = get_jiffies_64() + i2c->adap.timeout;  in octeon_i2c_wait()
56 		while (!octeon_i2c_test_iflg(i2c) &&  in octeon_i2c_wait()
60 		return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;  in octeon_i2c_wait()
63 	i2c->int_enable(i2c);  in octeon_i2c_wait()
64 	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),  in octeon_i2c_wait()
65 				       i2c->adap.timeout);  in octeon_i2c_wait()
66 	i2c->int_disable(i2c);  in octeon_i2c_wait()
68 	if (i2c->broken_irq_check && !time_left &&  in octeon_i2c_wait()
69 	    octeon_i2c_test_iflg(i2c)) {  in octeon_i2c_wait()
70 		dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");  in octeon_i2c_wait()
71 		i2c->broken_irq_mode = true;  in octeon_i2c_wait()
72 		return 0;  in octeon_i2c_wait()
76 		return -ETIMEDOUT;  in octeon_i2c_wait()
78 	return 0;  in octeon_i2c_wait()
81 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)  in octeon_i2c_hlc_test_valid()  argument
83 	return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;  in octeon_i2c_hlc_test_valid()
86 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)  in octeon_i2c_hlc_int_clear()  argument
89 	octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);  in octeon_i2c_hlc_int_clear()
93  * Cleanup low-level state & enable high-level controller.
95 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)  in octeon_i2c_hlc_enable()  argument
97 	int try = 0;  in octeon_i2c_hlc_enable()
100 	if (i2c->hlc_enabled)  in octeon_i2c_hlc_enable()
102 	i2c->hlc_enabled = true;  in octeon_i2c_hlc_enable()
105 		val = octeon_i2c_ctl_read(i2c);  in octeon_i2c_hlc_enable()
111 			octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_hlc_enable()
121 	octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);  in octeon_i2c_hlc_enable()
124 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)  in octeon_i2c_hlc_disable()  argument
126 	if (!i2c->hlc_enabled)  in octeon_i2c_hlc_disable()
129 	i2c->hlc_enabled = false;  in octeon_i2c_hlc_disable()
130 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_hlc_disable()
134  * octeon_i2c_hlc_wait - wait for an HLC operation to complete
135  * @i2c: The struct octeon_i2c
137  * Returns 0 on success, otherwise -ETIMEDOUT.
139 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)  in octeon_i2c_hlc_wait()  argument
147 	if (i2c->broken_irq_mode) {  in octeon_i2c_hlc_wait()
148 		u64 end = get_jiffies_64() + i2c->adap.timeout;  in octeon_i2c_hlc_wait()
150 		while (!octeon_i2c_hlc_test_valid(i2c) &&  in octeon_i2c_hlc_wait()
154 		return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;  in octeon_i2c_hlc_wait()
157 	i2c->hlc_int_enable(i2c);  in octeon_i2c_hlc_wait()
158 	time_left = wait_event_timeout(i2c->queue,  in octeon_i2c_hlc_wait()
159 				       octeon_i2c_hlc_test_valid(i2c),  in octeon_i2c_hlc_wait()
160 				       i2c->adap.timeout);  in octeon_i2c_hlc_wait()
161 	i2c->hlc_int_disable(i2c);  in octeon_i2c_hlc_wait()
163 		octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_wait()
165 	if (i2c->broken_irq_check && !time_left &&  in octeon_i2c_hlc_wait()
166 	    octeon_i2c_hlc_test_valid(i2c)) {  in octeon_i2c_hlc_wait()
167 		dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");  in octeon_i2c_hlc_wait()
168 		i2c->broken_irq_mode = true;  in octeon_i2c_hlc_wait()
169 		return 0;  in octeon_i2c_hlc_wait()
173 		return -ETIMEDOUT;  in octeon_i2c_hlc_wait()
174 	return 0;  in octeon_i2c_hlc_wait()
177 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)  in octeon_i2c_check_status()  argument
185 	if (i2c->hlc_enabled)  in octeon_i2c_check_status()
186 		stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_check_status()
188 		stat = octeon_i2c_stat_read(i2c);  in octeon_i2c_check_status()
197 		return 0;  in octeon_i2c_check_status()
199 	/* ACK allowed on pre-terminal bytes only */  in octeon_i2c_check_status()
202 			return 0;  in octeon_i2c_check_status()
203 		return -EIO;  in octeon_i2c_check_status()
208 			return 0;  in octeon_i2c_check_status()
209 		return -EIO;  in octeon_i2c_check_status()
216 		return -EAGAIN;  in octeon_i2c_check_status()
223 		return -EOPNOTSUPP;  in octeon_i2c_check_status()
233 		return -EOPNOTSUPP;  in octeon_i2c_check_status()
237 		return -EIO;  in octeon_i2c_check_status()
241 		return -ENXIO;  in octeon_i2c_check_status()
243 		dev_err(i2c->dev, "unhandled state: %d\n", stat);  in octeon_i2c_check_status()
244 		return -EIO;  in octeon_i2c_check_status()
248 static int octeon_i2c_recovery(struct octeon_i2c *i2c)  in octeon_i2c_recovery()  argument
252 	ret = i2c_recover_bus(&i2c->adap);  in octeon_i2c_recovery()
254 		/* recover failed, try hardware re-init */  in octeon_i2c_recovery()
255 		ret = octeon_i2c_init_lowlevel(i2c);  in octeon_i2c_recovery()
260  * octeon_i2c_start - send START to the bus
261  * @i2c: The struct octeon_i2c
263  * Returns 0 on success, otherwise a negative errno.
265 static int octeon_i2c_start(struct octeon_i2c *i2c)  in octeon_i2c_start()  argument
270 	octeon_i2c_hlc_disable(i2c);  in octeon_i2c_start()
272 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);  in octeon_i2c_start()
273 	ret = octeon_i2c_wait(i2c);  in octeon_i2c_start()
277 	stat = octeon_i2c_stat_read(i2c);  in octeon_i2c_start()
280 		return 0;  in octeon_i2c_start()
284 	ret = octeon_i2c_recovery(i2c);  in octeon_i2c_start()
285 	return (ret) ? ret : -EAGAIN;  in octeon_i2c_start()
289 static void octeon_i2c_stop(struct octeon_i2c *i2c)  in octeon_i2c_stop()  argument
291 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);  in octeon_i2c_stop()
295  * octeon_i2c_read - receive data from the bus via low-level controller
296  * @i2c: The struct octeon_i2c
304  * Returns 0 on success, otherwise a negative errno.
306 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,  in octeon_i2c_read()  argument
312 	octeon_i2c_data_write(i2c, (target << 1) | 1);  in octeon_i2c_read()
313 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_read()
315 	result = octeon_i2c_wait(i2c);  in octeon_i2c_read()
320 	result = octeon_i2c_check_status(i2c, false);  in octeon_i2c_read()
324 	for (i = 0; i < length; i++) {  in octeon_i2c_read()
333 		if ((i + 1 == length) && !(recv_len && i == 0))  in octeon_i2c_read()
338 			octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_read()
340 			octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);  in octeon_i2c_read()
342 		result = octeon_i2c_wait(i2c);  in octeon_i2c_read()
346 		data[i] = octeon_i2c_data_read(i2c, &result);  in octeon_i2c_read()
349 		if (recv_len && i == 0) {  in octeon_i2c_read()
351 				return -EPROTO;  in octeon_i2c_read()
355 		result = octeon_i2c_check_status(i2c, final_read);  in octeon_i2c_read()
360 	return 0;  in octeon_i2c_read()
364  * octeon_i2c_write - send data to the bus via low-level controller
365  * @i2c: The struct octeon_i2c
372  * Returns 0 on success, otherwise a negative errno.
374 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,  in octeon_i2c_write()  argument
379 	octeon_i2c_data_write(i2c, target << 1);  in octeon_i2c_write()
380 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_write()
382 	result = octeon_i2c_wait(i2c);  in octeon_i2c_write()
386 	for (i = 0; i < length; i++) {  in octeon_i2c_write()
387 		result = octeon_i2c_check_status(i2c, false);  in octeon_i2c_write()
391 		octeon_i2c_data_write(i2c, data[i]);  in octeon_i2c_write()
392 		octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_write()
394 		result = octeon_i2c_wait(i2c);  in octeon_i2c_write()
399 	return 0;  in octeon_i2c_write()
402 /* high-level-controller pure read of up to 8 bytes */
403 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_read()  argument
405 	int i, j, ret = 0;  in octeon_i2c_hlc_read()
408 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_read()
409 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_read()
413 	cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_read()
415 	cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;  in octeon_i2c_hlc_read()
417 	if (msgs[0].flags & I2C_M_TEN)  in octeon_i2c_hlc_read()
422 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_read()
423 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_read()
427 	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_read()
428 	if ((cmd & SW_TWSI_R) == 0)  in octeon_i2c_hlc_read()
429 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_read()
431 	for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)  in octeon_i2c_hlc_read()
432 		msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;  in octeon_i2c_hlc_read()
434 	if (msgs[0].len > 4) {  in octeon_i2c_hlc_read()
435 		cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_read()
436 		for (i = 0; i  < msgs[0].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_read()
437 			msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;  in octeon_i2c_hlc_read()
444 /* high-level-controller pure write of up to 8 bytes */
445 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_write()  argument
447 	int i, j, ret = 0;  in octeon_i2c_hlc_write()
450 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_write()
451 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_write()
455 	cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_write()
457 	cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;  in octeon_i2c_hlc_write()
459 	if (msgs[0].flags & I2C_M_TEN)  in octeon_i2c_hlc_write()
464 	for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)  in octeon_i2c_hlc_write()
465 		cmd |= (u64)msgs[0].buf[j] << (8 * i);  in octeon_i2c_hlc_write()
467 	if (msgs[0].len > 4) {  in octeon_i2c_hlc_write()
468 		u64 ext = 0;  in octeon_i2c_hlc_write()
470 		for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_write()
471 			ext |= (u64)msgs[0].buf[j] << (8 * i);  in octeon_i2c_hlc_write()
472 		octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_write()
475 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_write()
476 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_write()
480 	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_write()
481 	if ((cmd & SW_TWSI_R) == 0)  in octeon_i2c_hlc_write()
482 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_write()
488 /* high-level-controller composite write+read, msg0=addr, msg1=data */
489 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_comp_read()  argument
491 	int i, j, ret = 0;  in octeon_i2c_hlc_comp_read()
494 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_comp_read()
498 	cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_comp_read()
500 	cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;  in octeon_i2c_hlc_comp_read()
502 	if (msgs[0].flags & I2C_M_TEN)  in octeon_i2c_hlc_comp_read()
507 	if (msgs[0].len == 2) {  in octeon_i2c_hlc_comp_read()
508 		u64 ext = 0;  in octeon_i2c_hlc_comp_read()
511 		ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_read()
512 		cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_read()
513 		octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_comp_read()
515 		cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_read()
518 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_comp_read()
519 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_comp_read()
521 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_comp_read()
525 	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_comp_read()
526 	if ((cmd & SW_TWSI_R) == 0)  in octeon_i2c_hlc_comp_read()
527 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_comp_read()
529 	for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)  in octeon_i2c_hlc_comp_read()
530 		msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;  in octeon_i2c_hlc_comp_read()
533 		cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_comp_read()
534 		for (i = 0; i  < msgs[1].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_comp_read()
535 			msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;  in octeon_i2c_hlc_comp_read()
542 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
543 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_comp_write()  argument
546 	int i, j, ret = 0;  in octeon_i2c_hlc_comp_write()
547 	u64 cmd, ext = 0;  in octeon_i2c_hlc_comp_write()
549 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_comp_write()
553 	cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_comp_write()
555 	cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;  in octeon_i2c_hlc_comp_write()
557 	if (msgs[0].flags & I2C_M_TEN)  in octeon_i2c_hlc_comp_write()
562 	if (msgs[0].len == 2) {  in octeon_i2c_hlc_comp_write()
564 		ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_write()
566 		cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_write()
568 		cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_write()
571 	for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)  in octeon_i2c_hlc_comp_write()
575 		for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_comp_write()
580 		octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_comp_write()
582 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_comp_write()
583 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_comp_write()
585 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_comp_write()
589 	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));  in octeon_i2c_hlc_comp_write()
590 	if ((cmd & SW_TWSI_R) == 0)  in octeon_i2c_hlc_comp_write()
591 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_comp_write()
598  * octeon_i2c_xfer - The driver's master_xfer function
607 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_xfer()  local
608 	int i, ret = 0;  in octeon_i2c_xfer()
611 		if (msgs[0].len > 0 && msgs[0].len <= 8) {  in octeon_i2c_xfer()
612 			if (msgs[0].flags & I2C_M_RD)  in octeon_i2c_xfer()
613 				ret = octeon_i2c_hlc_read(i2c, msgs);  in octeon_i2c_xfer()
615 				ret = octeon_i2c_hlc_write(i2c, msgs);  in octeon_i2c_xfer()
619 		if ((msgs[0].flags & I2C_M_RD) == 0 &&  in octeon_i2c_xfer()
620 		    (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&  in octeon_i2c_xfer()
621 		    msgs[0].len > 0 && msgs[0].len <= 2 &&  in octeon_i2c_xfer()
622 		    msgs[1].len > 0 && msgs[1].len <= 8 &&  in octeon_i2c_xfer()
623 		    msgs[0].addr == msgs[1].addr) {  in octeon_i2c_xfer()
625 				ret = octeon_i2c_hlc_comp_read(i2c, msgs);  in octeon_i2c_xfer()
627 				ret = octeon_i2c_hlc_comp_write(i2c, msgs);  in octeon_i2c_xfer()
632 	for (i = 0; ret == 0 && i < num; i++) {  in octeon_i2c_xfer()
635 		/* zero-length messages are not supported */  in octeon_i2c_xfer()
636 		if (!pmsg->len) {  in octeon_i2c_xfer()
637 			ret = -EOPNOTSUPP;  in octeon_i2c_xfer()
641 		ret = octeon_i2c_start(i2c);  in octeon_i2c_xfer()
645 		if (pmsg->flags & I2C_M_RD)  in octeon_i2c_xfer()
646 			ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,  in octeon_i2c_xfer()
647 					      &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);  in octeon_i2c_xfer()
649 			ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,  in octeon_i2c_xfer()
650 					       pmsg->len);  in octeon_i2c_xfer()
652 	octeon_i2c_stop(i2c);  in octeon_i2c_xfer()
654 	return (ret != 0) ? ret : num;  in octeon_i2c_xfer()
658 void octeon_i2c_set_clock(struct octeon_i2c *i2c)  in octeon_i2c_set_clock()  argument
661 	int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;  in octeon_i2c_set_clock()
663 	for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {  in octeon_i2c_set_clock()
668 		for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {  in octeon_i2c_set_clock()
673 			tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;  in octeon_i2c_set_clock()
675 			thp_base = (i2c->sys_freq / (tclk * 2)) - 1;  in octeon_i2c_set_clock()
677 			for (inc = 0; inc <= 1; inc++) {  in octeon_i2c_set_clock()
679 				if (thp_idx < 5 || thp_idx > 0xff)  in octeon_i2c_set_clock()
682 				foscl = i2c->sys_freq / (2 * (thp_idx + 1));  in octeon_i2c_set_clock()
685 				diff = abs(foscl - i2c->twsi_freq);  in octeon_i2c_set_clock()
695 	octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);  in octeon_i2c_set_clock()
696 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);  in octeon_i2c_set_clock()
699 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)  in octeon_i2c_init_lowlevel()  argument
701 	u8 status = 0;  in octeon_i2c_init_lowlevel()
705 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);  in octeon_i2c_init_lowlevel()
707 	for (tries = 10; tries && status != STAT_IDLE; tries--) {  in octeon_i2c_init_lowlevel()
709 		status = octeon_i2c_stat_read(i2c);  in octeon_i2c_init_lowlevel()
715 		dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",  in octeon_i2c_init_lowlevel()
717 		return -EIO;  in octeon_i2c_init_lowlevel()
721 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_init_lowlevel()
722 	octeon_i2c_hlc_disable(i2c);  in octeon_i2c_init_lowlevel()
723 	return 0;  in octeon_i2c_init_lowlevel()
728 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_get_scl()  local
731 	state = octeon_i2c_read_int(i2c);  in octeon_i2c_get_scl()
737 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_set_scl()  local
739 	octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);  in octeon_i2c_set_scl()
744 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_get_sda()  local
747 	state = octeon_i2c_read_int(i2c);  in octeon_i2c_get_sda()
753 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_prepare_recovery()  local
755 	octeon_i2c_hlc_disable(i2c);  in octeon_i2c_prepare_recovery()
756 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);  in octeon_i2c_prepare_recovery()
764 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_prepare_recovery()
766 	octeon_i2c_write_int(i2c, 0);  in octeon_i2c_prepare_recovery()
771 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_unprepare_recovery()  local
778 	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);  in octeon_i2c_unprepare_recovery()
780 	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);  in octeon_i2c_unprepare_recovery()
782 	octeon_i2c_write_int(i2c, 0);  in octeon_i2c_unprepare_recovery()