Searched +full:fpga +full:- +full:mgr (Results 1 – 11 of 11) sorted by relevance
1 Altera SOCFPGA Arria10 FPGA Manager4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"5 - reg : base address and size for memory mapped io.6 - The first index is for FPGA manager register access.7 - The second index is for writing FPGA configuration data.8 - resets : Phandle and reset specifier for the device's reset.9 - clocks : Clocks used by the device.13 fpga_mgr: fpga-mgr@ffd03000 {14 compatible = "altr,socfpga-a10-fpga-mgr";
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>20 #include <dt-bindings/reset/altr,rst-mgr-s10.h>28 * FPGA programming support for SoC FPGA Stratix 1037 -1,57 return -EINVAL; in socfpga_phymode_setup()67 return -EINVAL; in socfpga_phymode_setup()69 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, in socfpga_phymode_setup()78 const void *fdt = gd->fdt_blob; in socfpga_set_phymode()95 "#reset-cells", 1, 0, in socfpga_set_phymode()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>24 #include <dt-bindings/reset/altr,rst-mgr.h>38 * FPGA programming support for SoC FPGA Cyclone V47 -1,95 printf("FPGA: Not Altera chip ID\n"); in socfpga_fpga_id()96 return -EINVAL; in socfpga_fpga_id()104 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); in socfpga_fpga_id()105 return -EINVAL; in socfpga_fpga_id()109 printf("FPGA: Altera %s, version 0x%01x\n", in socfpga_fpga_id()[all …]
17 #include <dt-bindings/interrupt-controller/arm-gic.h>18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>21 #address-cells = <1>;22 #size-cells = <1>;25 tick-timer = &timer2;26 u-boot,dm-pre-reloc;30 #address-cells = <1>;31 #size-cells = <0>;32 enable-method = "altr,socfpga-a10-smp";35 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0+6 #include <dt-bindings/reset/altr,rst-mgr.h>9 #address-cells = <1>;10 #size-cells = <1>;22 #address-cells = <1>;23 #size-cells = <0>;24 enable-method = "altr,socfpga-smp";27 compatible = "arm,cortex-a9";30 next-level-cache = <&L2>;33 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * Describes the hardware common to all Zynq 7000-based boards.6 * Copyright (C) 2011 - 2015 Xilinx10 #address-cells = <1>;11 #size-cells = <1>;12 compatible = "xlnx,zynq-7000";15 #address-cells = <1>;16 #size-cells = <0>;19 compatible = "arm,cortex-a9";23 clock-latency = <1000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2014 - 2015, Xilinx, Inc.17 #address-cells = <2>;18 #size-cells = <2>;21 #address-cells = <1>;22 #size-cells = <0>;25 compatible = "arm,cortex-a53", "arm,armv8";27 enable-method = "psci";28 operating-points-v2 = <&cpu_opp_table>;30 cpu-idle-states = <&CPU_SLEEP_0>;[all …]
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1 // SPDX-License-Identifier: GPL-2.0+30 * good reason why driver-model conversion is infeasible. Examples include36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),[all …]
1 2025-12-15 03:01:05.452-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-15 03:01:05.518-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]
1 2025-12-14 03:01:07.427-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-14 03:01:07.482-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]