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/openbmc/linux/drivers/fpga/
H A Dfpga-mgr.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Core
5 * Copyright (C) 2013-2015 Altera Corporation
12 #include <linux/fpga/fpga-mgr.h>
25 struct fpga_manager *mgr; member
28 static inline void fpga_mgr_fpga_remove(struct fpga_manager *mgr) in fpga_mgr_fpga_remove() argument
30 if (mgr->mops->fpga_remove) in fpga_mgr_fpga_remove()
31 mgr->mops->fpga_remove(mgr); in fpga_mgr_fpga_remove()
34 static inline enum fpga_mgr_states fpga_mgr_state(struct fpga_manager *mgr) in fpga_mgr_state() argument
36 if (mgr->mops->state) in fpga_mgr_state()
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H A Ddfl-fme-region.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-mgr.h>
18 #include <linux/fpga/fpga-region.h>
20 #include "dfl-fme-pr.h"
24 struct dfl_fme_region_pdata *pdata = region->priv; in fme_region_get_bridges()
25 struct device *dev = &pdata->br->dev; in fme_region_get_bridges()
27 return fpga_bridge_get_to_list(dev, region->info, &region->bridge_list); in fme_region_get_bridges()
32 struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev); in fme_region_probe()
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H A Ddfl-fme-pr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 #include <linux/fpga/fpga-mgr.h>
24 #include <linux/fpga/fpga-bridge.h>
25 #include <linux/fpga/fpga-region.h>
26 #include <linux/fpga-dfl.h>
29 #include "dfl-fme.h"
30 #include "dfl-fme-pr.h"
37 list_for_each_entry(fme_region, &fme->region_list, node) in dfl_fme_region_find_by_port_id()
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H A Dof-fpga-region.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
31 * Caller will need to put_device(&region->dev) when done.
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H A Dts73xx-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
35 static int ts73xx_fpga_write_init(struct fpga_manager *mgr, in ts73xx_fpga_write_init() argument
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
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H A Dfpga-region.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to an fpga region
37 * @region: FPGA Region struct
43 * * -EBUSY if someone already has a reference to the region.
44 * * -ENODEV if can't take parent driver module refcount.
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H A Dstratix10-soc.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Intel Stratix10 SoC
8 #include <linux/fpga/fpga-mgr.h>
9 #include <linux/firmware/intel/stratix10-svc-client.h>
16 * FPGA programming requires a higher level of privilege (EL3), per the SoC
50 struct stratix10_svc_chan *chan = priv->chan; in s10_svc_send_msg()
51 struct device *dev = priv->client.dev; in s10_svc_send_msg()
72 static bool s10_free_buffers(struct fpga_manager *mgr) in s10_free_buffers() argument
74 struct s10_priv *priv = mgr->priv; in s10_free_buffers()
79 if (!priv->svc_bufs[i].buf) { in s10_free_buffers()
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H A Dice40-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * FPGA Manager Driver for Lattice iCE40.
7 * This driver adds support to the FPGA manager for configuring the SRAM of
11 #include <linux/fpga/fpga-mgr.h>
32 static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr) in ice40_fpga_ops_state() argument
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
40 static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, in ice40_fpga_ops_write_init() argument
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
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H A Dxilinx-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Manage Xilinx FPGA firmware that is loaded over SPI using
15 #include <linux/fpga/fpga-mgr.h>
30 static int get_done_gpio(struct fpga_manager *mgr) in get_done_gpio() argument
32 struct xilinx_spi_conf *conf = mgr->priv; in get_done_gpio()
35 ret = gpiod_get_value(conf->done); in get_done_gpio()
38 dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); in get_done_gpio()
43 static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) in xilinx_spi_state() argument
45 if (!get_done_gpio(mgr)) in xilinx_spi_state()
52 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
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H A Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera Arria10 SoCFPGA
5 * Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/fpga-mgr.h>
54 /* FPGA CD Ratio Value */
65 * struct a10_fpga_priv - private data for fpga manager
67 * @fpga_data_addr: iomap for single address data register to FPGA
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
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H A Dversal-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
15 static int versal_fpga_ops_write_init(struct fpga_manager *mgr, in versal_fpga_ops_write_init() argument
22 static int versal_fpga_ops_write(struct fpga_manager *mgr, in versal_fpga_ops_write() argument
29 kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL); in versal_fpga_ops_write()
31 return -ENOMEM; in versal_fpga_ops_write()
35 dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr); in versal_fpga_ops_write()
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H A Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera SOCFPGA
5 * Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 "FPGA-1.5V",
99 "FPGA-1.1V",
100 "FPGA-2.5V",
136 return readl(priv->fpga_base_addr + reg_offset); in socfpga_fpga_readl()
142 writel(value, priv->fpga_base_addr + reg_offset); in socfpga_fpga_writel()
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H A Dzynqmp-fpga.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
28 static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, in zynqmp_fpga_ops_write_init() argument
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
40 static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, in zynqmp_fpga_ops_write() argument
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
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H A Daltera-ps-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Manage Altera FPGA firmware that is loaded over SPI using the passive
18 #include <linux/fpga/fpga-mgr.h>
82 { .compatible = "altr,fpga-passive-serial", .data = &c5_data },
83 { .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
88 static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr) in altera_ps_state() argument
90 struct altera_ps_conf *conf = mgr->priv; in altera_ps_state()
92 if (gpiod_get_value_cansleep(conf->status)) in altera_ps_state()
106 static int altera_ps_write_init(struct fpga_manager *mgr, in altera_ps_write_init() argument
110 struct altera_ps_conf *conf = mgr->priv; in altera_ps_write_init()
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H A Dmicrochip-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip Polarfire FPGA programming over slave SPI interface.
8 #include <linux/fpga/fpga-mgr.h>
59 .tx_buf = &priv->tx, in mpf_read_status()
60 .rx_buf = &priv->rx, in mpf_read_status()
64 .tx_buf = &priv->tx, in mpf_read_status()
65 .rx_buf = &priv->rx, in mpf_read_status()
72 priv->tx = MPF_SPI_READ_STATUS; in mpf_read_status()
74 ret = spi_sync_transfer(priv->spi, xfers, 2); in mpf_read_status()
78 status = priv->rx; in mpf_read_status()
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H A Ddfl-fme-mgr.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
22 #include <linux/io-64-nonatomic-lo-hi.h>
23 #include <linux/fpga/fpga-mgr.h>
25 #include "dfl-fme-pr.h"
52 /* PR data from the raw-binary file. */
107 static int fme_mgr_write_init(struct fpga_manager *mgr, in fme_mgr_write_init() argument
111 struct device *dev = &mgr->dev; in fme_mgr_write_init()
112 struct fme_mgr_priv *priv = mgr->priv; in fme_mgr_write_init()
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/openbmc/linux/Documentation/driver-api/fpga/
H A Dfpga-mgr.rst1 FPGA Manager
5 --------
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
24 --------------------------------
26 To add another FPGA manager, write a driver that implements a set of ops. The
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H A Dfpga-programming.rst1 In-kernel API for FPGA Programming
5 --------
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
19 * re-enable the bridges
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/openbmc/linux/include/linux/fpga/
H A Dfpga-mgr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FPGA Framework
5 * Copyright (C) 2013-2016 Altera Corporation
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
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H A Dfpga-region.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
13 * struct fpga_region_info - collection of parameters an FPGA Region
14 * @mgr: fpga region manager
15 * @compat_id: FPGA region id for compatibility check.
16 * @priv: fpga region private data
25 struct fpga_manager *mgr; member
32 * struct fpga_region - FPGA Region structure
33 * @dev: FPGA Region device
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/openbmc/linux/drivers/fpga/tests/
H A Dfpga-region-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
11 #include <linux/fpga/fpga-bridge.h>
12 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/fpga/fpga-region.h>
28 struct fpga_manager *mgr; member
38 static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) in op_write() argument
40 struct mgr_stats *stats = mgr->priv; in op_write()
42 stats->write_count++; in op_write()
48 * Fake FPGA manager that implements only the write op to count the number
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H A Dfpga-mgr-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Manager
12 #include <linux/fpga/fpga-mgr.h>
42 struct fpga_manager *mgr; member
48 * init_test_buffer() - Allocate and initialize a test image in a buffer.
64 memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE); in init_test_buffer()
71 * since, in this case, it is a failure of the FPGA manager itself, not this
74 static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info, in op_parse_header() argument
77 struct mgr_stats *stats = mgr->priv; in op_parse_header()
80 stats->op_parse_header_state = mgr->state; in op_parse_header()
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/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dintel-stratix10-soc-fpga-mgr.txt1 Intel Stratix10 SoC FPGA Manager
7 - compatible : should contain "intel,stratix10-soc-fpga-mgr" or
8 "intel,agilex-soc-fpga-mgr"
14 fpga_mgr: fpga-mgr {
15 compatible = "intel,stratix10-soc-fpga-mgr";
H A Daltera-socfpga-a10-fpga-mgr.txt1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
/openbmc/u-boot/doc/device-tree-bindings/fpga/
H A Daltera-socfpga-a10-fpga-mgr.txt1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";

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