1bb61b9beSWu Hao // SPDX-License-Identifier: GPL-2.0
2bb61b9beSWu Hao /*
3bb61b9beSWu Hao * FPGA Region Driver for FPGA Management Engine (FME)
4bb61b9beSWu Hao *
5bb61b9beSWu Hao * Copyright (C) 2017-2018 Intel Corporation, Inc.
6bb61b9beSWu Hao *
7bb61b9beSWu Hao * Authors:
8bb61b9beSWu Hao * Wu Hao <hao.wu@intel.com>
9bb61b9beSWu Hao * Joseph Grecco <joe.grecco@intel.com>
10bb61b9beSWu Hao * Enno Luebbers <enno.luebbers@intel.com>
11bb61b9beSWu Hao * Tim Whisonant <tim.whisonant@intel.com>
12bb61b9beSWu Hao * Ananda Ravuri <ananda.ravuri@intel.com>
13bb61b9beSWu Hao * Henry Mitchel <henry.mitchel@intel.com>
14bb61b9beSWu Hao */
15bb61b9beSWu Hao
16bb61b9beSWu Hao #include <linux/module.h>
1734bd2833SAlan Tull #include <linux/fpga/fpga-mgr.h>
18bb61b9beSWu Hao #include <linux/fpga/fpga-region.h>
19bb61b9beSWu Hao
20bb61b9beSWu Hao #include "dfl-fme-pr.h"
21bb61b9beSWu Hao
fme_region_get_bridges(struct fpga_region * region)22bb61b9beSWu Hao static int fme_region_get_bridges(struct fpga_region *region)
23bb61b9beSWu Hao {
24bb61b9beSWu Hao struct dfl_fme_region_pdata *pdata = region->priv;
25bb61b9beSWu Hao struct device *dev = &pdata->br->dev;
26bb61b9beSWu Hao
27bb61b9beSWu Hao return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list);
28bb61b9beSWu Hao }
29bb61b9beSWu Hao
fme_region_probe(struct platform_device * pdev)30bb61b9beSWu Hao static int fme_region_probe(struct platform_device *pdev)
31bb61b9beSWu Hao {
32bb61b9beSWu Hao struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev);
33*8886a579SRuss Weight struct fpga_region_info info = { 0 };
34bb61b9beSWu Hao struct device *dev = &pdev->dev;
35bb61b9beSWu Hao struct fpga_region *region;
36bb61b9beSWu Hao struct fpga_manager *mgr;
37bb61b9beSWu Hao int ret;
38bb61b9beSWu Hao
39bb61b9beSWu Hao mgr = fpga_mgr_get(&pdata->mgr->dev);
40bb61b9beSWu Hao if (IS_ERR(mgr))
41bb61b9beSWu Hao return -EPROBE_DEFER;
42bb61b9beSWu Hao
43*8886a579SRuss Weight info.mgr = mgr;
44*8886a579SRuss Weight info.compat_id = mgr->compat_id;
45*8886a579SRuss Weight info.get_bridges = fme_region_get_bridges;
46*8886a579SRuss Weight info.priv = pdata;
47*8886a579SRuss Weight region = fpga_region_register_full(dev, &info);
48*8886a579SRuss Weight if (IS_ERR(region)) {
49*8886a579SRuss Weight ret = PTR_ERR(region);
50bb61b9beSWu Hao goto eprobe_mgr_put;
51bb61b9beSWu Hao }
52bb61b9beSWu Hao
53bb61b9beSWu Hao platform_set_drvdata(pdev, region);
54bb61b9beSWu Hao
55bb61b9beSWu Hao dev_dbg(dev, "DFL FME FPGA Region probed\n");
56bb61b9beSWu Hao
57bb61b9beSWu Hao return 0;
58bb61b9beSWu Hao
59bb61b9beSWu Hao eprobe_mgr_put:
60bb61b9beSWu Hao fpga_mgr_put(mgr);
61bb61b9beSWu Hao return ret;
62bb61b9beSWu Hao }
63bb61b9beSWu Hao
fme_region_remove(struct platform_device * pdev)64bb61b9beSWu Hao static int fme_region_remove(struct platform_device *pdev)
65bb61b9beSWu Hao {
66b77c9878SMoritz Fischer struct fpga_region *region = platform_get_drvdata(pdev);
6734bd2833SAlan Tull struct fpga_manager *mgr = region->mgr;
68bb61b9beSWu Hao
69bb61b9beSWu Hao fpga_region_unregister(region);
7034bd2833SAlan Tull fpga_mgr_put(mgr);
71bb61b9beSWu Hao
72bb61b9beSWu Hao return 0;
73bb61b9beSWu Hao }
74bb61b9beSWu Hao
75bb61b9beSWu Hao static struct platform_driver fme_region_driver = {
76bb61b9beSWu Hao .driver = {
77bb61b9beSWu Hao .name = DFL_FPGA_FME_REGION,
78bb61b9beSWu Hao },
79bb61b9beSWu Hao .probe = fme_region_probe,
80bb61b9beSWu Hao .remove = fme_region_remove,
81bb61b9beSWu Hao };
82bb61b9beSWu Hao
83bb61b9beSWu Hao module_platform_driver(fme_region_driver);
84bb61b9beSWu Hao
85bb61b9beSWu Hao MODULE_DESCRIPTION("FPGA Region for DFL FPGA Management Engine");
86bb61b9beSWu Hao MODULE_AUTHOR("Intel Corporation");
87bb61b9beSWu Hao MODULE_LICENSE("GPL v2");
88bb61b9beSWu Hao MODULE_ALIAS("platform:dfl-fme-region");
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