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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_slc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * LPC32xx SLC NAND flash controller driver
5 * (C) Copyright 2015-2018 Vladimir Zapolskiy <vz@mleia.com>
21 #include <asm/arch/dma.h>
44 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
46 #define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
47 #define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
52 #define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
55 #define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
87 * DMA Descriptors
[all …]
H A Dmxs_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
9 * Freescale GPMI NFC NAND Flash Driver
24 #include <asm/arch/imx-regs.h>
25 #include <asm/mach-imx/regs-bch.h>
26 #include <asm/mach-imx/regs-gpmi.h>
56 uint32_t addr = (uint32_t)info->data_buf; in mxs_nand_flush_data_buf()
58 flush_dcache_range(addr, addr + info->data_buf_size); in mxs_nand_flush_data_buf()
63 uint32_t addr = (uint32_t)info->data_buf; in mxs_nand_inval_data_buf()
65 invalidate_dcache_range(addr, addr + info->data_buf_size); in mxs_nand_inval_data_buf()
[all …]
H A Dmxs_nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * NXP GPMI NAND flash driver
13 #include <asm/mach-imx/dma.h>
23 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
25 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
66 /* DMA descriptors */
/openbmc/u-boot/board/freescale/m547xevb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m547xevb/mii.c MII init
14 - board/freescale/m547xevb/Makefile Makefile
15 - board/freescale/m547xevb/config.mk config make
16 - board/freescale/m547xevb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
20 - arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
[all …]
/openbmc/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c34 #include "hw/block/flash.h"
37 #include "hw/char/serial-mm.h"
38 #include "hw/qdev-properties.h"
39 #include "system/address-spaces.h"
49 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
72 ram_addr_t ram_size = machine->ram_size; in petalogix_ml605_init()
74 DeviceState *dev, *dma, *eth0; in petalogix_ml605_init() local
90 object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); in petalogix_ml605_init()
91 object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, in petalogix_ml605_init()
93 object_property_set_bool(OBJECT(cpu), "little-endian", true, &error_abort); in petalogix_ml605_init()
[all …]
/openbmc/u-boot/arch/sandbox/dts/
H A Dtest.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
27 testfdt6 = "/e-test";
28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6338.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6338-clock.h>
7 #include <dt-bindings/dma/bcm6338-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6338-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6348.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6348-clock.h>
7 #include <dt-bindings/dma/bcm6348-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6348-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6368.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6368-clock.h>
7 #include <dt-bindings/dma/bcm6368-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6368-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6358.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6358-clock.h>
7 #include <dt-bindings/dma/bcm6358-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6358-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
/openbmc/qemu/hw/ssi/
H A Daspeed_smc.c2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
26 #include "hw/block/flash.h"
31 #include "qemu/error-report.h"
37 #include "hw/qdev-properties.h"
80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
135 /* DMA DRAM Side Address High Part (AST2700) */
138 /* DMA Control/Status Register */
151 /* DMA Flash Side Address */
[all …]
/openbmc/u-boot/arch/x86/cpu/quark/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
29 to the resulting U-Boot image. It is a data block (up to 64K) of
30 machine-specific code which must be put in the flash for the RMU
48 put in flash at a location matching the strap-determined base address.
51 be located at offset 0 from the beginning of a 1MB flash device.
71 Embedded SRAM (eSRAM) memory-mapped base address.
81 Root Complex register block memory-mapped base address.
87 ACPI Power Management 1 (PM1) i/o-mapped base address.
94 ACPI Processor Block (PBLK) i/o-mapped base address.
101 SPI DMA i/o-mapped base address.
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dspl_a10.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/u-boot.h>
34 const u32 bsel = readl(&sysmgr_regs->bootinfo); in spl_boot_device()
39 case 0x2: /* NAND Flash (1.8V) */ in spl_boot_device()
40 case 0x3: /* NAND Flash (3.0V) */ in spl_boot_device()
46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device()
48 case 0x6: /* QSPI Flash (1.8V) */ in spl_boot_device()
49 case 0x7: /* QSPI Flash (3.0V) */ in spl_boot_device()
92 cm_basic_init(gd->fdt_blob); in board_init_f()
103 config_dedicated_pins(gd->fdt_blob); in board_init_f()
/openbmc/u-boot/doc/
H A DREADME.m54418twr4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m54418twr/m54418twr.c Dram setup
13 - board/freescale/m54418twr/Makefile Makefile
14 - board/freescale/m54418twr/config.mk config make
15 - board/freescale/m54418twr/u-boot.lds Linker description
16 - board/freescale/m54418twr/sbf_dram_init.S
19 - arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
20 - arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
21 - arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
22 - arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
16 #define DMA_BASE 0x31000000 /* DMA controller registers base */
/openbmc/u-boot/board/freescale/m52277evb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m52277evb/m52277evb.c Dram setup
13 - board/freescale/m52277evb/Makefile Makefile
14 - board/freescale/m52277evb/config.mk config make
15 - board/freescale/m52277evb/u-boot.lds Linker description
17 - arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
18 - arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
19 - arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
20 - arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
21 - arch/m68k/cpu/mcf5227x/Makefile Makefile
[all …]
/openbmc/u-boot/arch/riscv/dts/
H A Dae350_64.dts1 /dts-v1/;
4 #address-cells = <2>;
5 #size-cells = <2>;
16 stdout-path = "uart0:38400n8";
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <60000000>;
29 mmu-type = "riscv,sv39";
30 clock-frequency = <60000000>;
31 d-cache-size = <0x8000>;
[all …]
H A Dae350_32.dts1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
16 stdout-path = "uart0:38400n8";
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <60000000>;
29 mmu-type = "riscv,sv32";
30 clock-frequency = <60000000>;
31 d-cache-size = <0x8000>;
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
[all …]
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
21 ECC, up to 400-MHz clock/800 MHz data rate
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dutils.S1 // SPDX-License-Identifier: GPL-2.0
4 * Chia-Wei Wang <chiawei_wang@aspeedtech.com>
21 * perform FMC SPI DMA to speed up flash copy.
24 * @count: number of bytes to be copied, 4-byte aligned
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dutils.S1 // SPDX-License-Identifier: GPL-2.0
4 * Chia-Wei Wang <chiawei_wang@aspeedtech.com>
21 * perform FMC SPI DMA to speed up flash copy.
24 * @count: number of bytes to be copied, 4-byte aligned
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
182 #define DCWR_COPY 0 /* Copy-back */
183 #define DCWR_WRITE 1 /* Write-through */
211 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
212 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
213 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
/openbmc/u-boot/include/configs/
H A Dpcm058.h1 /* SPDX-License-Identifier: GPL-2.0+ */
40 /* SPI Flash */
57 /* DMA stuff, needed for GPMI/MXS NAND support */
69 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

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