1 /*
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "qemu/log.h"
29 #include "qemu/module.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
32 #include "qemu/units.h"
33 #include "trace.h"
34
35 #include "hw/irq.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/ssi/aspeed_smc.h"
38
39 /* CE Type Setting Register */
40 #define R_CONF (0x00 / 4)
41 #define CONF_LEGACY_DISABLE (1 << 31)
42 #define CONF_ENABLE_W4 20
43 #define CONF_ENABLE_W3 19
44 #define CONF_ENABLE_W2 18
45 #define CONF_ENABLE_W1 17
46 #define CONF_ENABLE_W0 16
47 #define CONF_FLASH_TYPE4 8
48 #define CONF_FLASH_TYPE3 6
49 #define CONF_FLASH_TYPE2 4
50 #define CONF_FLASH_TYPE1 2
51 #define CONF_FLASH_TYPE0 0
52 #define CONF_FLASH_TYPE_NOR 0x0
53 #define CONF_FLASH_TYPE_NAND 0x1
54 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
55
56 /* CE Control Register */
57 #define R_CE_CTRL (0x04 / 4)
58 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
59 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
60 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
61 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
62 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
63
64 /* Interrupt Control and Status Register */
65 #define R_INTR_CTRL (0x08 / 4)
66 #define INTR_CTRL_DMA_STATUS (1 << 11)
67 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
68 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
69 #define INTR_CTRL_DMA_EN (1 << 3)
70 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
71 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
72
73 /* Command Control Register */
74 #define R_CE_CMD_CTRL (0x0C / 4)
75 #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
76 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
77
78 #define aspeed_smc_addr_byte_enabled(s, i) \
79 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
80 #define aspeed_smc_data_byte_enabled(s, i) \
81 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
82
83 /* CEx Control Register */
84 #define R_CTRL0 (0x10 / 4)
85 #define CTRL_IO_QPI (1 << 31)
86 #define CTRL_IO_QUAD_DATA (1 << 30)
87 #define CTRL_IO_DUAL_DATA (1 << 29)
88 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
89 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */
90 #define CTRL_CMD_SHIFT 16
91 #define CTRL_CMD_MASK 0xff
92 #define CTRL_DUMMY_HIGH_SHIFT 14
93 #define CTRL_AST2400_SPI_4BYTE (1 << 13)
94 #define CE_CTRL_CLOCK_FREQ_SHIFT 8
95 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
96 #define CE_CTRL_CLOCK_FREQ(div) \
97 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
98 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
99 #define CTRL_CE_STOP_ACTIVE (1 << 2)
100 #define CTRL_CMD_MODE_MASK 0x3
101 #define CTRL_READMODE 0x0
102 #define CTRL_FREADMODE 0x1
103 #define CTRL_WRITEMODE 0x2
104 #define CTRL_USERMODE 0x3
105 #define R_CTRL1 (0x14 / 4)
106 #define R_CTRL2 (0x18 / 4)
107 #define R_CTRL3 (0x1C / 4)
108 #define R_CTRL4 (0x20 / 4)
109
110 /* CEx Segment Address Register */
111 #define R_SEG_ADDR0 (0x30 / 4)
112 #define SEG_END_SHIFT 24 /* 8MB units */
113 #define SEG_END_MASK 0xff
114 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
115 #define SEG_START_MASK 0xff
116 #define R_SEG_ADDR1 (0x34 / 4)
117 #define R_SEG_ADDR2 (0x38 / 4)
118 #define R_SEG_ADDR3 (0x3C / 4)
119 #define R_SEG_ADDR4 (0x40 / 4)
120
121 /* Misc Control Register #1 */
122 #define R_MISC_CTRL1 (0x50 / 4)
123
124 /* SPI dummy cycle data */
125 #define R_DUMMY_DATA (0x54 / 4)
126
127 /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */
128 #define R_FMC_WDT2_CTRL (0x64 / 4)
129 #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */
130 #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5)
131 #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */
132 #define FMC_WDT2_CTRL_EN BIT(0)
133 #define R_FMC_WDT2_RELOAD (0x68 / 4)
134 #define R_FMC_WDT2_RESTART (0x6C / 4)
135
136 /* DMA Control/Status Register */
137 #define R_DMA_CTRL (0x80 / 4)
138 #define DMA_CTRL_REQUEST (1 << 31)
139 #define DMA_CTRL_GRANT (1 << 30)
140 #define DMA_CTRL_DELAY_MASK 0xf
141 #define DMA_CTRL_DELAY_SHIFT 8
142 #define DMA_CTRL_FREQ_MASK 0xf
143 #define DMA_CTRL_FREQ_SHIFT 4
144 #define DMA_CTRL_CALIB (1 << 3)
145 #define DMA_CTRL_CKSUM (1 << 2)
146 #define DMA_CTRL_WRITE (1 << 1)
147 #define DMA_CTRL_ENABLE (1 << 0)
148
149 /* DMA Flash Side Address */
150 #define R_DMA_FLASH_ADDR (0x84 / 4)
151
152 /* DMA DRAM Side Address */
153 #define R_DMA_DRAM_ADDR (0x88 / 4)
154
155 /* DMA Length Register */
156 #define R_DMA_LEN (0x8C / 4)
157
158 /* Checksum Calculation Result */
159 #define R_DMA_CHECKSUM (0x90 / 4)
160
161 /* Read Timing Compensation Register */
162 #define R_TIMINGS (0x94 / 4)
163
164 /* SPI controller registers and bits (AST2400) */
165 #define R_SPI_CONF (0x00 / 4)
166 #define SPI_CONF_ENABLE_W0 0
167 #define R_SPI_CTRL0 (0x4 / 4)
168 #define R_SPI_MISC_CTRL (0x10 / 4)
169 #define R_SPI_TIMINGS (0x14 / 4)
170
171 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
172 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
173
174 /*
175 * DMA DRAM addresses should be 4 bytes aligned and the valid address
176 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
177 * 0x80000000 - 0xBFFFFFFF (AST2500)
178 *
179 * DMA flash addresses should be 4 bytes aligned and the valid address
180 * range is 0x20000000 - 0x2FFFFFFF.
181 *
182 * DMA length is from 4 bytes to 32MB
183 * 0: 4 bytes
184 * 0x7FFFFF: 32M bytes
185 */
186 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
187 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
188 #define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
189
190 /* Flash opcodes. */
191 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
192
193 #define SNOOP_OFF 0xFF
194 #define SNOOP_START 0x0
195
196 /*
197 * Default segments mapping addresses and size for each peripheral per
198 * controller. These can be changed when board is initialized with the
199 * Segment Address Registers.
200 */
201 static const AspeedSegments aspeed_2500_spi1_segments[];
202 static const AspeedSegments aspeed_2500_spi2_segments[];
203
204 #define ASPEED_SMC_FEATURE_DMA 0x1
205 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
206 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
207
aspeed_smc_has_dma(const AspeedSMCClass * asc)208 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)
209 {
210 return !!(asc->features & ASPEED_SMC_FEATURE_DMA);
211 }
212
aspeed_smc_has_wdt_control(const AspeedSMCClass * asc)213 static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc)
214 {
215 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);
216 }
217
218 #define aspeed_smc_error(fmt, ...) \
219 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)
220
aspeed_smc_flash_overlap(const AspeedSMCState * s,const AspeedSegments * new,int cs)221 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
222 const AspeedSegments *new,
223 int cs)
224 {
225 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
226 AspeedSegments seg;
227 int i;
228
229 for (i = 0; i < asc->cs_num_max; i++) {
230 if (i == cs) {
231 continue;
232 }
233
234 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
235
236 if (new->addr + new->size > seg.addr &&
237 new->addr < seg.addr + seg.size) {
238 aspeed_smc_error("new segment CS%d [ 0x%"
239 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
240 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
241 cs, new->addr, new->addr + new->size,
242 i, seg.addr, seg.addr + seg.size);
243 return true;
244 }
245 }
246 return false;
247 }
248
aspeed_smc_flash_set_segment_region(AspeedSMCState * s,int cs,uint64_t regval)249 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
250 uint64_t regval)
251 {
252 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
253 AspeedSMCFlash *fl = &s->flashes[cs];
254 AspeedSegments seg;
255
256 asc->reg_to_segment(s, regval, &seg);
257
258 memory_region_transaction_begin();
259 memory_region_set_size(&fl->mmio, seg.size);
260 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base);
261 memory_region_set_enabled(&fl->mmio, !!seg.size);
262 memory_region_transaction_commit();
263
264 if (asc->segment_addr_mask) {
265 regval &= asc->segment_addr_mask;
266 }
267
268 s->regs[R_SEG_ADDR0 + cs] = regval;
269 }
270
aspeed_smc_flash_set_segment(AspeedSMCState * s,int cs,uint64_t new)271 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
272 uint64_t new)
273 {
274 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
275 AspeedSegments seg;
276
277 asc->reg_to_segment(s, new, &seg);
278
279 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
280
281 /* The start address of CS0 is read-only */
282 if (cs == 0 && seg.addr != asc->flash_window_base) {
283 aspeed_smc_error("Tried to change CS0 start address to 0x%"
284 HWADDR_PRIx, seg.addr);
285 seg.addr = asc->flash_window_base;
286 new = asc->segment_to_reg(s, &seg);
287 }
288
289 /*
290 * The end address of the AST2500 spi controllers is also
291 * read-only.
292 */
293 if ((asc->segments == aspeed_2500_spi1_segments ||
294 asc->segments == aspeed_2500_spi2_segments) &&
295 cs == asc->cs_num_max &&
296 seg.addr + seg.size != asc->segments[cs].addr +
297 asc->segments[cs].size) {
298 aspeed_smc_error("Tried to change CS%d end address to 0x%"
299 HWADDR_PRIx, cs, seg.addr + seg.size);
300 seg.size = asc->segments[cs].addr + asc->segments[cs].size -
301 seg.addr;
302 new = asc->segment_to_reg(s, &seg);
303 }
304
305 /* Keep the segment in the overall flash window */
306 if (seg.size &&
307 (seg.addr + seg.size <= asc->flash_window_base ||
308 seg.addr > asc->flash_window_base + asc->flash_window_size)) {
309 aspeed_smc_error("new segment for CS%d is invalid : "
310 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
311 cs, seg.addr, seg.addr + seg.size);
312 return;
313 }
314
315 /* Check start address vs. alignment */
316 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
317 aspeed_smc_error("new segment for CS%d is not "
318 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
319 cs, seg.addr, seg.addr + seg.size);
320 }
321
322 /* And segments should not overlap (in the specs) */
323 aspeed_smc_flash_overlap(s, &seg, cs);
324
325 /* All should be fine now to move the region */
326 aspeed_smc_flash_set_segment_region(s, cs, new);
327 }
328
aspeed_smc_flash_default_read(void * opaque,hwaddr addr,unsigned size)329 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
330 unsigned size)
331 {
332 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size);
333 return 0;
334 }
335
aspeed_smc_flash_default_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)336 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
337 uint64_t data, unsigned size)
338 {
339 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64,
340 addr, size, data);
341 }
342
343 static const MemoryRegionOps aspeed_smc_flash_default_ops = {
344 .read = aspeed_smc_flash_default_read,
345 .write = aspeed_smc_flash_default_write,
346 .endianness = DEVICE_LITTLE_ENDIAN,
347 .valid = {
348 .min_access_size = 1,
349 .max_access_size = 4,
350 },
351 };
352
aspeed_smc_flash_mode(const AspeedSMCFlash * fl)353 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
354 {
355 const AspeedSMCState *s = fl->controller;
356
357 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK;
358 }
359
aspeed_smc_is_writable(const AspeedSMCFlash * fl)360 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
361 {
362 const AspeedSMCState *s = fl->controller;
363
364 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs));
365 }
366
aspeed_smc_flash_cmd(const AspeedSMCFlash * fl)367 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
368 {
369 const AspeedSMCState *s = fl->controller;
370 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
371
372 /*
373 * In read mode, the default SPI command is READ (0x3). In other
374 * modes, the command should necessarily be defined
375 *
376 * TODO: add support for READ4 (0x13) on AST2600
377 */
378 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
379 cmd = SPI_OP_READ;
380 }
381
382 if (!cmd) {
383 aspeed_smc_error("no command defined for mode %d",
384 aspeed_smc_flash_mode(fl));
385 }
386
387 return cmd;
388 }
389
aspeed_smc_flash_addr_width(const AspeedSMCFlash * fl)390 static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
391 {
392 const AspeedSMCState *s = fl->controller;
393 AspeedSMCClass *asc = fl->asc;
394
395 if (asc->addr_width) {
396 return asc->addr_width(s);
397 } else {
398 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3;
399 }
400 }
401
aspeed_smc_flash_do_select(AspeedSMCFlash * fl,bool unselect)402 static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
403 {
404 AspeedSMCState *s = fl->controller;
405
406 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : "");
407
408 qemu_set_irq(s->cs_lines[fl->cs], unselect);
409 }
410
aspeed_smc_flash_select(AspeedSMCFlash * fl)411 static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
412 {
413 aspeed_smc_flash_do_select(fl, false);
414 }
415
aspeed_smc_flash_unselect(AspeedSMCFlash * fl)416 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
417 {
418 aspeed_smc_flash_do_select(fl, true);
419 }
420
aspeed_smc_check_segment_addr(const AspeedSMCFlash * fl,uint32_t addr)421 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
422 uint32_t addr)
423 {
424 const AspeedSMCState *s = fl->controller;
425 AspeedSMCClass *asc = fl->asc;
426 AspeedSegments seg;
427
428 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
429 if ((addr % seg.size) != addr) {
430 aspeed_smc_error("invalid address 0x%08x for CS%d segment : "
431 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
432 addr, fl->cs, seg.addr, seg.addr + seg.size);
433 addr %= seg.size;
434 }
435
436 return addr;
437 }
438
aspeed_smc_flash_dummies(const AspeedSMCFlash * fl)439 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
440 {
441 const AspeedSMCState *s = fl->controller;
442 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs];
443 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
444 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
445 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
446
447 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
448 dummies /= 2;
449 }
450
451 return dummies;
452 }
453
aspeed_smc_flash_setup(AspeedSMCFlash * fl,uint32_t addr)454 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
455 {
456 const AspeedSMCState *s = fl->controller;
457 uint8_t cmd = aspeed_smc_flash_cmd(fl);
458 int i = aspeed_smc_flash_addr_width(fl);
459
460 /* Flash access can not exceed CS segment */
461 addr = aspeed_smc_check_segment_addr(fl, addr);
462
463 ssi_transfer(s->spi, cmd);
464 while (i--) {
465 if (aspeed_smc_addr_byte_enabled(s, i)) {
466 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
467 }
468 }
469
470 /*
471 * Use fake transfers to model dummy bytes. The value should
472 * be configured to some non-zero value in fast read mode and
473 * zero in read mode. But, as the HW allows inconsistent
474 * settings, let's check for fast read mode.
475 */
476 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
477 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
478 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
479 }
480 }
481 }
482
aspeed_smc_flash_read(void * opaque,hwaddr addr,unsigned size)483 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
484 {
485 AspeedSMCFlash *fl = opaque;
486 AspeedSMCState *s = fl->controller;
487 uint64_t ret = 0;
488 int i;
489
490 switch (aspeed_smc_flash_mode(fl)) {
491 case CTRL_USERMODE:
492 for (i = 0; i < size; i++) {
493 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
494 }
495 break;
496 case CTRL_READMODE:
497 case CTRL_FREADMODE:
498 aspeed_smc_flash_select(fl);
499 aspeed_smc_flash_setup(fl, addr);
500
501 for (i = 0; i < size; i++) {
502 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
503 }
504
505 aspeed_smc_flash_unselect(fl);
506 break;
507 default:
508 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
509 }
510
511 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret,
512 aspeed_smc_flash_mode(fl));
513 return ret;
514 }
515
516 /*
517 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
518 * common include header.
519 */
520 typedef enum {
521 READ = 0x3, READ_4 = 0x13,
522 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
523 DOR = 0x3b, DOR_4 = 0x3c,
524 QOR = 0x6b, QOR_4 = 0x6c,
525 DIOR = 0xbb, DIOR_4 = 0xbc,
526 QIOR = 0xeb, QIOR_4 = 0xec,
527
528 PP = 0x2, PP_4 = 0x12,
529 DPP = 0xa2,
530 QPP = 0x32, QPP_4 = 0x34,
531 } FlashCMD;
532
aspeed_smc_num_dummies(uint8_t command)533 static int aspeed_smc_num_dummies(uint8_t command)
534 {
535 switch (command) { /* check for dummies */
536 case READ: /* no dummy bytes/cycles */
537 case PP:
538 case DPP:
539 case QPP:
540 case READ_4:
541 case PP_4:
542 case QPP_4:
543 return 0;
544 case FAST_READ:
545 case DOR:
546 case QOR:
547 case FAST_READ_4:
548 case DOR_4:
549 case QOR_4:
550 return 1;
551 case DIOR:
552 case DIOR_4:
553 return 2;
554 case QIOR:
555 case QIOR_4:
556 return 4;
557 default:
558 return -1;
559 }
560 }
561
aspeed_smc_do_snoop(AspeedSMCFlash * fl,uint64_t data,unsigned size)562 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
563 unsigned size)
564 {
565 AspeedSMCState *s = fl->controller;
566 uint8_t addr_width = aspeed_smc_flash_addr_width(fl);
567
568 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
569 (uint8_t) data & 0xff);
570
571 if (s->snoop_index == SNOOP_OFF) {
572 return false; /* Do nothing */
573
574 } else if (s->snoop_index == SNOOP_START) {
575 uint8_t cmd = data & 0xff;
576 int ndummies = aspeed_smc_num_dummies(cmd);
577
578 /*
579 * No dummy cycles are expected with the current command. Turn
580 * off snooping and let the transfer proceed normally.
581 */
582 if (ndummies <= 0) {
583 s->snoop_index = SNOOP_OFF;
584 return false;
585 }
586
587 s->snoop_dummies = ndummies * 8;
588
589 } else if (s->snoop_index >= addr_width + 1) {
590
591 /* The SPI transfer has reached the dummy cycles sequence */
592 for (; s->snoop_dummies; s->snoop_dummies--) {
593 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
594 }
595
596 /* If no more dummy cycles are expected, turn off snooping */
597 if (!s->snoop_dummies) {
598 s->snoop_index = SNOOP_OFF;
599 } else {
600 s->snoop_index += size;
601 }
602
603 /*
604 * Dummy cycles have been faked already. Ignore the current
605 * SPI transfer
606 */
607 return true;
608 }
609
610 s->snoop_index += size;
611 return false;
612 }
613
aspeed_smc_flash_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)614 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
615 unsigned size)
616 {
617 AspeedSMCFlash *fl = opaque;
618 AspeedSMCState *s = fl->controller;
619 int i;
620
621 trace_aspeed_smc_flash_write(fl->cs, addr, size, data,
622 aspeed_smc_flash_mode(fl));
623
624 if (!aspeed_smc_is_writable(fl)) {
625 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr);
626 return;
627 }
628
629 switch (aspeed_smc_flash_mode(fl)) {
630 case CTRL_USERMODE:
631 if (aspeed_smc_do_snoop(fl, data, size)) {
632 break;
633 }
634
635 for (i = 0; i < size; i++) {
636 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
637 }
638 break;
639 case CTRL_WRITEMODE:
640 aspeed_smc_flash_select(fl);
641 aspeed_smc_flash_setup(fl, addr);
642
643 for (i = 0; i < size; i++) {
644 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
645 }
646
647 aspeed_smc_flash_unselect(fl);
648 break;
649 default:
650 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
651 }
652 }
653
654 static const MemoryRegionOps aspeed_smc_flash_ops = {
655 .read = aspeed_smc_flash_read,
656 .write = aspeed_smc_flash_write,
657 .endianness = DEVICE_LITTLE_ENDIAN,
658 .valid = {
659 .min_access_size = 1,
660 .max_access_size = 4,
661 },
662 };
663
aspeed_smc_flash_update_ctrl(AspeedSMCFlash * fl,uint32_t value)664 static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
665 {
666 AspeedSMCState *s = fl->controller;
667 bool unselect;
668
669 /* User mode selects the CS, other modes unselect */
670 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
671
672 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
673 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) &&
674 value & CTRL_CE_STOP_ACTIVE) {
675 unselect = true;
676 }
677
678 s->regs[s->r_ctrl0 + fl->cs] = value;
679
680 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
681
682 aspeed_smc_flash_do_select(fl, unselect);
683 }
684
aspeed_smc_reset(DeviceState * d)685 static void aspeed_smc_reset(DeviceState *d)
686 {
687 AspeedSMCState *s = ASPEED_SMC(d);
688 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
689 int i;
690
691 if (asc->resets) {
692 memcpy(s->regs, asc->resets, sizeof s->regs);
693 } else {
694 memset(s->regs, 0, sizeof s->regs);
695 }
696
697 for (i = 0; i < asc->cs_num_max; i++) {
698 DeviceState *dev = ssi_get_cs(s->spi, i);
699 if (dev) {
700 qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
701 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
702 }
703 }
704
705 /* Unselect all peripherals */
706 for (i = 0; i < asc->cs_num_max; ++i) {
707 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
708 qemu_set_irq(s->cs_lines[i], true);
709 }
710
711 /* setup the default segment register values and regions for all */
712 for (i = 0; i < asc->cs_num_max; ++i) {
713 aspeed_smc_flash_set_segment_region(s, i,
714 asc->segment_to_reg(s, &asc->segments[i]));
715 }
716
717 s->snoop_index = SNOOP_OFF;
718 s->snoop_dummies = 0;
719 }
720
721 #define ASPEED_WDT_RELOAD 0x04
722 #define ASPEED_WDT_RESTART 0x08
723 #define ASPEED_WDT_CTRL 0x0C
724
aspeed_smc_wdt2_write(AspeedSMCState * s,uint32_t offset,uint32_t value)725 static void aspeed_smc_wdt2_write(AspeedSMCState *s, uint32_t offset,
726 uint32_t value)
727 {
728 MemTxResult result;
729
730 address_space_stl_le(&s->wdt2_as, offset, value, MEMTXATTRS_UNSPECIFIED,
731 &result);
732 if (result != MEMTX_OK) {
733 aspeed_smc_error("WDT2 write failed @%08x", offset);
734 return;
735 }
736 }
737
aspeed_smc_wdt2_read(AspeedSMCState * s,uint32_t offset)738 static uint64_t aspeed_smc_wdt2_read(AspeedSMCState *s, uint32_t offset)
739 {
740 MemTxResult result;
741 uint32_t value;
742
743 value = address_space_ldl_le(&s->wdt2_as, offset, MEMTXATTRS_UNSPECIFIED,
744 &result);
745 if (result != MEMTX_OK) {
746 aspeed_smc_error("WDT2 read failed @%08x", offset);
747 return -1;
748 }
749 return value;
750 }
751
aspeed_smc_wdt2_enable(AspeedSMCState * s,bool enable)752 static void aspeed_smc_wdt2_enable(AspeedSMCState *s, bool enable)
753 {
754 uint32_t value;
755
756 value = aspeed_smc_wdt2_read(s, ASPEED_WDT_CTRL);
757 if (value == -1) {
758 return;
759 }
760
761 value &= ~BIT(0);
762 value |= enable;
763
764 aspeed_smc_wdt2_write(s, ASPEED_WDT_CTRL, value);
765
766 trace_aspeed_smc_wdt2_enable(enable ? "en" : "dis");
767 }
768
aspeed_smc_read(void * opaque,hwaddr addr,unsigned int size)769 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
770 {
771 AspeedSMCState *s = ASPEED_SMC(opaque);
772 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque);
773
774 addr >>= 2;
775
776 if (addr == s->r_conf ||
777 (addr >= s->r_timings &&
778 addr < s->r_timings + asc->nregs_timings) ||
779 addr == s->r_ce_ctrl ||
780 addr == R_CE_CMD_CTRL ||
781 addr == R_INTR_CTRL ||
782 addr == R_DUMMY_DATA ||
783 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||
784 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||
785 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||
786 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||
787 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||
788 (addr >= R_SEG_ADDR0 &&
789 addr < R_SEG_ADDR0 + asc->cs_num_max) ||
790 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) {
791
792 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]);
793
794 return s->regs[addr];
795 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) {
796 return aspeed_smc_wdt2_read(s, ASPEED_WDT_CTRL);
797 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_RELOAD) {
798 return aspeed_smc_wdt2_read(s, ASPEED_WDT_RELOAD) / 100000;
799 } else {
800 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
801 __func__, addr);
802 return -1;
803 }
804 }
805
aspeed_smc_hclk_divisor(uint8_t hclk_mask)806 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
807 {
808 /* HCLK/1 .. HCLK/16 */
809 const uint8_t hclk_divisors[] = {
810 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
811 };
812 int i;
813
814 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
815 if (hclk_mask == hclk_divisors[i]) {
816 return i + 1;
817 }
818 }
819
820 aspeed_smc_error("invalid HCLK mask %x", hclk_mask);
821 return 0;
822 }
823
824 /*
825 * When doing calibration, the SPI clock rate in the CE0 Control
826 * Register and the read delay cycles in the Read Timing Compensation
827 * Register are set using bit[11:4] of the DMA Control Register.
828 */
aspeed_smc_dma_calibration(AspeedSMCState * s)829 static void aspeed_smc_dma_calibration(AspeedSMCState *s)
830 {
831 uint8_t delay =
832 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
833 uint8_t hclk_mask =
834 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
835 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
836 uint32_t hclk_shift = (hclk_div - 1) << 2;
837 uint8_t cs;
838
839 /*
840 * The Read Timing Compensation Register values apply to all CS on
841 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
842 */
843 if (hclk_div && hclk_div < 6) {
844 s->regs[s->r_timings] &= ~(0xf << hclk_shift);
845 s->regs[s->r_timings] |= delay << hclk_shift;
846 }
847
848 /*
849 * TODO: compute the CS from the DMA address and the segment
850 * registers. This is not really a problem for now because the
851 * Timing Register values apply to all CS and software uses CS0 to
852 * do calibration.
853 */
854 cs = 0;
855 s->regs[s->r_ctrl0 + cs] &=
856 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
857 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
858 }
859
860 /*
861 * Emulate read errors in the DMA Checksum Register for high
862 * frequencies and optimistic settings of the Read Timing Compensation
863 * Register. This will help in tuning the SPI timing calibration
864 * algorithm.
865 */
aspeed_smc_inject_read_failure(AspeedSMCState * s)866 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
867 {
868 uint8_t delay =
869 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
870 uint8_t hclk_mask =
871 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
872
873 /*
874 * Typical values of a palmetto-bmc machine.
875 */
876 switch (aspeed_smc_hclk_divisor(hclk_mask)) {
877 case 4 ... 16:
878 return false;
879 case 3: /* at least one HCLK cycle delay */
880 return (delay & 0x7) < 1;
881 case 2: /* at least two HCLK cycle delay */
882 return (delay & 0x7) < 2;
883 case 1: /* (> 100MHz) is above the max freq of the controller */
884 return true;
885 default:
886 g_assert_not_reached();
887 }
888 }
889
890 /*
891 * Accumulate the result of the reads to provide a checksum that will
892 * be used to validate the read timing settings.
893 */
aspeed_smc_dma_checksum(AspeedSMCState * s)894 static void aspeed_smc_dma_checksum(AspeedSMCState *s)
895 {
896 MemTxResult result;
897 uint32_t data;
898
899 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
900 aspeed_smc_error("invalid direction for DMA checksum");
901 return;
902 }
903
904 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
905 aspeed_smc_dma_calibration(s);
906 }
907
908 while (s->regs[R_DMA_LEN]) {
909 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
910 MEMTXATTRS_UNSPECIFIED, &result);
911 if (result != MEMTX_OK) {
912 aspeed_smc_error("Flash read failed @%08x",
913 s->regs[R_DMA_FLASH_ADDR]);
914 return;
915 }
916 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
917
918 /*
919 * When the DMA is on-going, the DMA registers are updated
920 * with the current working addresses and length.
921 */
922 s->regs[R_DMA_CHECKSUM] += data;
923 s->regs[R_DMA_FLASH_ADDR] += 4;
924 s->regs[R_DMA_LEN] -= 4;
925 }
926
927 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
928 s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
929 }
930
931 }
932
aspeed_smc_dma_rw(AspeedSMCState * s)933 static void aspeed_smc_dma_rw(AspeedSMCState *s)
934 {
935 MemTxResult result;
936 uint32_t data;
937
938 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
939 "write" : "read",
940 s->regs[R_DMA_FLASH_ADDR],
941 s->regs[R_DMA_DRAM_ADDR],
942 s->regs[R_DMA_LEN]);
943 while (s->regs[R_DMA_LEN]) {
944 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
945 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
946 MEMTXATTRS_UNSPECIFIED, &result);
947 if (result != MEMTX_OK) {
948 aspeed_smc_error("DRAM read failed @%08x",
949 s->regs[R_DMA_DRAM_ADDR]);
950 return;
951 }
952
953 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
954 data, MEMTXATTRS_UNSPECIFIED, &result);
955 if (result != MEMTX_OK) {
956 aspeed_smc_error("Flash write failed @%08x",
957 s->regs[R_DMA_FLASH_ADDR]);
958 return;
959 }
960 } else {
961 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
962 MEMTXATTRS_UNSPECIFIED, &result);
963 if (result != MEMTX_OK) {
964 aspeed_smc_error("Flash read failed @%08x",
965 s->regs[R_DMA_FLASH_ADDR]);
966 return;
967 }
968
969 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
970 data, MEMTXATTRS_UNSPECIFIED, &result);
971 if (result != MEMTX_OK) {
972 aspeed_smc_error("DRAM write failed @%08x",
973 s->regs[R_DMA_DRAM_ADDR]);
974 return;
975 }
976 }
977
978 /*
979 * When the DMA is on-going, the DMA registers are updated
980 * with the current working addresses and length.
981 */
982 s->regs[R_DMA_FLASH_ADDR] += 4;
983 s->regs[R_DMA_DRAM_ADDR] += 4;
984 s->regs[R_DMA_LEN] -= 4;
985 s->regs[R_DMA_CHECKSUM] += data;
986 }
987 }
988
aspeed_smc_dma_stop(AspeedSMCState * s)989 static void aspeed_smc_dma_stop(AspeedSMCState *s)
990 {
991 /*
992 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
993 * engine is idle
994 */
995 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
996 s->regs[R_DMA_CHECKSUM] = 0;
997
998 /*
999 * Lower the DMA irq in any case. The IRQ control register could
1000 * have been cleared before disabling the DMA.
1001 */
1002 qemu_irq_lower(s->irq);
1003 }
1004
1005 /*
1006 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
1007 * can start even if the result of the previous was not collected.
1008 */
aspeed_smc_dma_in_progress(AspeedSMCState * s)1009 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
1010 {
1011 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
1012 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
1013 }
1014
aspeed_smc_dma_done(AspeedSMCState * s)1015 static void aspeed_smc_dma_done(AspeedSMCState *s)
1016 {
1017 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
1018 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
1019 qemu_irq_raise(s->irq);
1020 }
1021 }
1022
aspeed_smc_dma_ctrl(AspeedSMCState * s,uint32_t dma_ctrl)1023 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
1024 {
1025 if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
1026 s->regs[R_DMA_CTRL] = dma_ctrl;
1027
1028 aspeed_smc_dma_stop(s);
1029 return;
1030 }
1031
1032 if (aspeed_smc_dma_in_progress(s)) {
1033 aspeed_smc_error("DMA in progress !");
1034 return;
1035 }
1036
1037 s->regs[R_DMA_CTRL] = dma_ctrl;
1038
1039 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
1040 aspeed_smc_dma_checksum(s);
1041 } else {
1042 aspeed_smc_dma_rw(s);
1043 }
1044
1045 aspeed_smc_dma_done(s);
1046 }
1047
aspeed_smc_dma_granted(AspeedSMCState * s)1048 static inline bool aspeed_smc_dma_granted(AspeedSMCState *s)
1049 {
1050 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1051
1052 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) {
1053 return true;
1054 }
1055
1056 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {
1057 aspeed_smc_error("DMA not granted");
1058 return false;
1059 }
1060
1061 return true;
1062 }
1063
aspeed_2600_smc_dma_ctrl(AspeedSMCState * s,uint32_t dma_ctrl)1064 static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
1065 {
1066 /* Preserve DMA bits */
1067 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1068
1069 if (dma_ctrl == 0xAEED0000) {
1070 /* automatically grant request */
1071 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1072 return;
1073 }
1074
1075 /* clear request */
1076 if (dma_ctrl == 0xDEEA0000) {
1077 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1078 return;
1079 }
1080
1081 if (!aspeed_smc_dma_granted(s)) {
1082 aspeed_smc_error("DMA not granted");
1083 return;
1084 }
1085
1086 aspeed_smc_dma_ctrl(s, dma_ctrl);
1087 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1088 }
1089
aspeed_smc_write(void * opaque,hwaddr addr,uint64_t data,unsigned int size)1090 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
1091 unsigned int size)
1092 {
1093 AspeedSMCState *s = ASPEED_SMC(opaque);
1094 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1095 uint32_t value = data;
1096
1097 trace_aspeed_smc_write(addr, size, data);
1098
1099 addr >>= 2;
1100
1101 if (addr == s->r_conf ||
1102 (addr >= s->r_timings &&
1103 addr < s->r_timings + asc->nregs_timings) ||
1104 addr == s->r_ce_ctrl) {
1105 s->regs[addr] = value;
1106 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) {
1107 int cs = addr - s->r_ctrl0;
1108 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
1109 } else if (addr >= R_SEG_ADDR0 &&
1110 addr < R_SEG_ADDR0 + asc->cs_num_max) {
1111 int cs = addr - R_SEG_ADDR0;
1112
1113 if (value != s->regs[R_SEG_ADDR0 + cs]) {
1114 aspeed_smc_flash_set_segment(s, cs, value);
1115 }
1116 } else if (addr == R_CE_CMD_CTRL) {
1117 s->regs[addr] = value & 0xff;
1118 } else if (addr == R_DUMMY_DATA) {
1119 s->regs[addr] = value & 0xff;
1120 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) {
1121 aspeed_smc_wdt2_enable(s, !!(value & FMC_WDT2_CTRL_EN));
1122 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_RELOAD) {
1123 aspeed_smc_wdt2_write(s, ASPEED_WDT_RELOAD, value * 100000);
1124 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_RESTART) {
1125 aspeed_smc_wdt2_write(s, ASPEED_WDT_RESTART, value);
1126 } else if (addr == R_INTR_CTRL) {
1127 s->regs[addr] = value;
1128 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) {
1129 asc->dma_ctrl(s, value);
1130 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR &&
1131 aspeed_smc_dma_granted(s)) {
1132 s->regs[addr] = DMA_DRAM_ADDR(asc, value);
1133 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR &&
1134 aspeed_smc_dma_granted(s)) {
1135 s->regs[addr] = DMA_FLASH_ADDR(asc, value);
1136 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&
1137 aspeed_smc_dma_granted(s)) {
1138 s->regs[addr] = DMA_LENGTH(value);
1139 } else {
1140 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
1141 __func__, addr);
1142 return;
1143 }
1144 }
1145
1146 static const MemoryRegionOps aspeed_smc_ops = {
1147 .read = aspeed_smc_read,
1148 .write = aspeed_smc_write,
1149 .endianness = DEVICE_LITTLE_ENDIAN,
1150 };
1151
aspeed_smc_instance_init(Object * obj)1152 static void aspeed_smc_instance_init(Object *obj)
1153 {
1154 AspeedSMCState *s = ASPEED_SMC(obj);
1155 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1156 int i;
1157
1158 for (i = 0; i < asc->cs_num_max; i++) {
1159 object_initialize_child(obj, "flash[*]", &s->flashes[i],
1160 TYPE_ASPEED_SMC_FLASH);
1161 }
1162 }
1163
1164 /*
1165 * Initialize the custom address spaces for DMAs
1166 */
aspeed_smc_dma_setup(AspeedSMCState * s,Error ** errp)1167 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
1168 {
1169 if (!s->dram_mr) {
1170 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
1171 return;
1172 }
1173
1174 address_space_init(&s->flash_as, &s->mmio_flash,
1175 TYPE_ASPEED_SMC ".dma-flash");
1176 address_space_init(&s->dram_as, s->dram_mr,
1177 TYPE_ASPEED_SMC ".dma-dram");
1178 }
1179
aspeed_smc_wdt_setup(AspeedSMCState * s,Error ** errp)1180 static void aspeed_smc_wdt_setup(AspeedSMCState *s, Error **errp)
1181 {
1182 if (!s->wdt2_mr) {
1183 error_setg(errp, TYPE_ASPEED_SMC ": 'wdt2' link not set");
1184 return;
1185 }
1186
1187 address_space_init(&s->wdt2_as, s->wdt2_mr, TYPE_ASPEED_SMC ".wdt2");
1188 }
1189
aspeed_smc_realize(DeviceState * dev,Error ** errp)1190 static void aspeed_smc_realize(DeviceState *dev, Error **errp)
1191 {
1192 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1193 AspeedSMCState *s = ASPEED_SMC(dev);
1194 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1195 int i;
1196 hwaddr offset = 0;
1197
1198 /* keep a copy under AspeedSMCState to speed up accesses */
1199 s->r_conf = asc->r_conf;
1200 s->r_ce_ctrl = asc->r_ce_ctrl;
1201 s->r_ctrl0 = asc->r_ctrl0;
1202 s->r_timings = asc->r_timings;
1203 s->conf_enable_w0 = asc->conf_enable_w0;
1204
1205 /* DMA irq. Keep it first for the initialization in the SoC */
1206 sysbus_init_irq(sbd, &s->irq);
1207
1208 s->spi = ssi_create_bus(dev, NULL);
1209
1210 /* Setup cs_lines for peripherals */
1211 s->cs_lines = g_new0(qemu_irq, asc->cs_num_max);
1212 qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max);
1213
1214 /* The memory region for the controller registers */
1215 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
1216 TYPE_ASPEED_SMC, asc->nregs * 4);
1217 sysbus_init_mmio(sbd, &s->mmio);
1218
1219 /*
1220 * The container memory region representing the address space
1221 * window in which the flash modules are mapped. The size and
1222 * address depends on the SoC model and controller type.
1223 */
1224 memory_region_init(&s->mmio_flash_container, OBJECT(s),
1225 TYPE_ASPEED_SMC ".container",
1226 asc->flash_window_size);
1227 sysbus_init_mmio(sbd, &s->mmio_flash_container);
1228
1229 memory_region_init_io(&s->mmio_flash, OBJECT(s),
1230 &aspeed_smc_flash_default_ops, s,
1231 TYPE_ASPEED_SMC ".flash",
1232 asc->flash_window_size);
1233 memory_region_add_subregion(&s->mmio_flash_container, 0x0,
1234 &s->mmio_flash);
1235
1236 /*
1237 * Let's create a sub memory region for each possible peripheral. All
1238 * have a configurable memory segment in the overall flash mapping
1239 * window of the controller but, there is not necessarily a flash
1240 * module behind to handle the memory accesses. This depends on
1241 * the board configuration.
1242 */
1243 for (i = 0; i < asc->cs_num_max; ++i) {
1244 AspeedSMCFlash *fl = &s->flashes[i];
1245
1246 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s),
1247 errp)) {
1248 return;
1249 }
1250 if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) {
1251 return;
1252 }
1253 if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) {
1254 return;
1255 }
1256
1257 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
1258 offset += asc->segments[i].size;
1259 }
1260
1261 /* DMA support */
1262 if (aspeed_smc_has_dma(asc)) {
1263 aspeed_smc_dma_setup(s, errp);
1264 }
1265
1266 /* WDT2 support */
1267 if (aspeed_smc_has_wdt_control(asc)) {
1268 aspeed_smc_wdt_setup(s, errp);
1269 }
1270 }
1271
1272 static const VMStateDescription vmstate_aspeed_smc = {
1273 .name = "aspeed.smc",
1274 .version_id = 2,
1275 .minimum_version_id = 2,
1276 .fields = (VMStateField[]) {
1277 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
1278 VMSTATE_UINT8(snoop_index, AspeedSMCState),
1279 VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
1280 VMSTATE_END_OF_LIST()
1281 }
1282 };
1283
1284 static Property aspeed_smc_properties[] = {
1285 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1286 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
1287 TYPE_MEMORY_REGION, MemoryRegion *),
1288 DEFINE_PROP_LINK("wdt2", AspeedSMCState, wdt2_mr,
1289 TYPE_MEMORY_REGION, MemoryRegion *),
1290 DEFINE_PROP_END_OF_LIST(),
1291 };
1292
aspeed_smc_class_init(ObjectClass * klass,void * data)1293 static void aspeed_smc_class_init(ObjectClass *klass, void *data)
1294 {
1295 DeviceClass *dc = DEVICE_CLASS(klass);
1296
1297 dc->realize = aspeed_smc_realize;
1298 dc->reset = aspeed_smc_reset;
1299 device_class_set_props(dc, aspeed_smc_properties);
1300 dc->vmsd = &vmstate_aspeed_smc;
1301 }
1302
1303 static const TypeInfo aspeed_smc_info = {
1304 .name = TYPE_ASPEED_SMC,
1305 .parent = TYPE_SYS_BUS_DEVICE,
1306 .instance_init = aspeed_smc_instance_init,
1307 .instance_size = sizeof(AspeedSMCState),
1308 .class_size = sizeof(AspeedSMCClass),
1309 .class_init = aspeed_smc_class_init,
1310 .abstract = true,
1311 };
1312
aspeed_smc_flash_realize(DeviceState * dev,Error ** errp)1313 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
1314 {
1315 AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
1316 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
1317
1318 if (!s->controller) {
1319 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set");
1320 return;
1321 }
1322
1323 s->asc = ASPEED_SMC_GET_CLASS(s->controller);
1324
1325 /*
1326 * Use the default segment value to size the memory region. This
1327 * can be changed by FW at runtime.
1328 */
1329 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
1330 s, name, s->asc->segments[s->cs].size);
1331 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
1332 }
1333
1334 static Property aspeed_smc_flash_properties[] = {
1335 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1336 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC,
1337 AspeedSMCState *),
1338 DEFINE_PROP_END_OF_LIST(),
1339 };
1340
aspeed_smc_flash_class_init(ObjectClass * klass,void * data)1341 static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data)
1342 {
1343 DeviceClass *dc = DEVICE_CLASS(klass);
1344
1345 dc->desc = "Aspeed SMC Flash device region";
1346 dc->realize = aspeed_smc_flash_realize;
1347 device_class_set_props(dc, aspeed_smc_flash_properties);
1348 }
1349
1350 static const TypeInfo aspeed_smc_flash_info = {
1351 .name = TYPE_ASPEED_SMC_FLASH,
1352 .parent = TYPE_SYS_BUS_DEVICE,
1353 .instance_size = sizeof(AspeedSMCFlash),
1354 .class_init = aspeed_smc_flash_class_init,
1355 };
1356
1357 /*
1358 * The Segment Registers of the AST2400 and AST2500 have a 8MB
1359 * unit. The address range of a flash SPI peripheral is encoded with
1360 * absolute addresses which should be part of the overall controller
1361 * window.
1362 */
aspeed_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)1363 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
1364 const AspeedSegments *seg)
1365 {
1366 uint32_t reg = 0;
1367 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
1368 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
1369 return reg;
1370 }
1371
aspeed_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)1372 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
1373 uint32_t reg, AspeedSegments *seg)
1374 {
1375 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
1376 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
1377 }
1378
1379 static const AspeedSegments aspeed_2400_smc_segments[] = {
1380 { 0x10000000, 32 * MiB },
1381 };
1382
aspeed_2400_smc_class_init(ObjectClass * klass,void * data)1383 static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data)
1384 {
1385 DeviceClass *dc = DEVICE_CLASS(klass);
1386 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1387
1388 dc->desc = "Aspeed 2400 SMC Controller";
1389 asc->r_conf = R_CONF;
1390 asc->r_ce_ctrl = R_CE_CTRL;
1391 asc->r_ctrl0 = R_CTRL0;
1392 asc->r_timings = R_TIMINGS;
1393 asc->nregs_timings = 1;
1394 asc->conf_enable_w0 = CONF_ENABLE_W0;
1395 asc->cs_num_max = 1;
1396 asc->segments = aspeed_2400_smc_segments;
1397 asc->flash_window_base = 0x10000000;
1398 asc->flash_window_size = 0x6000000;
1399 asc->features = 0x0;
1400 asc->nregs = ASPEED_SMC_R_SMC_MAX;
1401 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1402 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1403 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1404 }
1405
1406 static const TypeInfo aspeed_2400_smc_info = {
1407 .name = "aspeed.smc-ast2400",
1408 .parent = TYPE_ASPEED_SMC,
1409 .class_init = aspeed_2400_smc_class_init,
1410 };
1411
1412 static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = {
1413 /*
1414 * CE0 and CE1 types are HW strapped in SCU70. Do it here to
1415 * simplify the model.
1416 */
1417 [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0,
1418 };
1419
1420 static const AspeedSegments aspeed_2400_fmc_segments[] = {
1421 { 0x20000000, 64 * MiB }, /* start address is readonly */
1422 { 0x24000000, 32 * MiB },
1423 { 0x26000000, 32 * MiB },
1424 { 0x28000000, 32 * MiB },
1425 { 0x2A000000, 32 * MiB }
1426 };
1427
aspeed_2400_fmc_class_init(ObjectClass * klass,void * data)1428 static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
1429 {
1430 DeviceClass *dc = DEVICE_CLASS(klass);
1431 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1432
1433 dc->desc = "Aspeed 2400 FMC Controller";
1434 asc->r_conf = R_CONF;
1435 asc->r_ce_ctrl = R_CE_CTRL;
1436 asc->r_ctrl0 = R_CTRL0;
1437 asc->r_timings = R_TIMINGS;
1438 asc->nregs_timings = 1;
1439 asc->conf_enable_w0 = CONF_ENABLE_W0;
1440 asc->cs_num_max = 5;
1441 asc->segments = aspeed_2400_fmc_segments;
1442 asc->segment_addr_mask = 0xffff0000;
1443 asc->resets = aspeed_2400_fmc_resets;
1444 asc->flash_window_base = 0x20000000;
1445 asc->flash_window_size = 0x10000000;
1446 asc->features = ASPEED_SMC_FEATURE_DMA;
1447 asc->dma_flash_mask = 0x0FFFFFFC;
1448 asc->dma_dram_mask = 0x1FFFFFFC;
1449 asc->nregs = ASPEED_SMC_R_MAX;
1450 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1451 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1452 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1453 }
1454
1455 static const TypeInfo aspeed_2400_fmc_info = {
1456 .name = "aspeed.fmc-ast2400",
1457 .parent = TYPE_ASPEED_SMC,
1458 .class_init = aspeed_2400_fmc_class_init,
1459 };
1460
1461 static const AspeedSegments aspeed_2400_spi1_segments[] = {
1462 { 0x30000000, 64 * MiB },
1463 };
1464
aspeed_2400_spi1_addr_width(const AspeedSMCState * s)1465 static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s)
1466 {
1467 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3;
1468 }
1469
aspeed_2400_spi1_class_init(ObjectClass * klass,void * data)1470 static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data)
1471 {
1472 DeviceClass *dc = DEVICE_CLASS(klass);
1473 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1474
1475 dc->desc = "Aspeed 2400 SPI1 Controller";
1476 asc->r_conf = R_SPI_CONF;
1477 asc->r_ce_ctrl = 0xff;
1478 asc->r_ctrl0 = R_SPI_CTRL0;
1479 asc->r_timings = R_SPI_TIMINGS;
1480 asc->nregs_timings = 1;
1481 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0;
1482 asc->cs_num_max = 1;
1483 asc->segments = aspeed_2400_spi1_segments;
1484 asc->flash_window_base = 0x30000000;
1485 asc->flash_window_size = 0x10000000;
1486 asc->features = 0x0;
1487 asc->nregs = ASPEED_SMC_R_SPI_MAX;
1488 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1489 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1490 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1491 asc->addr_width = aspeed_2400_spi1_addr_width;
1492 }
1493
1494 static const TypeInfo aspeed_2400_spi1_info = {
1495 .name = "aspeed.spi1-ast2400",
1496 .parent = TYPE_ASPEED_SMC,
1497 .class_init = aspeed_2400_spi1_class_init,
1498 };
1499
1500 static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = {
1501 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1502 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1503 };
1504
1505 static const AspeedSegments aspeed_2500_fmc_segments[] = {
1506 { 0x20000000, 128 * MiB }, /* start address is readonly */
1507 { 0x28000000, 32 * MiB },
1508 { 0x2A000000, 32 * MiB },
1509 };
1510
aspeed_2500_fmc_class_init(ObjectClass * klass,void * data)1511 static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
1512 {
1513 DeviceClass *dc = DEVICE_CLASS(klass);
1514 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1515
1516 dc->desc = "Aspeed 2600 FMC Controller";
1517 asc->r_conf = R_CONF;
1518 asc->r_ce_ctrl = R_CE_CTRL;
1519 asc->r_ctrl0 = R_CTRL0;
1520 asc->r_timings = R_TIMINGS;
1521 asc->nregs_timings = 1;
1522 asc->conf_enable_w0 = CONF_ENABLE_W0;
1523 asc->cs_num_max = 3;
1524 asc->segments = aspeed_2500_fmc_segments;
1525 asc->segment_addr_mask = 0xffff0000;
1526 asc->resets = aspeed_2500_fmc_resets;
1527 asc->flash_window_base = 0x20000000;
1528 asc->flash_window_size = 0x10000000;
1529 asc->features = ASPEED_SMC_FEATURE_DMA;
1530 asc->dma_flash_mask = 0x0FFFFFFC;
1531 asc->dma_dram_mask = 0x3FFFFFFC;
1532 asc->nregs = ASPEED_SMC_R_MAX;
1533 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1534 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1535 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1536 }
1537
1538 static const TypeInfo aspeed_2500_fmc_info = {
1539 .name = "aspeed.fmc-ast2500",
1540 .parent = TYPE_ASPEED_SMC,
1541 .class_init = aspeed_2500_fmc_class_init,
1542 };
1543
1544 static const AspeedSegments aspeed_2500_spi1_segments[] = {
1545 { 0x30000000, 32 * MiB }, /* start address is readonly */
1546 { 0x32000000, 96 * MiB }, /* end address is readonly */
1547 };
1548
aspeed_2500_spi1_class_init(ObjectClass * klass,void * data)1549 static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
1550 {
1551 DeviceClass *dc = DEVICE_CLASS(klass);
1552 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1553
1554 dc->desc = "Aspeed 2600 SPI1 Controller";
1555 asc->r_conf = R_CONF;
1556 asc->r_ce_ctrl = R_CE_CTRL;
1557 asc->r_ctrl0 = R_CTRL0;
1558 asc->r_timings = R_TIMINGS;
1559 asc->nregs_timings = 1;
1560 asc->conf_enable_w0 = CONF_ENABLE_W0;
1561 asc->cs_num_max = 2;
1562 asc->segments = aspeed_2500_spi1_segments;
1563 asc->segment_addr_mask = 0xffff0000;
1564 asc->flash_window_base = 0x30000000;
1565 asc->flash_window_size = 0x8000000;
1566 asc->features = 0x0;
1567 asc->nregs = ASPEED_SMC_R_MAX;
1568 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1569 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1570 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1571 }
1572
1573 static const TypeInfo aspeed_2500_spi1_info = {
1574 .name = "aspeed.spi1-ast2500",
1575 .parent = TYPE_ASPEED_SMC,
1576 .class_init = aspeed_2500_spi1_class_init,
1577 };
1578
1579 static const AspeedSegments aspeed_2500_spi2_segments[] = {
1580 { 0x38000000, 32 * MiB }, /* start address is readonly */
1581 { 0x3A000000, 96 * MiB }, /* end address is readonly */
1582 };
1583
aspeed_2500_spi2_class_init(ObjectClass * klass,void * data)1584 static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
1585 {
1586 DeviceClass *dc = DEVICE_CLASS(klass);
1587 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1588
1589 dc->desc = "Aspeed 2600 SPI2 Controller";
1590 asc->r_conf = R_CONF;
1591 asc->r_ce_ctrl = R_CE_CTRL;
1592 asc->r_ctrl0 = R_CTRL0;
1593 asc->r_timings = R_TIMINGS;
1594 asc->nregs_timings = 1;
1595 asc->conf_enable_w0 = CONF_ENABLE_W0;
1596 asc->cs_num_max = 2;
1597 asc->segments = aspeed_2500_spi2_segments;
1598 asc->segment_addr_mask = 0xffff0000;
1599 asc->flash_window_base = 0x38000000;
1600 asc->flash_window_size = 0x8000000;
1601 asc->features = 0x0;
1602 asc->nregs = ASPEED_SMC_R_MAX;
1603 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1604 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1605 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1606 }
1607
1608 static const TypeInfo aspeed_2500_spi2_info = {
1609 .name = "aspeed.spi2-ast2500",
1610 .parent = TYPE_ASPEED_SMC,
1611 .class_init = aspeed_2500_spi2_class_init,
1612 };
1613
1614 /*
1615 * The Segment Registers of the AST2600 have a 1MB unit. The address
1616 * range of a flash SPI peripheral is encoded with offsets in the overall
1617 * controller window. The previous SoC AST2400 and AST2500 used
1618 * absolute addresses. Only bits [27:20] are relevant and the end
1619 * address is an upper bound limit.
1620 */
1621 #define AST2600_SEG_ADDR_MASK 0x0ff00000
1622
aspeed_2600_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)1623 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
1624 const AspeedSegments *seg)
1625 {
1626 uint32_t reg = 0;
1627
1628 /* Disabled segments have a nil register */
1629 if (!seg->size) {
1630 return 0;
1631 }
1632
1633 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */
1634 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */
1635 return reg;
1636 }
1637
aspeed_2600_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)1638 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
1639 uint32_t reg, AspeedSegments *seg)
1640 {
1641 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
1642 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
1643 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1644
1645 if (reg) {
1646 seg->addr = asc->flash_window_base + start_offset;
1647 seg->size = end_offset + MiB - start_offset;
1648 } else {
1649 seg->addr = asc->flash_window_base;
1650 seg->size = 0;
1651 }
1652 }
1653
1654 static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = {
1655 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1656 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 |
1657 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2),
1658 };
1659
1660 static const AspeedSegments aspeed_2600_fmc_segments[] = {
1661 { 0x0, 128 * MiB }, /* start address is readonly */
1662 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1663 { 0x0, 0 }, /* disabled */
1664 };
1665
aspeed_2600_fmc_class_init(ObjectClass * klass,void * data)1666 static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
1667 {
1668 DeviceClass *dc = DEVICE_CLASS(klass);
1669 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1670
1671 dc->desc = "Aspeed 2600 FMC Controller";
1672 asc->r_conf = R_CONF;
1673 asc->r_ce_ctrl = R_CE_CTRL;
1674 asc->r_ctrl0 = R_CTRL0;
1675 asc->r_timings = R_TIMINGS;
1676 asc->nregs_timings = 1;
1677 asc->conf_enable_w0 = CONF_ENABLE_W0;
1678 asc->cs_num_max = 3;
1679 asc->segments = aspeed_2600_fmc_segments;
1680 asc->segment_addr_mask = 0x0ff00ff0;
1681 asc->resets = aspeed_2600_fmc_resets;
1682 asc->flash_window_base = 0x20000000;
1683 asc->flash_window_size = 0x10000000;
1684 asc->features = ASPEED_SMC_FEATURE_DMA |
1685 ASPEED_SMC_FEATURE_WDT_CONTROL;
1686 asc->dma_flash_mask = 0x0FFFFFFC;
1687 asc->dma_dram_mask = 0x3FFFFFFC;
1688 asc->nregs = ASPEED_SMC_R_MAX;
1689 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1690 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1691 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1692 }
1693
1694 static const TypeInfo aspeed_2600_fmc_info = {
1695 .name = "aspeed.fmc-ast2600",
1696 .parent = TYPE_ASPEED_SMC,
1697 .class_init = aspeed_2600_fmc_class_init,
1698 };
1699
1700 static const AspeedSegments aspeed_2600_spi1_segments[] = {
1701 { 0x0, 128 * MiB }, /* start address is readonly */
1702 { 0x0, 0 }, /* disabled */
1703 };
1704
aspeed_2600_spi1_class_init(ObjectClass * klass,void * data)1705 static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
1706 {
1707 DeviceClass *dc = DEVICE_CLASS(klass);
1708 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1709
1710 dc->desc = "Aspeed 2600 SPI1 Controller";
1711 asc->r_conf = R_CONF;
1712 asc->r_ce_ctrl = R_CE_CTRL;
1713 asc->r_ctrl0 = R_CTRL0;
1714 asc->r_timings = R_TIMINGS;
1715 asc->nregs_timings = 2;
1716 asc->conf_enable_w0 = CONF_ENABLE_W0;
1717 asc->cs_num_max = 2;
1718 asc->segments = aspeed_2600_spi1_segments;
1719 asc->segment_addr_mask = 0x0ff00ff0;
1720 asc->flash_window_base = 0x30000000;
1721 asc->flash_window_size = 0x10000000;
1722 asc->features = ASPEED_SMC_FEATURE_DMA |
1723 ASPEED_SMC_FEATURE_DMA_GRANT;
1724 asc->dma_flash_mask = 0x0FFFFFFC;
1725 asc->dma_dram_mask = 0x3FFFFFFC;
1726 asc->nregs = ASPEED_SMC_R_MAX;
1727 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1728 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1729 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1730 }
1731
1732 static const TypeInfo aspeed_2600_spi1_info = {
1733 .name = "aspeed.spi1-ast2600",
1734 .parent = TYPE_ASPEED_SMC,
1735 .class_init = aspeed_2600_spi1_class_init,
1736 };
1737
1738 static const AspeedSegments aspeed_2600_spi2_segments[] = {
1739 { 0x0, 128 * MiB }, /* start address is readonly */
1740 { 0x0, 0 }, /* disabled */
1741 { 0x0, 0 }, /* disabled */
1742 };
1743
aspeed_2600_spi2_class_init(ObjectClass * klass,void * data)1744 static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
1745 {
1746 DeviceClass *dc = DEVICE_CLASS(klass);
1747 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1748
1749 dc->desc = "Aspeed 2600 SPI2 Controller";
1750 asc->r_conf = R_CONF;
1751 asc->r_ce_ctrl = R_CE_CTRL;
1752 asc->r_ctrl0 = R_CTRL0;
1753 asc->r_timings = R_TIMINGS;
1754 asc->nregs_timings = 3;
1755 asc->conf_enable_w0 = CONF_ENABLE_W0;
1756 asc->cs_num_max = 3;
1757 asc->segments = aspeed_2600_spi2_segments;
1758 asc->segment_addr_mask = 0x0ff00ff0;
1759 asc->flash_window_base = 0x50000000;
1760 asc->flash_window_size = 0x10000000;
1761 asc->features = ASPEED_SMC_FEATURE_DMA |
1762 ASPEED_SMC_FEATURE_DMA_GRANT;
1763 asc->dma_flash_mask = 0x0FFFFFFC;
1764 asc->dma_dram_mask = 0x3FFFFFFC;
1765 asc->nregs = ASPEED_SMC_R_MAX;
1766 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1767 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1768 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1769 }
1770
1771 static const TypeInfo aspeed_2600_spi2_info = {
1772 .name = "aspeed.spi2-ast2600",
1773 .parent = TYPE_ASPEED_SMC,
1774 .class_init = aspeed_2600_spi2_class_init,
1775 };
1776
1777 /*
1778 * The FMC Segment Registers of the AST1030 have a 512KB unit.
1779 * Only bits [27:19] are used for decoding.
1780 */
1781 #define AST1030_SEG_ADDR_MASK 0x0ff80000
1782
aspeed_1030_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)1783 static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s,
1784 const AspeedSegments *seg)
1785 {
1786 uint32_t reg = 0;
1787
1788 /* Disabled segments have a nil register */
1789 if (!seg->size) {
1790 return 0;
1791 }
1792
1793 reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */
1794 reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */
1795 return reg;
1796 }
1797
aspeed_1030_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)1798 static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s,
1799 uint32_t reg, AspeedSegments *seg)
1800 {
1801 uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK;
1802 uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK;
1803 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1804
1805 if (reg) {
1806 seg->addr = asc->flash_window_base + start_offset;
1807 seg->size = end_offset + (512 * KiB) - start_offset;
1808 } else {
1809 seg->addr = asc->flash_window_base;
1810 seg->size = 0;
1811 }
1812 }
1813
1814 static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = {
1815 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1816 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1817 };
1818
1819 static const AspeedSegments aspeed_1030_fmc_segments[] = {
1820 { 0x0, 128 * MiB }, /* start address is readonly */
1821 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1822 { 0x0, 0 }, /* disabled */
1823 };
1824
aspeed_1030_fmc_class_init(ObjectClass * klass,void * data)1825 static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data)
1826 {
1827 DeviceClass *dc = DEVICE_CLASS(klass);
1828 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1829
1830 dc->desc = "Aspeed 1030 FMC Controller";
1831 asc->r_conf = R_CONF;
1832 asc->r_ce_ctrl = R_CE_CTRL;
1833 asc->r_ctrl0 = R_CTRL0;
1834 asc->r_timings = R_TIMINGS;
1835 asc->nregs_timings = 2;
1836 asc->conf_enable_w0 = CONF_ENABLE_W0;
1837 asc->cs_num_max = 2;
1838 asc->segments = aspeed_1030_fmc_segments;
1839 asc->segment_addr_mask = 0x0ff80ff8;
1840 asc->resets = aspeed_1030_fmc_resets;
1841 asc->flash_window_base = 0x80000000;
1842 asc->flash_window_size = 0x10000000;
1843 asc->features = ASPEED_SMC_FEATURE_DMA;
1844 asc->dma_flash_mask = 0x0FFFFFFC;
1845 asc->dma_dram_mask = 0x000BFFFC;
1846 asc->nregs = ASPEED_SMC_R_MAX;
1847 asc->segment_to_reg = aspeed_1030_smc_segment_to_reg;
1848 asc->reg_to_segment = aspeed_1030_smc_reg_to_segment;
1849 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1850 }
1851
1852 static const TypeInfo aspeed_1030_fmc_info = {
1853 .name = "aspeed.fmc-ast1030",
1854 .parent = TYPE_ASPEED_SMC,
1855 .class_init = aspeed_1030_fmc_class_init,
1856 };
1857
1858 static const AspeedSegments aspeed_1030_spi1_segments[] = {
1859 { 0x0, 128 * MiB }, /* start address is readonly */
1860 { 0x0, 0 }, /* disabled */
1861 };
1862
aspeed_1030_spi1_class_init(ObjectClass * klass,void * data)1863 static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data)
1864 {
1865 DeviceClass *dc = DEVICE_CLASS(klass);
1866 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1867
1868 dc->desc = "Aspeed 1030 SPI1 Controller";
1869 asc->r_conf = R_CONF;
1870 asc->r_ce_ctrl = R_CE_CTRL;
1871 asc->r_ctrl0 = R_CTRL0;
1872 asc->r_timings = R_TIMINGS;
1873 asc->nregs_timings = 2;
1874 asc->conf_enable_w0 = CONF_ENABLE_W0;
1875 asc->cs_num_max = 2;
1876 asc->segments = aspeed_1030_spi1_segments;
1877 asc->segment_addr_mask = 0x0ff00ff0;
1878 asc->flash_window_base = 0x90000000;
1879 asc->flash_window_size = 0x10000000;
1880 asc->features = ASPEED_SMC_FEATURE_DMA;
1881 asc->dma_flash_mask = 0x0FFFFFFC;
1882 asc->dma_dram_mask = 0x000BFFFC;
1883 asc->nregs = ASPEED_SMC_R_MAX;
1884 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1885 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1886 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1887 }
1888
1889 static const TypeInfo aspeed_1030_spi1_info = {
1890 .name = "aspeed.spi1-ast1030",
1891 .parent = TYPE_ASPEED_SMC,
1892 .class_init = aspeed_1030_spi1_class_init,
1893 };
1894 static const AspeedSegments aspeed_1030_spi2_segments[] = {
1895 { 0x0, 128 * MiB }, /* start address is readonly */
1896 { 0x0, 0 }, /* disabled */
1897 };
1898
aspeed_1030_spi2_class_init(ObjectClass * klass,void * data)1899 static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data)
1900 {
1901 DeviceClass *dc = DEVICE_CLASS(klass);
1902 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1903
1904 dc->desc = "Aspeed 1030 SPI2 Controller";
1905 asc->r_conf = R_CONF;
1906 asc->r_ce_ctrl = R_CE_CTRL;
1907 asc->r_ctrl0 = R_CTRL0;
1908 asc->r_timings = R_TIMINGS;
1909 asc->nregs_timings = 2;
1910 asc->conf_enable_w0 = CONF_ENABLE_W0;
1911 asc->cs_num_max = 2;
1912 asc->segments = aspeed_1030_spi2_segments;
1913 asc->segment_addr_mask = 0x0ff00ff0;
1914 asc->flash_window_base = 0xb0000000;
1915 asc->flash_window_size = 0x10000000;
1916 asc->features = ASPEED_SMC_FEATURE_DMA;
1917 asc->dma_flash_mask = 0x0FFFFFFC;
1918 asc->dma_dram_mask = 0x000BFFFC;
1919 asc->nregs = ASPEED_SMC_R_MAX;
1920 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1921 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1922 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1923 }
1924
1925 static const TypeInfo aspeed_1030_spi2_info = {
1926 .name = "aspeed.spi2-ast1030",
1927 .parent = TYPE_ASPEED_SMC,
1928 .class_init = aspeed_1030_spi2_class_init,
1929 };
1930
aspeed_smc_register_types(void)1931 static void aspeed_smc_register_types(void)
1932 {
1933 type_register_static(&aspeed_smc_flash_info);
1934 type_register_static(&aspeed_smc_info);
1935 type_register_static(&aspeed_2400_smc_info);
1936 type_register_static(&aspeed_2400_fmc_info);
1937 type_register_static(&aspeed_2400_spi1_info);
1938 type_register_static(&aspeed_2500_fmc_info);
1939 type_register_static(&aspeed_2500_spi1_info);
1940 type_register_static(&aspeed_2500_spi2_info);
1941 type_register_static(&aspeed_2600_fmc_info);
1942 type_register_static(&aspeed_2600_spi1_info);
1943 type_register_static(&aspeed_2600_spi2_info);
1944 type_register_static(&aspeed_1030_fmc_info);
1945 type_register_static(&aspeed_1030_spi1_info);
1946 type_register_static(&aspeed_1030_spi2_info);
1947 }
1948
1949 type_init(aspeed_smc_register_types)
1950