1*bae2d725SRick Chen/dts-v1/; 2*bae2d725SRick Chen 3*bae2d725SRick Chen/ { 4*bae2d725SRick Chen #address-cells = <2>; 5*bae2d725SRick Chen #size-cells = <2>; 6*bae2d725SRick Chen compatible = "andestech,ax25"; 7*bae2d725SRick Chen model = "andestech,ax25"; 8*bae2d725SRick Chen 9*bae2d725SRick Chen aliases { 10*bae2d725SRick Chen uart0 = &serial0; 11*bae2d725SRick Chen spi0 = &spi; 12*bae2d725SRick Chen }; 13*bae2d725SRick Chen 14*bae2d725SRick Chen chosen { 15*bae2d725SRick Chen bootargs = "console=ttyS0,38400n8 debug loglevel=7"; 16*bae2d725SRick Chen stdout-path = "uart0:38400n8"; 17*bae2d725SRick Chen }; 18*bae2d725SRick Chen 19*bae2d725SRick Chen cpus { 20*bae2d725SRick Chen #address-cells = <1>; 21*bae2d725SRick Chen #size-cells = <0>; 22*bae2d725SRick Chen timebase-frequency = <60000000>; 23*bae2d725SRick Chen CPU0: cpu@0 { 24*bae2d725SRick Chen device_type = "cpu"; 25*bae2d725SRick Chen reg = <0>; 26*bae2d725SRick Chen status = "okay"; 27*bae2d725SRick Chen compatible = "riscv"; 28*bae2d725SRick Chen riscv,isa = "rv64imafdc"; 29*bae2d725SRick Chen mmu-type = "riscv,sv39"; 30*bae2d725SRick Chen clock-frequency = <60000000>; 31*bae2d725SRick Chen d-cache-size = <0x8000>; 32*bae2d725SRick Chen d-cache-line-size = <32>; 33*bae2d725SRick Chen CPU0_intc: interrupt-controller { 34*bae2d725SRick Chen #interrupt-cells = <1>; 35*bae2d725SRick Chen interrupt-controller; 36*bae2d725SRick Chen compatible = "riscv,cpu-intc"; 37*bae2d725SRick Chen }; 38*bae2d725SRick Chen }; 39*bae2d725SRick Chen }; 40*bae2d725SRick Chen 41*bae2d725SRick Chen memory@0 { 42*bae2d725SRick Chen device_type = "memory"; 43*bae2d725SRick Chen reg = <0x0 0x00000000 0x0 0x40000000>; 44*bae2d725SRick Chen }; 45*bae2d725SRick Chen 46*bae2d725SRick Chen soc { 47*bae2d725SRick Chen #address-cells = <2>; 48*bae2d725SRick Chen #size-cells = <2>; 49*bae2d725SRick Chen compatible = "andestech,riscv-ae350-soc"; 50*bae2d725SRick Chen ranges; 51*bae2d725SRick Chen 52*bae2d725SRick Chen plic0: interrupt-controller@e4000000 { 53*bae2d725SRick Chen compatible = "riscv,plic0"; 54*bae2d725SRick Chen #address-cells = <2>; 55*bae2d725SRick Chen #interrupt-cells = <2>; 56*bae2d725SRick Chen interrupt-controller; 57*bae2d725SRick Chen reg = <0x0 0xe4000000 0x0 0x2000000>; 58*bae2d725SRick Chen riscv,ndev=<71>; 59*bae2d725SRick Chen interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; 60*bae2d725SRick Chen }; 61*bae2d725SRick Chen 62*bae2d725SRick Chen plic1: interrupt-controller@e6400000 { 63*bae2d725SRick Chen compatible = "riscv,plic1"; 64*bae2d725SRick Chen #address-cells = <2>; 65*bae2d725SRick Chen #interrupt-cells = <2>; 66*bae2d725SRick Chen interrupt-controller; 67*bae2d725SRick Chen reg = <0x0 0xe6400000 0x0 0x400000>; 68*bae2d725SRick Chen riscv,ndev=<1>; 69*bae2d725SRick Chen interrupts-extended = <&CPU0_intc 3>; 70*bae2d725SRick Chen }; 71*bae2d725SRick Chen 72*bae2d725SRick Chen plmt0@e6000000 { 73*bae2d725SRick Chen compatible = "riscv,plmt0"; 74*bae2d725SRick Chen interrupts-extended = <&CPU0_intc 7>; 75*bae2d725SRick Chen reg = <0x0 0xe6000000 0x0 0x100000>; 76*bae2d725SRick Chen }; 77*bae2d725SRick Chen }; 78*bae2d725SRick Chen 79*bae2d725SRick Chen spiclk: virt_100mhz { 80*bae2d725SRick Chen #clock-cells = <0>; 81*bae2d725SRick Chen compatible = "fixed-clock"; 82*bae2d725SRick Chen clock-frequency = <100000000>; 83*bae2d725SRick Chen }; 84*bae2d725SRick Chen 85*bae2d725SRick Chen timer0: timer@f0400000 { 86*bae2d725SRick Chen compatible = "andestech,atcpit100"; 87*bae2d725SRick Chen reg = <0x0 0xf0400000 0x0 0x1000>; 88*bae2d725SRick Chen clock-frequency = <60000000>; 89*bae2d725SRick Chen interrupts = <3 4>; 90*bae2d725SRick Chen interrupt-parent = <&plic0>; 91*bae2d725SRick Chen }; 92*bae2d725SRick Chen 93*bae2d725SRick Chen serial0: serial@f0300000 { 94*bae2d725SRick Chen compatible = "andestech,uart16550", "ns16550a"; 95*bae2d725SRick Chen reg = <0x0 0xf0300000 0x0 0x1000>; 96*bae2d725SRick Chen interrupts = <9 4>; 97*bae2d725SRick Chen clock-frequency = <19660800>; 98*bae2d725SRick Chen reg-shift = <2>; 99*bae2d725SRick Chen reg-offset = <32>; 100*bae2d725SRick Chen no-loopback-test = <1>; 101*bae2d725SRick Chen interrupt-parent = <&plic0>; 102*bae2d725SRick Chen }; 103*bae2d725SRick Chen 104*bae2d725SRick Chen mac0: mac@e0100000 { 105*bae2d725SRick Chen compatible = "andestech,atmac100"; 106*bae2d725SRick Chen reg = <0x0 0xe0100000 0x0 0x1000>; 107*bae2d725SRick Chen interrupts = <19 4>; 108*bae2d725SRick Chen interrupt-parent = <&plic0>; 109*bae2d725SRick Chen }; 110*bae2d725SRick Chen 111*bae2d725SRick Chen mmc0: mmc@f0e00000 { 112*bae2d725SRick Chen compatible = "andestech,atfsdc010"; 113*bae2d725SRick Chen max-frequency = <100000000>; 114*bae2d725SRick Chen clock-freq-min-max = <400000 100000000>; 115*bae2d725SRick Chen fifo-depth = <0x10>; 116*bae2d725SRick Chen reg = <0x0 0xf0e00000 0x0 0x1000>; 117*bae2d725SRick Chen interrupts = <18 4>; 118*bae2d725SRick Chen cap-sd-highspeed; 119*bae2d725SRick Chen interrupt-parent = <&plic0>; 120*bae2d725SRick Chen }; 121*bae2d725SRick Chen 122*bae2d725SRick Chen dma0: dma@f0c00000 { 123*bae2d725SRick Chen compatible = "andestech,atcdmac300"; 124*bae2d725SRick Chen reg = <0x0 0xf0c00000 0x0 0x1000>; 125*bae2d725SRick Chen interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; 126*bae2d725SRick Chen dma-channels = <8>; 127*bae2d725SRick Chen interrupt-parent = <&plic0>; 128*bae2d725SRick Chen }; 129*bae2d725SRick Chen 130*bae2d725SRick Chen lcd0: lcd@e0200000 { 131*bae2d725SRick Chen compatible = "andestech,atflcdc100"; 132*bae2d725SRick Chen reg = <0x0 0xe0200000 0x0 0x1000>; 133*bae2d725SRick Chen interrupts = <20 4>; 134*bae2d725SRick Chen interrupt-parent = <&plic0>; 135*bae2d725SRick Chen }; 136*bae2d725SRick Chen 137*bae2d725SRick Chen smc0: smc@e0400000 { 138*bae2d725SRick Chen compatible = "andestech,atfsmc020"; 139*bae2d725SRick Chen reg = <0x0 0xe0400000 0x0 0x1000>; 140*bae2d725SRick Chen }; 141*bae2d725SRick Chen 142*bae2d725SRick Chen snd0: snd@f0d00000 { 143*bae2d725SRick Chen compatible = "andestech,atfac97"; 144*bae2d725SRick Chen reg = <0x0 0xf0d00000 0x0 0x1000>; 145*bae2d725SRick Chen interrupts = <17 4>; 146*bae2d725SRick Chen interrupt-parent = <&plic0>; 147*bae2d725SRick Chen }; 148*bae2d725SRick Chen 149*bae2d725SRick Chen virtio_mmio@fe007000 { 150*bae2d725SRick Chen interrupts = <0x17 0x4>; 151*bae2d725SRick Chen interrupt-parent = <0x2>; 152*bae2d725SRick Chen reg = <0x0 0xfe007000 0x0 0x1000>; 153*bae2d725SRick Chen compatible = "virtio,mmio"; 154*bae2d725SRick Chen }; 155*bae2d725SRick Chen 156*bae2d725SRick Chen virtio_mmio@fe006000 { 157*bae2d725SRick Chen interrupts = <0x16 0x4>; 158*bae2d725SRick Chen interrupt-parent = <0x2>; 159*bae2d725SRick Chen reg = <0x0 0xfe006000 0x0 0x1000>; 160*bae2d725SRick Chen compatible = "virtio,mmio"; 161*bae2d725SRick Chen }; 162*bae2d725SRick Chen 163*bae2d725SRick Chen virtio_mmio@fe005000 { 164*bae2d725SRick Chen interrupts = <0x15 0x4>; 165*bae2d725SRick Chen interrupt-parent = <0x2>; 166*bae2d725SRick Chen reg = <0x0 0xfe005000 0x0 0x1000>; 167*bae2d725SRick Chen compatible = "virtio,mmio"; 168*bae2d725SRick Chen }; 169*bae2d725SRick Chen 170*bae2d725SRick Chen virtio_mmio@fe004000 { 171*bae2d725SRick Chen interrupts = <0x14 0x4>; 172*bae2d725SRick Chen interrupt-parent = <0x2>; 173*bae2d725SRick Chen reg = <0x0 0xfe004000 0x0 0x1000>; 174*bae2d725SRick Chen compatible = "virtio,mmio"; 175*bae2d725SRick Chen }; 176*bae2d725SRick Chen 177*bae2d725SRick Chen virtio_mmio@fe003000 { 178*bae2d725SRick Chen interrupts = <0x13 0x4>; 179*bae2d725SRick Chen interrupt-parent = <0x2>; 180*bae2d725SRick Chen reg = <0x0 0xfe003000 0x0 0x1000>; 181*bae2d725SRick Chen compatible = "virtio,mmio"; 182*bae2d725SRick Chen }; 183*bae2d725SRick Chen 184*bae2d725SRick Chen virtio_mmio@fe002000 { 185*bae2d725SRick Chen interrupts = <0x12 0x4>; 186*bae2d725SRick Chen interrupt-parent = <0x2>; 187*bae2d725SRick Chen reg = <0x0 0xfe002000 0x0 0x1000>; 188*bae2d725SRick Chen compatible = "virtio,mmio"; 189*bae2d725SRick Chen }; 190*bae2d725SRick Chen 191*bae2d725SRick Chen virtio_mmio@fe001000 { 192*bae2d725SRick Chen interrupts = <0x11 0x4>; 193*bae2d725SRick Chen interrupt-parent = <0x2>; 194*bae2d725SRick Chen reg = <0x0 0xfe001000 0x0 0x1000>; 195*bae2d725SRick Chen compatible = "virtio,mmio"; 196*bae2d725SRick Chen }; 197*bae2d725SRick Chen 198*bae2d725SRick Chen virtio_mmio@fe000000 { 199*bae2d725SRick Chen interrupts = <0x10 0x4>; 200*bae2d725SRick Chen interrupt-parent = <0x2>; 201*bae2d725SRick Chen reg = <0x0 0xfe000000 0x0 0x1000>; 202*bae2d725SRick Chen compatible = "virtio,mmio"; 203*bae2d725SRick Chen }; 204*bae2d725SRick Chen 205*bae2d725SRick Chen nor@0,0 { 206*bae2d725SRick Chen compatible = "cfi-flash"; 207*bae2d725SRick Chen reg = <0x0 0x88000000 0x0 0x1000>; 208*bae2d725SRick Chen bank-width = <2>; 209*bae2d725SRick Chen device-width = <1>; 210*bae2d725SRick Chen }; 211*bae2d725SRick Chen 212*bae2d725SRick Chen spi: spi@f0b00000 { 213*bae2d725SRick Chen compatible = "andestech,atcspi200"; 214*bae2d725SRick Chen reg = <0x0 0xf0b00000 0x0 0x1000>; 215*bae2d725SRick Chen #address-cells = <1>; 216*bae2d725SRick Chen #size-cells = <0>; 217*bae2d725SRick Chen num-cs = <1>; 218*bae2d725SRick Chen clocks = <&spiclk>; 219*bae2d725SRick Chen interrupts = <4 4>; 220*bae2d725SRick Chen interrupt-parent = <&plic0>; 221*bae2d725SRick Chen flash@0 { 222*bae2d725SRick Chen compatible = "spi-flash"; 223*bae2d725SRick Chen spi-max-frequency = <50000000>; 224*bae2d725SRick Chen reg = <0>; 225*bae2d725SRick Chen spi-cpol; 226*bae2d725SRick Chen spi-cpha; 227*bae2d725SRick Chen }; 228*bae2d725SRick Chen }; 229*bae2d725SRick Chen}; 230