Lines Matching +full:flash +full:- +full:dma
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
26 #include "hw/block/flash.h"
31 #include "qemu/error-report.h"
37 #include "hw/qdev-properties.h"
80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
137 /* DMA DRAM Side Address High Part (AST2700) */
140 /* DMA Control/Status Register */
153 /* DMA Flash Side Address */
156 /* DMA DRAM Side Address */
159 /* DMA Length Register */
179 * DMA DRAM addresses should be 4 bytes aligned and the valid address
180 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
181 * 0x80000000 - 0xBFFFFFFF (AST2500)
183 * DMA flash addresses should be 4 bytes aligned and the valid address
184 * range is 0x20000000 - 0x2FFFFFFF.
186 * DMA length is from 4 bytes to 32MB (AST2500)
190 * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700)
194 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
196 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
199 /* Flash opcodes. */
220 return !!(asc->features & ASPEED_SMC_FEATURE_DMA); in aspeed_smc_has_dma()
225 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); in aspeed_smc_has_wdt_control()
230 return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH); in aspeed_smc_has_dma64()
244 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_flash_overlap()
249 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); in aspeed_smc_flash_overlap()
251 if (new->addr + new->size > seg.addr && in aspeed_smc_flash_overlap()
252 new->addr < seg.addr + seg.size) { in aspeed_smc_flash_overlap()
254 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " in aspeed_smc_flash_overlap()
255 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_overlap()
256 cs, new->addr, new->addr + new->size, in aspeed_smc_flash_overlap()
268 AspeedSMCFlash *fl = &s->flashes[cs]; in aspeed_smc_flash_set_segment_region()
271 asc->reg_to_segment(s, regval, &seg); in aspeed_smc_flash_set_segment_region()
274 memory_region_set_size(&fl->mmio, seg.size); in aspeed_smc_flash_set_segment_region()
275 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); in aspeed_smc_flash_set_segment_region()
276 memory_region_set_enabled(&fl->mmio, !!seg.size); in aspeed_smc_flash_set_segment_region()
279 if (asc->segment_addr_mask) { in aspeed_smc_flash_set_segment_region()
280 regval &= asc->segment_addr_mask; in aspeed_smc_flash_set_segment_region()
283 s->regs[R_SEG_ADDR0 + cs] = regval; in aspeed_smc_flash_set_segment_region()
292 asc->reg_to_segment(s, new, &seg); in aspeed_smc_flash_set_segment()
296 /* The start address of CS0 is read-only */ in aspeed_smc_flash_set_segment()
297 if (cs == 0 && seg.addr != asc->flash_window_base) { in aspeed_smc_flash_set_segment()
300 seg.addr = asc->flash_window_base; in aspeed_smc_flash_set_segment()
301 new = asc->segment_to_reg(s, &seg); in aspeed_smc_flash_set_segment()
306 * read-only. in aspeed_smc_flash_set_segment()
308 if ((asc->segments == aspeed_2500_spi1_segments || in aspeed_smc_flash_set_segment()
309 asc->segments == aspeed_2500_spi2_segments) && in aspeed_smc_flash_set_segment()
310 cs == asc->cs_num_max && in aspeed_smc_flash_set_segment()
311 seg.addr + seg.size != asc->segments[cs].addr + in aspeed_smc_flash_set_segment()
312 asc->segments[cs].size) { in aspeed_smc_flash_set_segment()
315 seg.size = asc->segments[cs].addr + asc->segments[cs].size - in aspeed_smc_flash_set_segment()
317 new = asc->segment_to_reg(s, &seg); in aspeed_smc_flash_set_segment()
320 /* Keep the segment in the overall flash window */ in aspeed_smc_flash_set_segment()
322 (seg.addr + seg.size <= asc->flash_window_base || in aspeed_smc_flash_set_segment()
323 seg.addr > asc->flash_window_base + asc->flash_window_size)) { in aspeed_smc_flash_set_segment()
325 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
333 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
370 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_mode()
372 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; in aspeed_smc_flash_mode()
377 const AspeedSMCState *s = fl->controller; in aspeed_smc_is_writable()
379 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); in aspeed_smc_is_writable()
384 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_cmd()
385 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; in aspeed_smc_flash_cmd()
407 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_addr_width()
408 AspeedSMCClass *asc = fl->asc; in aspeed_smc_flash_addr_width()
410 if (asc->addr_width) { in aspeed_smc_flash_addr_width()
411 return asc->addr_width(s); in aspeed_smc_flash_addr_width()
413 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3; in aspeed_smc_flash_addr_width()
419 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_do_select()
421 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); in aspeed_smc_flash_do_select()
422 s->unselect = unselect; in aspeed_smc_flash_do_select()
423 qemu_set_irq(s->cs_lines[fl->cs], unselect); in aspeed_smc_flash_do_select()
439 const AspeedSMCState *s = fl->controller; in aspeed_smc_check_segment_addr()
440 AspeedSMCClass *asc = fl->asc; in aspeed_smc_check_segment_addr()
443 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); in aspeed_smc_check_segment_addr()
446 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_check_segment_addr()
447 addr, fl->cs, seg.addr, seg.addr + seg.size); in aspeed_smc_check_segment_addr()
456 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_dummies()
457 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; in aspeed_smc_flash_dummies()
471 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_setup()
475 /* Flash access can not exceed CS segment */ in aspeed_smc_flash_setup()
478 ssi_transfer(s->spi, cmd); in aspeed_smc_flash_setup()
479 while (i--) { in aspeed_smc_flash_setup()
481 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); in aspeed_smc_flash_setup()
487 * be configured to some non-zero value in fast read mode and in aspeed_smc_flash_setup()
493 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_flash_setup()
501 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_read()
508 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
517 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
523 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); in aspeed_smc_flash_read()
526 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, in aspeed_smc_flash_read()
573 return -1; in aspeed_smc_num_dummies()
580 AspeedSMCState *s = fl->controller; in aspeed_smc_do_snoop()
583 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies, in aspeed_smc_do_snoop()
586 if (s->snoop_index == SNOOP_OFF) { in aspeed_smc_do_snoop()
589 } else if (s->snoop_index == SNOOP_START) { in aspeed_smc_do_snoop()
598 s->snoop_index = SNOOP_OFF; in aspeed_smc_do_snoop()
602 s->snoop_dummies = ndummies * 8; in aspeed_smc_do_snoop()
604 } else if (s->snoop_index >= addr_width + 1) { in aspeed_smc_do_snoop()
607 for (; s->snoop_dummies; s->snoop_dummies--) { in aspeed_smc_do_snoop()
608 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_do_snoop()
612 if (!s->snoop_dummies) { in aspeed_smc_do_snoop()
613 s->snoop_index = SNOOP_OFF; in aspeed_smc_do_snoop()
615 s->snoop_index += size; in aspeed_smc_do_snoop()
625 s->snoop_index += size; in aspeed_smc_do_snoop()
633 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_write()
636 trace_aspeed_smc_flash_write(fl->cs, addr, size, data, in aspeed_smc_flash_write()
640 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); in aspeed_smc_flash_write()
651 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
659 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
665 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); in aspeed_smc_flash_write()
681 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_update_ctrl()
686 old_mode = s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; in aspeed_smc_flash_update_ctrl()
695 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && in aspeed_smc_flash_update_ctrl()
705 s->regs[s->r_ctrl0 + fl->cs] = value; in aspeed_smc_flash_update_ctrl()
707 if (unselect != s->unselect) { in aspeed_smc_flash_update_ctrl()
708 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; in aspeed_smc_flash_update_ctrl()
719 if (asc->resets) { in aspeed_smc_reset()
720 memcpy(s->regs, asc->resets, sizeof s->regs); in aspeed_smc_reset()
722 memset(s->regs, 0, sizeof s->regs); in aspeed_smc_reset()
725 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_reset()
726 DeviceState *dev = ssi_get_cs(s->spi, i); in aspeed_smc_reset()
732 BUS(s->spi)->name, i, object_get_typename(o)); in aspeed_smc_reset()
742 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
743 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; in aspeed_smc_reset()
744 qemu_set_irq(s->cs_lines[i], true); in aspeed_smc_reset()
747 s->unselect = true; in aspeed_smc_reset()
750 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
752 asc->segment_to_reg(s, &asc->segments[i])); in aspeed_smc_reset()
755 s->snoop_index = SNOOP_OFF; in aspeed_smc_reset()
756 s->snoop_dummies = 0; in aspeed_smc_reset()
768 address_space_stl_le(&s->wdt2_as, offset, value, MEMTXATTRS_UNSPECIFIED, in aspeed_smc_wdt2_write()
781 value = address_space_ldl_le(&s->wdt2_as, offset, MEMTXATTRS_UNSPECIFIED, in aspeed_smc_wdt2_read()
785 return -1; in aspeed_smc_wdt2_read()
795 if (value == -1) { in aspeed_smc_wdt2_enable()
814 if (addr == s->r_conf || in aspeed_smc_read()
815 (addr >= s->r_timings && in aspeed_smc_read()
816 addr < s->r_timings + asc->nregs_timings) || in aspeed_smc_read()
817 addr == s->r_ce_ctrl || in aspeed_smc_read()
829 addr < R_SEG_ADDR0 + asc->cs_num_max) || in aspeed_smc_read()
830 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { in aspeed_smc_read()
832 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); in aspeed_smc_read()
834 return s->regs[addr]; in aspeed_smc_read()
842 return -1; in aspeed_smc_read()
866 * Register are set using bit[11:4] of the DMA Control Register.
871 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; in aspeed_smc_dma_calibration()
873 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; in aspeed_smc_dma_calibration()
875 uint32_t hclk_shift = (hclk_div - 1) << 2; in aspeed_smc_dma_calibration()
880 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays in aspeed_smc_dma_calibration()
883 s->regs[s->r_timings] &= ~(0xf << hclk_shift); in aspeed_smc_dma_calibration()
884 s->regs[s->r_timings] |= delay << hclk_shift; in aspeed_smc_dma_calibration()
888 * TODO: compute the CS from the DMA address and the segment in aspeed_smc_dma_calibration()
894 s->regs[s->r_ctrl0 + cs] &= in aspeed_smc_dma_calibration()
896 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); in aspeed_smc_dma_calibration()
900 * Emulate read errors in the DMA Checksum Register for high
908 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; in aspeed_smc_inject_read_failure()
910 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; in aspeed_smc_inject_read_failure()
913 * Typical values of a palmetto-bmc machine. in aspeed_smc_inject_read_failure()
931 return s->regs[R_DMA_DRAM_ADDR] | in aspeed_smc_dma_dram_addr()
932 ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32); in aspeed_smc_dma_dram_addr()
939 return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4); in aspeed_smc_dma_len()
952 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { in aspeed_smc_dma_checksum()
953 aspeed_smc_error("invalid direction for DMA checksum"); in aspeed_smc_dma_checksum()
957 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { in aspeed_smc_dma_checksum()
964 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_checksum()
967 aspeed_smc_error("Flash read failed @%08x", in aspeed_smc_dma_checksum()
968 s->regs[R_DMA_FLASH_ADDR]); in aspeed_smc_dma_checksum()
971 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); in aspeed_smc_dma_checksum()
974 * When the DMA is on-going, the DMA registers are updated in aspeed_smc_dma_checksum()
977 s->regs[R_DMA_CHECKSUM] += data; in aspeed_smc_dma_checksum()
978 s->regs[R_DMA_FLASH_ADDR] += 4; in aspeed_smc_dma_checksum()
979 dma_len -= 4; in aspeed_smc_dma_checksum()
980 s->regs[R_DMA_LEN] = dma_len; in aspeed_smc_dma_checksum()
983 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { in aspeed_smc_dma_checksum()
984 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; in aspeed_smc_dma_checksum()
1002 dma_dram_offset = dma_dram_addr - s->dram_base; in aspeed_smc_dma_rw()
1007 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? in aspeed_smc_dma_rw()
1009 s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_rw()
1013 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { in aspeed_smc_dma_rw()
1014 data = address_space_ldl_le(&s->dram_as, dma_dram_offset, in aspeed_smc_dma_rw()
1022 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_rw()
1025 aspeed_smc_error("Flash write failed @%08x", in aspeed_smc_dma_rw()
1026 s->regs[R_DMA_FLASH_ADDR]); in aspeed_smc_dma_rw()
1030 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_rw()
1033 aspeed_smc_error("Flash read failed @%08x", in aspeed_smc_dma_rw()
1034 s->regs[R_DMA_FLASH_ADDR]); in aspeed_smc_dma_rw()
1038 address_space_stl_le(&s->dram_as, dma_dram_offset, in aspeed_smc_dma_rw()
1048 * When the DMA is on-going, the DMA registers are updated in aspeed_smc_dma_rw()
1054 s->regs[R_DMA_DRAM_ADDR_HIGH] = dma_dram_addr >> 32; in aspeed_smc_dma_rw()
1055 s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff; in aspeed_smc_dma_rw()
1056 s->regs[R_DMA_FLASH_ADDR] += 4; in aspeed_smc_dma_rw()
1057 dma_len -= 4; in aspeed_smc_dma_rw()
1058 s->regs[R_DMA_LEN] = dma_len; in aspeed_smc_dma_rw()
1059 s->regs[R_DMA_CHECKSUM] += data; in aspeed_smc_dma_rw()
1066 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the in aspeed_smc_dma_stop()
1069 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; in aspeed_smc_dma_stop()
1070 s->regs[R_DMA_CHECKSUM] = 0; in aspeed_smc_dma_stop()
1073 * Lower the DMA irq in any case. The IRQ control register could in aspeed_smc_dma_stop()
1074 * have been cleared before disabling the DMA. in aspeed_smc_dma_stop()
1076 qemu_irq_lower(s->irq); in aspeed_smc_dma_stop()
1080 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
1085 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && in aspeed_smc_dma_in_progress()
1086 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); in aspeed_smc_dma_in_progress()
1091 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; in aspeed_smc_dma_done()
1092 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { in aspeed_smc_dma_done()
1093 qemu_irq_raise(s->irq); in aspeed_smc_dma_done()
1100 s->regs[R_DMA_CTRL] = dma_ctrl; in aspeed_smc_dma_ctrl()
1107 aspeed_smc_error("DMA in progress !"); in aspeed_smc_dma_ctrl()
1111 s->regs[R_DMA_CTRL] = dma_ctrl; in aspeed_smc_dma_ctrl()
1113 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { in aspeed_smc_dma_ctrl()
1126 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { in aspeed_smc_dma_granted()
1130 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { in aspeed_smc_dma_granted()
1131 aspeed_smc_error("DMA not granted"); in aspeed_smc_dma_granted()
1140 /* Preserve DMA bits */ in aspeed_2600_smc_dma_ctrl()
1141 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1145 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1151 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1156 aspeed_smc_error("DMA not granted"); in aspeed_2600_smc_dma_ctrl()
1161 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1175 if (addr == s->r_conf || in aspeed_smc_write()
1176 (addr >= s->r_timings && in aspeed_smc_write()
1177 addr < s->r_timings + asc->nregs_timings) || in aspeed_smc_write()
1178 addr == s->r_ce_ctrl) { in aspeed_smc_write()
1179 s->regs[addr] = value; in aspeed_smc_write()
1180 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { in aspeed_smc_write()
1181 int cs = addr - s->r_ctrl0; in aspeed_smc_write()
1182 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); in aspeed_smc_write()
1184 addr < R_SEG_ADDR0 + asc->cs_num_max) { in aspeed_smc_write()
1185 int cs = addr - R_SEG_ADDR0; in aspeed_smc_write()
1187 if (value != s->regs[R_SEG_ADDR0 + cs]) { in aspeed_smc_write()
1191 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1193 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1201 s->regs[addr] = value; in aspeed_smc_write()
1203 asc->dma_ctrl(s, value); in aspeed_smc_write()
1206 s->regs[addr] = DMA_DRAM_ADDR(asc, value); in aspeed_smc_write()
1209 s->regs[addr] = DMA_FLASH_ADDR(asc, value); in aspeed_smc_write()
1212 s->regs[addr] = DMA_LENGTH(value); in aspeed_smc_write()
1215 s->regs[addr] = DMA_DRAM_ADDR_HIGH(value); in aspeed_smc_write()
1235 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_instance_init()
1236 object_initialize_child(obj, "flash[*]", &s->flashes[i], in aspeed_smc_instance_init()
1246 if (!s->dram_mr) { in aspeed_smc_dma_setup()
1251 address_space_init(&s->flash_as, &s->mmio_flash, in aspeed_smc_dma_setup()
1252 TYPE_ASPEED_SMC ".dma-flash"); in aspeed_smc_dma_setup()
1253 address_space_init(&s->dram_as, s->dram_mr, in aspeed_smc_dma_setup()
1254 TYPE_ASPEED_SMC ".dma-dram"); in aspeed_smc_dma_setup()
1259 if (!s->wdt2_mr) { in aspeed_smc_wdt_setup()
1264 address_space_init(&s->wdt2_as, s->wdt2_mr, TYPE_ASPEED_SMC ".wdt2"); in aspeed_smc_wdt_setup()
1276 s->r_conf = asc->r_conf; in aspeed_smc_realize()
1277 s->r_ce_ctrl = asc->r_ce_ctrl; in aspeed_smc_realize()
1278 s->r_ctrl0 = asc->r_ctrl0; in aspeed_smc_realize()
1279 s->r_timings = asc->r_timings; in aspeed_smc_realize()
1280 s->conf_enable_w0 = asc->conf_enable_w0; in aspeed_smc_realize()
1282 /* DMA irq. Keep it first for the initialization in the SoC */ in aspeed_smc_realize()
1283 sysbus_init_irq(sbd, &s->irq); in aspeed_smc_realize()
1285 s->spi = ssi_create_bus(dev, NULL); in aspeed_smc_realize()
1288 s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); in aspeed_smc_realize()
1289 qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max); in aspeed_smc_realize()
1292 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, in aspeed_smc_realize()
1293 TYPE_ASPEED_SMC, asc->nregs * 4); in aspeed_smc_realize()
1294 sysbus_init_mmio(sbd, &s->mmio); in aspeed_smc_realize()
1298 * window in which the flash modules are mapped. The size and in aspeed_smc_realize()
1301 memory_region_init(&s->mmio_flash_container, OBJECT(s), in aspeed_smc_realize()
1303 asc->flash_window_size); in aspeed_smc_realize()
1304 sysbus_init_mmio(sbd, &s->mmio_flash_container); in aspeed_smc_realize()
1306 memory_region_init_io(&s->mmio_flash, OBJECT(s), in aspeed_smc_realize()
1308 TYPE_ASPEED_SMC ".flash", in aspeed_smc_realize()
1309 asc->flash_window_size); in aspeed_smc_realize()
1310 memory_region_add_subregion(&s->mmio_flash_container, 0x0, in aspeed_smc_realize()
1311 &s->mmio_flash); in aspeed_smc_realize()
1315 * have a configurable memory segment in the overall flash mapping in aspeed_smc_realize()
1316 * window of the controller but, there is not necessarily a flash in aspeed_smc_realize()
1320 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_realize()
1321 AspeedSMCFlash *fl = &s->flashes[i]; in aspeed_smc_realize()
1334 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); in aspeed_smc_realize()
1335 offset += asc->segments[i].size; in aspeed_smc_realize()
1338 /* DMA support */ in aspeed_smc_realize()
1363 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1364 DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
1376 dc->realize = aspeed_smc_realize; in aspeed_smc_class_init()
1379 dc->vmsd = &vmstate_aspeed_smc; in aspeed_smc_class_init()
1395 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs); in aspeed_smc_flash_realize()
1397 if (!s->controller) { in aspeed_smc_flash_realize()
1402 s->asc = ASPEED_SMC_GET_CLASS(s->controller); in aspeed_smc_flash_realize()
1408 memory_region_init_io(&s->mmio, OBJECT(s), s->asc->reg_ops, in aspeed_smc_flash_realize()
1409 s, name, s->asc->segments[s->cs].size); in aspeed_smc_flash_realize()
1410 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); in aspeed_smc_flash_realize()
1424 dc->desc = "Aspeed SMC Flash device region"; in aspeed_smc_flash_class_init()
1425 dc->realize = aspeed_smc_flash_realize; in aspeed_smc_flash_class_init()
1438 * unit. The address range of a flash SPI peripheral is encoded with
1446 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; in aspeed_smc_segment_to_reg()
1447 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; in aspeed_smc_segment_to_reg()
1454 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; in aspeed_smc_reg_to_segment()
1455 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; in aspeed_smc_reg_to_segment()
1467 dc->desc = "Aspeed 2400 SMC Controller"; in aspeed_2400_smc_class_init()
1468 asc->r_conf = R_CONF; in aspeed_2400_smc_class_init()
1469 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2400_smc_class_init()
1470 asc->r_ctrl0 = R_CTRL0; in aspeed_2400_smc_class_init()
1471 asc->r_timings = R_TIMINGS; in aspeed_2400_smc_class_init()
1472 asc->nregs_timings = 1; in aspeed_2400_smc_class_init()
1473 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2400_smc_class_init()
1474 asc->cs_num_max = 1; in aspeed_2400_smc_class_init()
1475 asc->segments = aspeed_2400_smc_segments; in aspeed_2400_smc_class_init()
1476 asc->flash_window_base = 0x10000000; in aspeed_2400_smc_class_init()
1477 asc->flash_window_size = 0x6000000; in aspeed_2400_smc_class_init()
1478 asc->features = 0x0; in aspeed_2400_smc_class_init()
1479 asc->nregs = ASPEED_SMC_R_SMC_MAX; in aspeed_2400_smc_class_init()
1480 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2400_smc_class_init()
1481 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2400_smc_class_init()
1482 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2400_smc_class_init()
1483 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2400_smc_class_init()
1487 .name = "aspeed.smc-ast2400",
1513 dc->desc = "Aspeed 2400 FMC Controller"; in aspeed_2400_fmc_class_init()
1514 asc->r_conf = R_CONF; in aspeed_2400_fmc_class_init()
1515 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2400_fmc_class_init()
1516 asc->r_ctrl0 = R_CTRL0; in aspeed_2400_fmc_class_init()
1517 asc->r_timings = R_TIMINGS; in aspeed_2400_fmc_class_init()
1518 asc->nregs_timings = 1; in aspeed_2400_fmc_class_init()
1519 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2400_fmc_class_init()
1520 asc->cs_num_max = 5; in aspeed_2400_fmc_class_init()
1521 asc->segments = aspeed_2400_fmc_segments; in aspeed_2400_fmc_class_init()
1522 asc->segment_addr_mask = 0xffff0000; in aspeed_2400_fmc_class_init()
1523 asc->resets = aspeed_2400_fmc_resets; in aspeed_2400_fmc_class_init()
1524 asc->flash_window_base = 0x20000000; in aspeed_2400_fmc_class_init()
1525 asc->flash_window_size = 0x10000000; in aspeed_2400_fmc_class_init()
1526 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_2400_fmc_class_init()
1527 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2400_fmc_class_init()
1528 asc->dma_dram_mask = 0x1FFFFFFC; in aspeed_2400_fmc_class_init()
1529 asc->dma_start_length = 4; in aspeed_2400_fmc_class_init()
1530 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2400_fmc_class_init()
1531 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2400_fmc_class_init()
1532 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2400_fmc_class_init()
1533 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2400_fmc_class_init()
1534 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2400_fmc_class_init()
1538 .name = "aspeed.fmc-ast2400",
1549 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3; in aspeed_2400_spi1_addr_width()
1557 dc->desc = "Aspeed 2400 SPI1 Controller"; in aspeed_2400_spi1_class_init()
1558 asc->r_conf = R_SPI_CONF; in aspeed_2400_spi1_class_init()
1559 asc->r_ce_ctrl = 0xff; in aspeed_2400_spi1_class_init()
1560 asc->r_ctrl0 = R_SPI_CTRL0; in aspeed_2400_spi1_class_init()
1561 asc->r_timings = R_SPI_TIMINGS; in aspeed_2400_spi1_class_init()
1562 asc->nregs_timings = 1; in aspeed_2400_spi1_class_init()
1563 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; in aspeed_2400_spi1_class_init()
1564 asc->cs_num_max = 1; in aspeed_2400_spi1_class_init()
1565 asc->segments = aspeed_2400_spi1_segments; in aspeed_2400_spi1_class_init()
1566 asc->flash_window_base = 0x30000000; in aspeed_2400_spi1_class_init()
1567 asc->flash_window_size = 0x10000000; in aspeed_2400_spi1_class_init()
1568 asc->features = 0x0; in aspeed_2400_spi1_class_init()
1569 asc->nregs = ASPEED_SMC_R_SPI_MAX; in aspeed_2400_spi1_class_init()
1570 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2400_spi1_class_init()
1571 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2400_spi1_class_init()
1572 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2400_spi1_class_init()
1573 asc->addr_width = aspeed_2400_spi1_addr_width; in aspeed_2400_spi1_class_init()
1574 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2400_spi1_class_init()
1578 .name = "aspeed.spi1-ast2400",
1599 dc->desc = "Aspeed 2500 FMC Controller"; in aspeed_2500_fmc_class_init()
1600 asc->r_conf = R_CONF; in aspeed_2500_fmc_class_init()
1601 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2500_fmc_class_init()
1602 asc->r_ctrl0 = R_CTRL0; in aspeed_2500_fmc_class_init()
1603 asc->r_timings = R_TIMINGS; in aspeed_2500_fmc_class_init()
1604 asc->nregs_timings = 1; in aspeed_2500_fmc_class_init()
1605 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2500_fmc_class_init()
1606 asc->cs_num_max = 3; in aspeed_2500_fmc_class_init()
1607 asc->segments = aspeed_2500_fmc_segments; in aspeed_2500_fmc_class_init()
1608 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_fmc_class_init()
1609 asc->resets = aspeed_2500_fmc_resets; in aspeed_2500_fmc_class_init()
1610 asc->flash_window_base = 0x20000000; in aspeed_2500_fmc_class_init()
1611 asc->flash_window_size = 0x10000000; in aspeed_2500_fmc_class_init()
1612 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_2500_fmc_class_init()
1613 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2500_fmc_class_init()
1614 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2500_fmc_class_init()
1615 asc->dma_start_length = 4; in aspeed_2500_fmc_class_init()
1616 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2500_fmc_class_init()
1617 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2500_fmc_class_init()
1618 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2500_fmc_class_init()
1619 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2500_fmc_class_init()
1620 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2500_fmc_class_init()
1624 .name = "aspeed.fmc-ast2500",
1639 dc->desc = "Aspeed 2500 SPI1 Controller"; in aspeed_2500_spi1_class_init()
1640 asc->r_conf = R_CONF; in aspeed_2500_spi1_class_init()
1641 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2500_spi1_class_init()
1642 asc->r_ctrl0 = R_CTRL0; in aspeed_2500_spi1_class_init()
1643 asc->r_timings = R_TIMINGS; in aspeed_2500_spi1_class_init()
1644 asc->nregs_timings = 1; in aspeed_2500_spi1_class_init()
1645 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2500_spi1_class_init()
1646 asc->cs_num_max = 2; in aspeed_2500_spi1_class_init()
1647 asc->segments = aspeed_2500_spi1_segments; in aspeed_2500_spi1_class_init()
1648 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi1_class_init()
1649 asc->flash_window_base = 0x30000000; in aspeed_2500_spi1_class_init()
1650 asc->flash_window_size = 0x8000000; in aspeed_2500_spi1_class_init()
1651 asc->features = 0x0; in aspeed_2500_spi1_class_init()
1652 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2500_spi1_class_init()
1653 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2500_spi1_class_init()
1654 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2500_spi1_class_init()
1655 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2500_spi1_class_init()
1656 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2500_spi1_class_init()
1660 .name = "aspeed.spi1-ast2500",
1675 dc->desc = "Aspeed 2500 SPI2 Controller"; in aspeed_2500_spi2_class_init()
1676 asc->r_conf = R_CONF; in aspeed_2500_spi2_class_init()
1677 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2500_spi2_class_init()
1678 asc->r_ctrl0 = R_CTRL0; in aspeed_2500_spi2_class_init()
1679 asc->r_timings = R_TIMINGS; in aspeed_2500_spi2_class_init()
1680 asc->nregs_timings = 1; in aspeed_2500_spi2_class_init()
1681 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2500_spi2_class_init()
1682 asc->cs_num_max = 2; in aspeed_2500_spi2_class_init()
1683 asc->segments = aspeed_2500_spi2_segments; in aspeed_2500_spi2_class_init()
1684 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi2_class_init()
1685 asc->flash_window_base = 0x38000000; in aspeed_2500_spi2_class_init()
1686 asc->flash_window_size = 0x8000000; in aspeed_2500_spi2_class_init()
1687 asc->features = 0x0; in aspeed_2500_spi2_class_init()
1688 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2500_spi2_class_init()
1689 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2500_spi2_class_init()
1690 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2500_spi2_class_init()
1691 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2500_spi2_class_init()
1692 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2500_spi2_class_init()
1696 .name = "aspeed.spi2-ast2500",
1703 * range of a flash SPI peripheral is encoded with offsets in the overall
1716 if (!seg->size) { in aspeed_2600_smc_segment_to_reg()
1720 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ in aspeed_2600_smc_segment_to_reg()
1721 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ in aspeed_2600_smc_segment_to_reg()
1733 seg->addr = asc->flash_window_base + start_offset; in aspeed_2600_smc_reg_to_segment()
1734 seg->size = end_offset + MiB - start_offset; in aspeed_2600_smc_reg_to_segment()
1736 seg->addr = asc->flash_window_base; in aspeed_2600_smc_reg_to_segment()
1737 seg->size = 0; in aspeed_2600_smc_reg_to_segment()
1749 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1758 dc->desc = "Aspeed 2600 FMC Controller"; in aspeed_2600_fmc_class_init()
1759 asc->r_conf = R_CONF; in aspeed_2600_fmc_class_init()
1760 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2600_fmc_class_init()
1761 asc->r_ctrl0 = R_CTRL0; in aspeed_2600_fmc_class_init()
1762 asc->r_timings = R_TIMINGS; in aspeed_2600_fmc_class_init()
1763 asc->nregs_timings = 1; in aspeed_2600_fmc_class_init()
1764 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2600_fmc_class_init()
1765 asc->cs_num_max = 3; in aspeed_2600_fmc_class_init()
1766 asc->segments = aspeed_2600_fmc_segments; in aspeed_2600_fmc_class_init()
1767 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_fmc_class_init()
1768 asc->resets = aspeed_2600_fmc_resets; in aspeed_2600_fmc_class_init()
1769 asc->flash_window_base = 0x20000000; in aspeed_2600_fmc_class_init()
1770 asc->flash_window_size = 0x10000000; in aspeed_2600_fmc_class_init()
1771 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2600_fmc_class_init()
1773 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_fmc_class_init()
1774 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_fmc_class_init()
1775 asc->dma_start_length = 1; in aspeed_2600_fmc_class_init()
1776 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2600_fmc_class_init()
1777 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_2600_fmc_class_init()
1778 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_2600_fmc_class_init()
1779 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2600_fmc_class_init()
1780 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2600_fmc_class_init()
1784 .name = "aspeed.fmc-ast2600",
1799 dc->desc = "Aspeed 2600 SPI1 Controller"; in aspeed_2600_spi1_class_init()
1800 asc->r_conf = R_CONF; in aspeed_2600_spi1_class_init()
1801 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2600_spi1_class_init()
1802 asc->r_ctrl0 = R_CTRL0; in aspeed_2600_spi1_class_init()
1803 asc->r_timings = R_TIMINGS; in aspeed_2600_spi1_class_init()
1804 asc->nregs_timings = 2; in aspeed_2600_spi1_class_init()
1805 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2600_spi1_class_init()
1806 asc->cs_num_max = 2; in aspeed_2600_spi1_class_init()
1807 asc->segments = aspeed_2600_spi1_segments; in aspeed_2600_spi1_class_init()
1808 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi1_class_init()
1809 asc->flash_window_base = 0x30000000; in aspeed_2600_spi1_class_init()
1810 asc->flash_window_size = 0x10000000; in aspeed_2600_spi1_class_init()
1811 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2600_spi1_class_init()
1813 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi1_class_init()
1814 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi1_class_init()
1815 asc->dma_start_length = 1; in aspeed_2600_spi1_class_init()
1816 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2600_spi1_class_init()
1817 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_2600_spi1_class_init()
1818 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_2600_spi1_class_init()
1819 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2600_spi1_class_init()
1820 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2600_spi1_class_init()
1824 .name = "aspeed.spi1-ast2600",
1840 dc->desc = "Aspeed 2600 SPI2 Controller"; in aspeed_2600_spi2_class_init()
1841 asc->r_conf = R_CONF; in aspeed_2600_spi2_class_init()
1842 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2600_spi2_class_init()
1843 asc->r_ctrl0 = R_CTRL0; in aspeed_2600_spi2_class_init()
1844 asc->r_timings = R_TIMINGS; in aspeed_2600_spi2_class_init()
1845 asc->nregs_timings = 3; in aspeed_2600_spi2_class_init()
1846 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2600_spi2_class_init()
1847 asc->cs_num_max = 3; in aspeed_2600_spi2_class_init()
1848 asc->segments = aspeed_2600_spi2_segments; in aspeed_2600_spi2_class_init()
1849 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi2_class_init()
1850 asc->flash_window_base = 0x50000000; in aspeed_2600_spi2_class_init()
1851 asc->flash_window_size = 0x10000000; in aspeed_2600_spi2_class_init()
1852 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2600_spi2_class_init()
1854 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi2_class_init()
1855 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi2_class_init()
1856 asc->dma_start_length = 1; in aspeed_2600_spi2_class_init()
1857 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2600_spi2_class_init()
1858 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_2600_spi2_class_init()
1859 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_2600_spi2_class_init()
1860 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2600_spi2_class_init()
1861 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2600_spi2_class_init()
1865 .name = "aspeed.spi2-ast2600",
1882 if (!seg->size) { in aspeed_1030_smc_segment_to_reg()
1886 reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ in aspeed_1030_smc_segment_to_reg()
1887 reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ in aspeed_1030_smc_segment_to_reg()
1899 seg->addr = asc->flash_window_base + start_offset; in aspeed_1030_smc_reg_to_segment()
1900 seg->size = end_offset + (512 * KiB) - start_offset; in aspeed_1030_smc_reg_to_segment()
1902 seg->addr = asc->flash_window_base; in aspeed_1030_smc_reg_to_segment()
1903 seg->size = 0; in aspeed_1030_smc_reg_to_segment()
1914 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1923 dc->desc = "Aspeed 1030 FMC Controller"; in aspeed_1030_fmc_class_init()
1924 asc->r_conf = R_CONF; in aspeed_1030_fmc_class_init()
1925 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_1030_fmc_class_init()
1926 asc->r_ctrl0 = R_CTRL0; in aspeed_1030_fmc_class_init()
1927 asc->r_timings = R_TIMINGS; in aspeed_1030_fmc_class_init()
1928 asc->nregs_timings = 2; in aspeed_1030_fmc_class_init()
1929 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_1030_fmc_class_init()
1930 asc->cs_num_max = 2; in aspeed_1030_fmc_class_init()
1931 asc->segments = aspeed_1030_fmc_segments; in aspeed_1030_fmc_class_init()
1932 asc->segment_addr_mask = 0x0ff80ff8; in aspeed_1030_fmc_class_init()
1933 asc->resets = aspeed_1030_fmc_resets; in aspeed_1030_fmc_class_init()
1934 asc->flash_window_base = 0x80000000; in aspeed_1030_fmc_class_init()
1935 asc->flash_window_size = 0x10000000; in aspeed_1030_fmc_class_init()
1936 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_1030_fmc_class_init()
1937 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_fmc_class_init()
1938 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_fmc_class_init()
1939 asc->dma_start_length = 1; in aspeed_1030_fmc_class_init()
1940 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_1030_fmc_class_init()
1941 asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; in aspeed_1030_fmc_class_init()
1942 asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; in aspeed_1030_fmc_class_init()
1943 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_1030_fmc_class_init()
1944 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_1030_fmc_class_init()
1948 .name = "aspeed.fmc-ast1030",
1963 dc->desc = "Aspeed 1030 SPI1 Controller"; in aspeed_1030_spi1_class_init()
1964 asc->r_conf = R_CONF; in aspeed_1030_spi1_class_init()
1965 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_1030_spi1_class_init()
1966 asc->r_ctrl0 = R_CTRL0; in aspeed_1030_spi1_class_init()
1967 asc->r_timings = R_TIMINGS; in aspeed_1030_spi1_class_init()
1968 asc->nregs_timings = 2; in aspeed_1030_spi1_class_init()
1969 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_1030_spi1_class_init()
1970 asc->cs_num_max = 2; in aspeed_1030_spi1_class_init()
1971 asc->segments = aspeed_1030_spi1_segments; in aspeed_1030_spi1_class_init()
1972 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi1_class_init()
1973 asc->flash_window_base = 0x90000000; in aspeed_1030_spi1_class_init()
1974 asc->flash_window_size = 0x10000000; in aspeed_1030_spi1_class_init()
1975 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_1030_spi1_class_init()
1976 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi1_class_init()
1977 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi1_class_init()
1978 asc->dma_start_length = 1; in aspeed_1030_spi1_class_init()
1979 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_1030_spi1_class_init()
1980 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_1030_spi1_class_init()
1981 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_1030_spi1_class_init()
1982 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_1030_spi1_class_init()
1983 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_1030_spi1_class_init()
1987 .name = "aspeed.spi1-ast1030",
2001 dc->desc = "Aspeed 1030 SPI2 Controller"; in aspeed_1030_spi2_class_init()
2002 asc->r_conf = R_CONF; in aspeed_1030_spi2_class_init()
2003 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_1030_spi2_class_init()
2004 asc->r_ctrl0 = R_CTRL0; in aspeed_1030_spi2_class_init()
2005 asc->r_timings = R_TIMINGS; in aspeed_1030_spi2_class_init()
2006 asc->nregs_timings = 2; in aspeed_1030_spi2_class_init()
2007 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_1030_spi2_class_init()
2008 asc->cs_num_max = 2; in aspeed_1030_spi2_class_init()
2009 asc->segments = aspeed_1030_spi2_segments; in aspeed_1030_spi2_class_init()
2010 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi2_class_init()
2011 asc->flash_window_base = 0xb0000000; in aspeed_1030_spi2_class_init()
2012 asc->flash_window_size = 0x10000000; in aspeed_1030_spi2_class_init()
2013 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_1030_spi2_class_init()
2014 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi2_class_init()
2015 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi2_class_init()
2016 asc->dma_start_length = 1; in aspeed_1030_spi2_class_init()
2017 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_1030_spi2_class_init()
2018 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_1030_spi2_class_init()
2019 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_1030_spi2_class_init()
2020 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_1030_spi2_class_init()
2021 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_1030_spi2_class_init()
2025 .name = "aspeed.spi2-ast1030",
2042 if (!seg->size) { in aspeed_2700_smc_segment_to_reg()
2046 reg |= (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */ in aspeed_2700_smc_segment_to_reg()
2047 reg |= (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end offset */ in aspeed_2700_smc_segment_to_reg()
2059 seg->addr = asc->flash_window_base + start_offset; in aspeed_2700_smc_reg_to_segment()
2060 seg->size = end_offset + (64 * KiB) - start_offset; in aspeed_2700_smc_reg_to_segment()
2062 seg->addr = asc->flash_window_base; in aspeed_2700_smc_reg_to_segment()
2063 seg->size = 0; in aspeed_2700_smc_reg_to_segment()
2096 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
2097 { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
2106 dc->desc = "Aspeed 2700 FMC Controller"; in aspeed_2700_fmc_class_init()
2107 asc->r_conf = R_CONF; in aspeed_2700_fmc_class_init()
2108 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_fmc_class_init()
2109 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_fmc_class_init()
2110 asc->r_timings = R_TIMINGS; in aspeed_2700_fmc_class_init()
2111 asc->nregs_timings = 3; in aspeed_2700_fmc_class_init()
2112 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_fmc_class_init()
2113 asc->cs_num_max = 3; in aspeed_2700_fmc_class_init()
2114 asc->segments = aspeed_2700_fmc_segments; in aspeed_2700_fmc_class_init()
2115 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_fmc_class_init()
2116 asc->resets = aspeed_2700_fmc_resets; in aspeed_2700_fmc_class_init()
2117 asc->flash_window_base = 0x100000000; in aspeed_2700_fmc_class_init()
2118 asc->flash_window_size = 1 * GiB; in aspeed_2700_fmc_class_init()
2119 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_fmc_class_init()
2121 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_fmc_class_init()
2122 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_fmc_class_init()
2123 asc->dma_start_length = 1; in aspeed_2700_fmc_class_init()
2124 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_fmc_class_init()
2125 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_fmc_class_init()
2126 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_fmc_class_init()
2127 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_fmc_class_init()
2128 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_fmc_class_init()
2132 .name = "aspeed.fmc-ast2700",
2148 dc->desc = "Aspeed 2700 SPI0 Controller"; in aspeed_2700_spi0_class_init()
2149 asc->r_conf = R_CONF; in aspeed_2700_spi0_class_init()
2150 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_spi0_class_init()
2151 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_spi0_class_init()
2152 asc->r_timings = R_TIMINGS; in aspeed_2700_spi0_class_init()
2153 asc->nregs_timings = 2; in aspeed_2700_spi0_class_init()
2154 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_spi0_class_init()
2155 asc->cs_num_max = 2; in aspeed_2700_spi0_class_init()
2156 asc->segments = aspeed_2700_spi0_segments; in aspeed_2700_spi0_class_init()
2157 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi0_class_init()
2158 asc->flash_window_base = 0x180000000; in aspeed_2700_spi0_class_init()
2159 asc->flash_window_size = 1 * GiB; in aspeed_2700_spi0_class_init()
2160 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_spi0_class_init()
2162 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi0_class_init()
2163 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi0_class_init()
2164 asc->dma_start_length = 1; in aspeed_2700_spi0_class_init()
2165 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_spi0_class_init()
2166 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_spi0_class_init()
2167 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_spi0_class_init()
2168 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_spi0_class_init()
2169 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_spi0_class_init()
2173 .name = "aspeed.spi0-ast2700",
2188 dc->desc = "Aspeed 2700 SPI1 Controller"; in aspeed_2700_spi1_class_init()
2189 asc->r_conf = R_CONF; in aspeed_2700_spi1_class_init()
2190 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_spi1_class_init()
2191 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_spi1_class_init()
2192 asc->r_timings = R_TIMINGS; in aspeed_2700_spi1_class_init()
2193 asc->nregs_timings = 2; in aspeed_2700_spi1_class_init()
2194 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_spi1_class_init()
2195 asc->cs_num_max = 2; in aspeed_2700_spi1_class_init()
2196 asc->segments = aspeed_2700_spi1_segments; in aspeed_2700_spi1_class_init()
2197 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi1_class_init()
2198 asc->flash_window_base = 0x200000000; in aspeed_2700_spi1_class_init()
2199 asc->flash_window_size = 1 * GiB; in aspeed_2700_spi1_class_init()
2200 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_spi1_class_init()
2202 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi1_class_init()
2203 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi1_class_init()
2204 asc->dma_start_length = 1; in aspeed_2700_spi1_class_init()
2205 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_spi1_class_init()
2206 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_spi1_class_init()
2207 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_spi1_class_init()
2208 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_spi1_class_init()
2209 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_spi1_class_init()
2213 .name = "aspeed.spi1-ast2700",
2228 dc->desc = "Aspeed 2700 SPI2 Controller"; in aspeed_2700_spi2_class_init()
2229 asc->r_conf = R_CONF; in aspeed_2700_spi2_class_init()
2230 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_spi2_class_init()
2231 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_spi2_class_init()
2232 asc->r_timings = R_TIMINGS; in aspeed_2700_spi2_class_init()
2233 asc->nregs_timings = 2; in aspeed_2700_spi2_class_init()
2234 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_spi2_class_init()
2235 asc->cs_num_max = 2; in aspeed_2700_spi2_class_init()
2236 asc->segments = aspeed_2700_spi2_segments; in aspeed_2700_spi2_class_init()
2237 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi2_class_init()
2238 asc->flash_window_base = 0x280000000; in aspeed_2700_spi2_class_init()
2239 asc->flash_window_size = 1 * GiB; in aspeed_2700_spi2_class_init()
2240 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_spi2_class_init()
2242 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2700_spi2_class_init()
2243 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi2_class_init()
2244 asc->dma_start_length = 1; in aspeed_2700_spi2_class_init()
2245 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_spi2_class_init()
2246 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_spi2_class_init()
2247 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_spi2_class_init()
2248 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_spi2_class_init()
2249 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_spi2_class_init()
2253 .name = "aspeed.spi2-ast2700",