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Searched +full:disable +full:- +full:timing +full:- +full:generator (Results 1 – 25 of 83) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen()
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
42 regmap_write(adv->regmap_cec, 0x16, in adv7511_dsi_config_timing_gen()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
45 /* Trigger Source Select - ASIC-defendant, actual values for the
74 /* Trigger Source Select - ASIC-dependant, actual values for the
126 /* determine if given timing can be supported by TG */
129 const struct dc_crtc_timing *timing,
134 /* Program timing generator with given timing */
139 /* Disable/Enable Timing Generator */
166 /*********** Timing Generator Synchronization routines ****/
188 /* disabling trigger-reset */
200 /* Fully program CRTC timing in timing generator */
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H A Ddce110_timing_generator.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
49 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
55 * So we can create dce110 timing generator to use it.
67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
34 optc1->tg_regs->reg
37 optc1->base.ctx
41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
44 struct dc_crtc_timing *timing) in optc31_set_odm_combine() argument
47 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) in optc31_set_odm_combine()
90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
91 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
95 * Enable CRTC - call ASIC Control Object to enable Timing generator.
103 OPTC_SEG0_SRC_SEL, optc->inst); in optc31_enable_crtc()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
33 optc1->tg_regs->reg
36 optc1->base.ctx
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
45 * apply_front_porch_workaround() - This is a workaround for a bug that has
50 * @timing: Timing parameters used to configure DCN blocks.
52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) in apply_front_porch_workaround() argument
54 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
55 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
56 timing->v_front_porch = 2; in apply_front_porch_workaround()
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/openbmc/linux/drivers/video/fbdev/geode/
H A Ddisplay_gx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The number of pages is (PMAX - PMIN)+1 */ in gx_frame_buffer_size()
33 val -= (lo & 0x000fffff); in gx_frame_buffer_size()
59 struct gxfb_par *par = info->par; in gx_set_mode()
70 /* Disable the timing generator. */ in gx_set_mode()
77 /* Disable FIFO load and compression. */ in gx_set_mode()
102 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); in gx_set_mode()
104 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2); in gx_set_mode()
112 switch (info->var.bits_per_pixel) { in gx_set_mode()
125 /* Enable timing generator. */ in gx_set_mode()
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H A Ddisplay_gx1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * -- Geode GX1 display controller
58 return -ENOMEM; in gx1_frame_buffer_size()
74 return dram_size - fb_base; in gx1_frame_buffer_size()
79 struct geodefb_par *par = info->par; in gx1_set_mode()
85 readl(par->dc_regs + DC_UNLOCK); in gx1_set_mode()
86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
88 gcfg = readl(par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
89 tcfg = readl(par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
91 /* Blank the display and disable the timing generator. */ in gx1_set_mode()
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dadi,adv7533.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
20 - adi,adv7533
21 - adi,adv7535
35 reg-names:
38 needing a non-default address.
41 - const: main
42 - const: edid
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.c1 // SPDX-License-Identifier: MIT
36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
47 * Enable CRTC - call ASIC Control Object to enable Timing generator.
51 struct dc_crtc_timing *timing) in optc314_set_odm_combine() argument
55 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; in optc314_set_odm_combine()
102 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
103 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
112 OPTC_SEG0_SRC_SEL, optc->inst); in optc314_enable_crtc()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.c36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
46 struct dc_crtc_timing *timing) in optc32_set_odm_combine() argument
50 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; in optc32_set_odm_combine()
97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
98 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
109 * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
121 OPTC_SEG0_SRC_SEL, optc->inst); in optc32_enable_crtc()
155 /* disable otg request until end of the first line in optc32_disable_crtc()
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/openbmc/linux/drivers/tty/serial/
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
67 #define RxINT_DISAB 0 /* Rx Int Disable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
137 #define nDTRnREQ 0x10 /* /DTR/REQ timing */
146 #define DLC 4 /* Disable Lower Chain */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dcafe_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
92 static int timing[3]; variable
93 module_param_array(timing, int, &numtimings, 0644);
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", in cafe_device_ready()
124 if (cafe->usedma) in cafe_write_buf()
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); in cafe_write_buf()
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
129 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
138 hw->init = &init; in meson8b_dwmac_register_clk()
140 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
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/openbmc/linux/arch/sh/include/asm/
H A Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
81 /* DISPLAY-ENABLE polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
148 * Display Enable signal (default high-active) DISPEN_LOWACT
149 * Display Data signals (default high-active) DPOL_LOWACT
151 * Hsync-During-Vsync suppression (default off) CL1CNT
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
31 optc1->tg_regs->reg
34 optc1->base.ctx
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
41 * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
60 OPTC_SEG0_SRC_SEL, optc->inst); in optc2_enable_crtc()
80 * optc2_set_gsl() - Assign OTG to GSL groups,
97 OTG_GSL0_EN, params->gsl0_en, in optc2_set_gsl()
98 OTG_GSL1_EN, params->gsl1_en, in optc2_set_gsl()
99 OTG_GSL2_EN, params->gsl2_en, in optc2_set_gsl()
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/openbmc/linux/drivers/media/i2c/
H A Dths8200.c2 * ths8200 - Texas Instruments THS8200 video encoder driver
23 #include <linux/v4l2-dv-timings.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-device.h>
33 MODULE_PARM_DESC(debug, "debug level (0-2)");
93 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
94 * and then the value-mask (to be OR-ed).
108 reg->val = ths8200_read(sd, reg->reg & 0xff); in ths8200_g_register()
109 reg->size = 1; in ths8200_g_register()
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H A Dtda1997x.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/v4l2-dv-timings.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
31 #include <dt-bindings/media/tda1997x.h>
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
46 "OBA", /* One-Bit Audio */
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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
37 stdout-path = "serial0:115200n8";
47 gpio-keys {
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
36 stdout-path = "serial0:115200n8";
56 phy-handle = <&phy0>;
57 phy-mode = "rgmii-id";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
36 stdout-path = "serial0:115200n8";
55 phy-handle = <&phy0>;
56 phy-mode = "rgmii-id";
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/openbmc/linux/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
170 bool "Disable run-time self tests"
173 Disable run-time self tests that normally take place at
177 bool "Enable extra run-time crypto self tests"
180 Enable extra run-time self tests of registered crypto algorithms,
246 menu "Public-key cryptography"
249 tristate "RSA (Rivest-Shamir-Adleman)"
255 RSA (Rivest-Shamir-Adleman) public key algorithm (RFC8017)
258 tristate "DH (Diffie-Hellman)"
262 DH (Diffie-Hellman) key exchange algorithm
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/openbmc/linux/drivers/media/usb/gspca/
H A Dstk1135.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 /* -- read a register -- */
48 struct usb_device *dev = gspca_dev->dev; in reg_r()
51 if (gspca_dev->usb_err < 0) in reg_r()
58 gspca_dev->usb_buf, 1, in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
65 gspca_dev->usb_err = ret; in reg_r()
69 return gspca_dev->usb_buf[0]; in reg_r()
72 /* -- write a register -- */
76 struct usb_device *dev = gspca_dev->dev; in reg_w()
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/openbmc/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
34 #define BBC_EBUST 0x20 /* [Q] EBUS Timing */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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