tty/serial/sunzilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
67 #define	RxINT_DISAB	0	/* Rx Int Disable */
118 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
137 #define	nDTRnREQ	0x10	/* /DTR/REQ timing */
146 #define	DLC	4	/* Disable Lower Chain */
170 #define	TRxCBR	2	/* TRxC = BR Generator Output */
175 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
179 #define	RCBR	0x40	/* Receive clock = BR Generator output */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
188 #define	BRENAB 	1	/* Baud rate generator enable */
189 #define	BRSRC	2	/* Baud rate generator source */
195 #define	DISDPLL	0x60	/* Disable DPLL */
196 #define	SSBR	0x80	/* Set DPLL source = BR generator */
239 /* Read Register 2 (channel b only) - Interrupt vector */
270 /* Read Register 12 (lower byte of baud rate generator constant) */
272 /* Read Register 13 (upper byte of baud rate generator constant) */
277 #define ZS_CLEARERR(channel)    do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel)   do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel)   do { sbus_readb(&channel->data); \
285 				     sbus_readb(&channel->data); \
287 				     sbus_readb(&channel->data); \