Home
last modified time | relevance | path

Searched +full:cycle +full:- +full:4 (Results 1 – 25 of 1040) sorted by relevance

12345678910>>...42

/openbmc/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
H A Dev6-memchr.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memchr.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9 * - memory accessed as aligned quadwords only
10 * - uses cmpbge to compare 8 bytes in parallel
11 * - does binary search to find 0 byte in last
18 * - only minimum number of quadwords may be accessed
19 * - the third argument is an unsigned long
24 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26 * E - either cluster
[all …]
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
55 ldq_u $4,0($16) /* E0 */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle3 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
4 source /usr/libexec/phosphor-state-manager/power-cmd
6 #Sled cycle
[all...]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json6 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
13 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
20 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
27 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
34 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
64 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
38 # bit4: 0, addr/cmd in same cycle
41 # bit11-7: 0 required
[all …]
H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
36 # bit4: 0, addr/cmd in smame cycle
[all …]
/openbmc/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Dfloating-point.json6 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
13 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
20 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
27 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
34 …4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for …
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …ly-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired …
53 …are root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
59 …Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
65 …subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
[all …]
/openbmc/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
36 #define RZ_MTU3_TCR2 4 /* Timer control register 2 */
47 /* Only MTU3/4/6/7 have TBTM registers */
[all …]
/openbmc/linux/drivers/staging/vme_user/
H A Dvme_fake.c1 // SPDX-License-Identifier: GPL-2.0-or-later
49 u32 cycle; member
57 u32 cycle; member
70 void (*lm_callback[4])(void *);
71 void *lm_data[4];
99 bridge = fake_bridge->driver_priv; in fake_VIRQ_tasklet()
101 vme_irq_handler(fake_bridge, bridge->int_level, bridge->int_statid); in fake_VIRQ_tasklet()
132 bridge = fake_bridge->driver_priv; in fake_irq_generate()
134 mutex_lock(&bridge->vme_int); in fake_irq_generate()
136 bridge->int_level = level; in fake_irq_generate()
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dvirtual-memory.json56 …cription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
59 …d in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes pag…
65 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
68 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
74 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
77 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
83 …Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
86 …n PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle agai…
92 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
95 …the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A Dvirtual-memory.json11 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page",
14 …hose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page wa…
19 "BriefDescription": "Page walk completed due to a demand load to a 4K page",
22 …hes) whose address translations missed in all TLB levels and were mapped to 4K pages. The page wa…
27 "BriefDescription": "Page walks outstanding due to a demand load every cycle.",
30 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat…
43 "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page",
46 …tores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page wa…
51 "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
54 …data stores whose address translations missed in the TLB and were mapped to 4K pages. The page wa…
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle6 # shellcheck source=meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/powe…
7 source /usr/libexec/phosphor-state-manager/power-cmd
8 # shellcheck source=meta-facebook/meta-yosemite4/recipes-yosemite4/plat-tool/files/yosemite4-common…
9 source /usr/libexec/yosemite4-common-functions
14 IO_EXP_SLOT_PWR_STATUS=$((CHASSIS_ID - 1))
21 if [ -z "$MANAGEMENT_BOARD_VERSION" ]; then
22 echo "Failed to check management board fru info, sled cycle keep default setting"
25 GPIOCHIP_IO_EXP_SLOT_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$SPIDER_BOARD_IO_EXP_BUS_NUM-00$IO_E…
26 GPIOCHIP_IO_EXP_SLED_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$MANAGEMENT_BOARD_IO_EXP_BUS_NUM-00$…
27 #GPIOCHIP_IO_EXP_BIC_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$IO_EXP_SLOT_PWR_STATUS-00$IO_EXP_BI…
[all …]
/openbmc/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
31 @ full unroll ~5100/+260% ~1260/+4% ~1300/+5%
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * STATIC_TRAINING - Set only if static parameters for training are set and
25 /*4 */
45 /*4 */
56 /*center DQS on read cycle */
78 /*4 */
98 /*4 */
118 /*4 */
129 /*center DQS on read cycle */
143 /*0 2 4 15 */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A Dvirtual-memory.json28 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
31 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
36 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
39 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
44 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
47 …the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
77 "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
80 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. Thi…
85 "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
88 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/
H A Dvirtual-memory.json28 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
31 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
36 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
39 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
44 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
47 …the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
77 "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
80 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. Thi…
85 "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
88 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Dvirtual-memory.json28 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
31 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
36 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
39 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
44 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
47 …the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
77 "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
80 …a stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page wa…
85 "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
88 …data stores whose address translations missed in the TLB and were mapped to 4K pages. The page wa…
[all …]
/openbmc/linux/drivers/ata/
H A Dlibata-pata-timings.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
15 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
19 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
22 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1)
63 q->setup = EZ(t->setup, T); in ata_timing_quantize()
64 q->act8b = EZ(t->act8b, T); in ata_timing_quantize()
[all …]
/openbmc/u-boot/drivers/net/
H A Dftmac110.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
44 #define ISR_TXOK (1 << 4) /* tx to ethernet */
65 #define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
66 #define MACCR_LOOPBACK (1 << 3) /* loop-back */
83 /* Tx Cycle Length */
88 /* Tx Interrupt Timeout = n * Tx Cycle */
90 /* Rx Cycle Length */
94 #define ITC_RX_THR(n) (((n) & 0x7) << 4)
95 /* Rx Interrupt Timeout = n * Rx Cycle */
[all …]

12345678910>>...42