1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2ff9112dfSStefan Roese /* 3ff9112dfSStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4ff9112dfSStefan Roese */ 5ff9112dfSStefan Roese 6ff9112dfSStefan Roese #ifndef __AXP_TRAINING_STATIC_H 7ff9112dfSStefan Roese #define __AXP_TRAINING_STATIC_H 8ff9112dfSStefan Roese 9ff9112dfSStefan Roese /* 10ff9112dfSStefan Roese * STATIC_TRAINING - Set only if static parameters for training are set and 11ff9112dfSStefan Roese * required 12ff9112dfSStefan Roese */ 13ff9112dfSStefan Roese 14ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = { 15ff9112dfSStefan Roese /* Read Leveling */ 16ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 17ff9112dfSStefan Roese /*0 */ 18ff9112dfSStefan Roese {0x000016A0, 0xC002011A}, 19ff9112dfSStefan Roese /*1 */ 20ff9112dfSStefan Roese {0x000016A0, 0xC0420100}, 21ff9112dfSStefan Roese /*2 */ 22ff9112dfSStefan Roese {0x000016A0, 0xC082020A}, 23ff9112dfSStefan Roese /*3 */ 24ff9112dfSStefan Roese {0x000016A0, 0xC0C20017}, 25ff9112dfSStefan Roese /*4 */ 26ff9112dfSStefan Roese {0x000016A0, 0xC1020113}, 27ff9112dfSStefan Roese /*5 */ 28ff9112dfSStefan Roese {0x000016A0, 0xC1420107}, 29ff9112dfSStefan Roese /*6 */ 30ff9112dfSStefan Roese {0x000016A0, 0xC182011F}, 31ff9112dfSStefan Roese /*7 */ 32ff9112dfSStefan Roese {0x000016A0, 0xC1C2001C}, 33ff9112dfSStefan Roese /*8 */ 34ff9112dfSStefan Roese {0x000016A0, 0xC202010D}, 35ff9112dfSStefan Roese 36ff9112dfSStefan Roese /* Write Leveling */ 37ff9112dfSStefan Roese /*0 */ 38ff9112dfSStefan Roese {0x000016A0, 0xC0004A06}, 39ff9112dfSStefan Roese /*1 */ 40ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 41ff9112dfSStefan Roese /*2 */ 42ff9112dfSStefan Roese {0x000016A0, 0xC0806A0D}, 43ff9112dfSStefan Roese /*3 */ 44ff9112dfSStefan Roese {0x000016A0, 0xC0C0A01B}, 45ff9112dfSStefan Roese /*4 */ 46ff9112dfSStefan Roese {0x000016A0, 0xC1003A01}, 47ff9112dfSStefan Roese /*5 */ 48ff9112dfSStefan Roese {0x000016A0, 0xC1408113}, 49ff9112dfSStefan Roese /*6 */ 50ff9112dfSStefan Roese {0x000016A0, 0xC1805609}, 51ff9112dfSStefan Roese /*7 */ 52ff9112dfSStefan Roese {0x000016A0, 0xC1C04504}, 53ff9112dfSStefan Roese /*8 */ 54ff9112dfSStefan Roese {0x000016A0, 0xC2009518}, 55ff9112dfSStefan Roese 56ff9112dfSStefan Roese /*center DQS on read cycle */ 57ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 58ff9112dfSStefan Roese 59ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 60ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 61ff9112dfSStefan Roese 62ff9112dfSStefan Roese /*init DRAM */ 63ff9112dfSStefan Roese {0x00001480, 0x00000001}, 64ff9112dfSStefan Roese {0x0, 0x0} 65ff9112dfSStefan Roese }; 66ff9112dfSStefan Roese 67ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = { 68ff9112dfSStefan Roese /* Read Leveling */ 69ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 70ff9112dfSStefan Roese /*0 */ 71ff9112dfSStefan Roese {0x000016A0, 0xC0020301}, 72ff9112dfSStefan Roese /*1 */ 73ff9112dfSStefan Roese {0x000016A0, 0xC0420202}, 74ff9112dfSStefan Roese /*2 */ 75ff9112dfSStefan Roese {0x000016A0, 0xC0820314}, 76ff9112dfSStefan Roese /*3 */ 77ff9112dfSStefan Roese {0x000016A0, 0xC0C20117}, 78ff9112dfSStefan Roese /*4 */ 79ff9112dfSStefan Roese {0x000016A0, 0xC1020219}, 80ff9112dfSStefan Roese /*5 */ 81ff9112dfSStefan Roese {0x000016A0, 0xC142020B}, 82ff9112dfSStefan Roese /*6 */ 83ff9112dfSStefan Roese {0x000016A0, 0xC182030A}, 84ff9112dfSStefan Roese /*7 */ 85ff9112dfSStefan Roese {0x000016A0, 0xC1C2011D}, 86ff9112dfSStefan Roese /*8 */ 87ff9112dfSStefan Roese {0x000016A0, 0xC2020212}, 88ff9112dfSStefan Roese 89ff9112dfSStefan Roese /* Write Leveling */ 90ff9112dfSStefan Roese /*0 */ 91ff9112dfSStefan Roese {0x000016A0, 0xC0007A12}, 92ff9112dfSStefan Roese /*1 */ 93ff9112dfSStefan Roese {0x000016A0, 0xC0408D16}, 94ff9112dfSStefan Roese /*2 */ 95ff9112dfSStefan Roese {0x000016A0, 0xC0809E1B}, 96ff9112dfSStefan Roese /*3 */ 97ff9112dfSStefan Roese {0x000016A0, 0xC0C0AC1F}, 98ff9112dfSStefan Roese /*4 */ 99ff9112dfSStefan Roese {0x000016A0, 0xC1005E0A}, 100ff9112dfSStefan Roese /*5 */ 101ff9112dfSStefan Roese {0x000016A0, 0xC140A91D}, 102ff9112dfSStefan Roese /*6 */ 103ff9112dfSStefan Roese {0x000016A0, 0xC1808E17}, 104ff9112dfSStefan Roese /*7 */ 105ff9112dfSStefan Roese {0x000016A0, 0xC1C05509}, 106ff9112dfSStefan Roese /*8 */ 107ff9112dfSStefan Roese {0x000016A0, 0xC2003A01}, 108ff9112dfSStefan Roese 109ff9112dfSStefan Roese /* PBS Leveling */ 110ff9112dfSStefan Roese /*0 */ 111ff9112dfSStefan Roese {0x000016A0, 0xC0007A12}, 112ff9112dfSStefan Roese /*1 */ 113ff9112dfSStefan Roese {0x000016A0, 0xC0408D16}, 114ff9112dfSStefan Roese /*2 */ 115ff9112dfSStefan Roese {0x000016A0, 0xC0809E1B}, 116ff9112dfSStefan Roese /*3 */ 117ff9112dfSStefan Roese {0x000016A0, 0xC0C0AC1F}, 118ff9112dfSStefan Roese /*4 */ 119ff9112dfSStefan Roese {0x000016A0, 0xC1005E0A}, 120ff9112dfSStefan Roese /*5 */ 121ff9112dfSStefan Roese {0x000016A0, 0xC140A91D}, 122ff9112dfSStefan Roese /*6 */ 123ff9112dfSStefan Roese {0x000016A0, 0xC1808E17}, 124ff9112dfSStefan Roese /*7 */ 125ff9112dfSStefan Roese {0x000016A0, 0xC1C05509}, 126ff9112dfSStefan Roese /*8 */ 127ff9112dfSStefan Roese {0x000016A0, 0xC2003A01}, 128ff9112dfSStefan Roese 129ff9112dfSStefan Roese /*center DQS on read cycle */ 130ff9112dfSStefan Roese {0x000016A0, 0xC803000B}, 131ff9112dfSStefan Roese 132ff9112dfSStefan Roese {0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */ 133ff9112dfSStefan Roese {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */ 134ff9112dfSStefan Roese 135ff9112dfSStefan Roese /*init DRAM */ 136ff9112dfSStefan Roese {0x00001480, 0x00000001}, 137ff9112dfSStefan Roese {0x0, 0x0} 138ff9112dfSStefan Roese }; 139ff9112dfSStefan Roese 140ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = { 141ff9112dfSStefan Roese /* Read Leveling */ 142ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 143ff9112dfSStefan Roese /*0 2 4 15 */ 144ff9112dfSStefan Roese {0x000016A0, 0xC002010C}, 145ff9112dfSStefan Roese /*1 2 4 2 */ 146ff9112dfSStefan Roese {0x000016A0, 0xC042001C}, 147ff9112dfSStefan Roese /*2 2 4 27 */ 148ff9112dfSStefan Roese {0x000016A0, 0xC0820115}, 149ff9112dfSStefan Roese /*3 2 4 0 */ 150ff9112dfSStefan Roese {0x000016A0, 0xC0C20019}, 151ff9112dfSStefan Roese /*4 2 4 13 */ 152ff9112dfSStefan Roese {0x000016A0, 0xC1020108}, 153ff9112dfSStefan Roese /*5 2 4 5 */ 154ff9112dfSStefan Roese {0x000016A0, 0xC1420100}, 155ff9112dfSStefan Roese /*6 2 4 19 */ 156ff9112dfSStefan Roese {0x000016A0, 0xC1820111}, 157ff9112dfSStefan Roese /*7 2 4 0 */ 158ff9112dfSStefan Roese {0x000016A0, 0xC1C2001B}, 159ff9112dfSStefan Roese /*8 2 4 10 */ 160ff9112dfSStefan Roese /*{0x000016A0, 0xC2020117}, */ 161ff9112dfSStefan Roese {0x000016A0, 0xC202010C}, 162ff9112dfSStefan Roese 163ff9112dfSStefan Roese /* Write Leveling */ 164ff9112dfSStefan Roese /*0 */ 165ff9112dfSStefan Roese {0x000016A0, 0xC0005508}, 166ff9112dfSStefan Roese /*1 */ 167ff9112dfSStefan Roese {0x000016A0, 0xC0409819}, 168ff9112dfSStefan Roese /*2 */ 169ff9112dfSStefan Roese {0x000016A0, 0xC080650C}, 170ff9112dfSStefan Roese /*3 */ 171ff9112dfSStefan Roese {0x000016A0, 0xC0C0700F}, 172ff9112dfSStefan Roese /*4 */ 173ff9112dfSStefan Roese {0x000016A0, 0xC1004103}, 174ff9112dfSStefan Roese /*5 */ 175ff9112dfSStefan Roese {0x000016A0, 0xC140A81D}, 176ff9112dfSStefan Roese /*6 */ 177ff9112dfSStefan Roese {0x000016A0, 0xC180650C}, 178ff9112dfSStefan Roese /*7 */ 179ff9112dfSStefan Roese {0x000016A0, 0xC1C08013}, 180ff9112dfSStefan Roese /*8 */ 181ff9112dfSStefan Roese {0x000016A0, 0xC2005508}, 182ff9112dfSStefan Roese 183ff9112dfSStefan Roese /*center DQS on read cycle */ 184ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 185ff9112dfSStefan Roese 186ff9112dfSStefan Roese {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ 187ff9112dfSStefan Roese {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ 188ff9112dfSStefan Roese 189ff9112dfSStefan Roese /*init DRAM */ 190ff9112dfSStefan Roese {0x00001480, 0x00000001}, 191ff9112dfSStefan Roese {0x0, 0x0} 192ff9112dfSStefan Roese }; 193ff9112dfSStefan Roese 194ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = { 195ff9112dfSStefan Roese /* Read Leveling */ 196ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 197ff9112dfSStefan Roese /*0 2 4 15 */ 198ff9112dfSStefan Roese {0x000016A0, 0xC002040C}, 199ff9112dfSStefan Roese /*1 2 4 2 */ 200ff9112dfSStefan Roese {0x000016A0, 0xC0420117}, 201ff9112dfSStefan Roese /*2 2 4 27 */ 202ff9112dfSStefan Roese {0x000016A0, 0xC082041B}, 203ff9112dfSStefan Roese /*3 2 4 0 */ 204ff9112dfSStefan Roese {0x000016A0, 0xC0C20117}, 205ff9112dfSStefan Roese /*4 2 4 13 */ 206ff9112dfSStefan Roese {0x000016A0, 0xC102040A}, 207ff9112dfSStefan Roese /*5 2 4 5 */ 208ff9112dfSStefan Roese {0x000016A0, 0xC1420117}, 209ff9112dfSStefan Roese /*6 2 4 19 */ 210ff9112dfSStefan Roese {0x000016A0, 0xC1820419}, 211ff9112dfSStefan Roese /*7 2 4 0 */ 212ff9112dfSStefan Roese {0x000016A0, 0xC1C20117}, 213ff9112dfSStefan Roese /*8 2 4 10 */ 214ff9112dfSStefan Roese {0x000016A0, 0xC2020117}, 215ff9112dfSStefan Roese 216ff9112dfSStefan Roese /* Write Leveling */ 217ff9112dfSStefan Roese /*0 */ 218ff9112dfSStefan Roese {0x000016A0, 0xC0008113}, 219ff9112dfSStefan Roese /*1 */ 220ff9112dfSStefan Roese {0x000016A0, 0xC0404504}, 221ff9112dfSStefan Roese /*2 */ 222ff9112dfSStefan Roese {0x000016A0, 0xC0808514}, 223ff9112dfSStefan Roese /*3 */ 224ff9112dfSStefan Roese {0x000016A0, 0xC0C09418}, 225ff9112dfSStefan Roese /*4 */ 226ff9112dfSStefan Roese {0x000016A0, 0xC1006D0E}, 227ff9112dfSStefan Roese /*5 */ 228ff9112dfSStefan Roese {0x000016A0, 0xC1405508}, 229ff9112dfSStefan Roese /*6 */ 230ff9112dfSStefan Roese {0x000016A0, 0xC1807D12}, 231ff9112dfSStefan Roese /*7 */ 232ff9112dfSStefan Roese {0x000016A0, 0xC1C0b01F}, 233ff9112dfSStefan Roese /*8 */ 234ff9112dfSStefan Roese {0x000016A0, 0xC2005D0A}, 235ff9112dfSStefan Roese 236ff9112dfSStefan Roese /*center DQS on read cycle */ 237ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 238ff9112dfSStefan Roese 239ff9112dfSStefan Roese {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ 240ff9112dfSStefan Roese {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ 241ff9112dfSStefan Roese 242ff9112dfSStefan Roese /*init DRAM */ 243ff9112dfSStefan Roese {0x00001480, 0x00000001}, 244ff9112dfSStefan Roese {0x0, 0x0} 245ff9112dfSStefan Roese }; 246ff9112dfSStefan Roese 247ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = { 248ff9112dfSStefan Roese /* Read Leveling */ 249ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 250ff9112dfSStefan Roese /*0 2 3 1 */ 251ff9112dfSStefan Roese {0x000016A0, 0xC0020104}, 252ff9112dfSStefan Roese /*1 2 2 6 */ 253ff9112dfSStefan Roese {0x000016A0, 0xC0420010}, 254ff9112dfSStefan Roese /*2 2 3 16 */ 255ff9112dfSStefan Roese {0x000016A0, 0xC0820112}, 256ff9112dfSStefan Roese /*3 2 1 26 */ 257ff9112dfSStefan Roese {0x000016A0, 0xC0C20009}, 258ff9112dfSStefan Roese /*4 2 2 29 */ 259ff9112dfSStefan Roese {0x000016A0, 0xC102001F}, 260ff9112dfSStefan Roese /*5 2 2 13 */ 261ff9112dfSStefan Roese {0x000016A0, 0xC1420014}, 262ff9112dfSStefan Roese /*6 2 3 6 */ 263ff9112dfSStefan Roese {0x000016A0, 0xC1820109}, 264ff9112dfSStefan Roese /*7 2 1 31 */ 265ff9112dfSStefan Roese {0x000016A0, 0xC1C2000C}, 266ff9112dfSStefan Roese /*8 2 2 22 */ 267ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 268ff9112dfSStefan Roese 269ff9112dfSStefan Roese /* Write Leveling */ 270ff9112dfSStefan Roese /*0 */ 271ff9112dfSStefan Roese {0x000016A0, 0xC0009919}, 272ff9112dfSStefan Roese /*1 */ 273ff9112dfSStefan Roese {0x000016A0, 0xC0405508}, 274ff9112dfSStefan Roese /*2 */ 275ff9112dfSStefan Roese {0x000016A0, 0xC0809919}, 276ff9112dfSStefan Roese /*3 */ 277ff9112dfSStefan Roese {0x000016A0, 0xC0C09C1A}, 278ff9112dfSStefan Roese /*4 */ 279ff9112dfSStefan Roese {0x000016A0, 0xC1008113}, 280ff9112dfSStefan Roese /*5 */ 281ff9112dfSStefan Roese {0x000016A0, 0xC140650C}, 282ff9112dfSStefan Roese /*6 */ 283ff9112dfSStefan Roese {0x000016A0, 0xC1809518}, 284ff9112dfSStefan Roese /*7 */ 285ff9112dfSStefan Roese {0x000016A0, 0xC1C04103}, 286ff9112dfSStefan Roese /*8 */ 287ff9112dfSStefan Roese {0x000016A0, 0xC2006D0E}, 288ff9112dfSStefan Roese 289ff9112dfSStefan Roese /*center DQS on read cycle */ 290ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 291ff9112dfSStefan Roese 292ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 293ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 294ff9112dfSStefan Roese /*init DRAM */ 295ff9112dfSStefan Roese {0x00001480, 0x00000001}, 296ff9112dfSStefan Roese {0x0, 0x0} 297ff9112dfSStefan Roese }; 298ff9112dfSStefan Roese 299ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = { 300ff9112dfSStefan Roese 301ff9112dfSStefan Roese /* Read Leveling */ 302ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 303ff9112dfSStefan Roese /*0 2 3 1 */ 304ff9112dfSStefan Roese {0x000016A0, 0xC0020103}, 305ff9112dfSStefan Roese /*1 2 2 6 */ 306ff9112dfSStefan Roese {0x000016A0, 0xC0420012}, 307ff9112dfSStefan Roese /*2 2 3 16 */ 308ff9112dfSStefan Roese {0x000016A0, 0xC0820113}, 309ff9112dfSStefan Roese /*3 2 1 26 */ 310ff9112dfSStefan Roese {0x000016A0, 0xC0C20012}, 311ff9112dfSStefan Roese /*4 2 2 29 */ 312ff9112dfSStefan Roese {0x000016A0, 0xC1020100}, 313ff9112dfSStefan Roese /*5 2 2 13 */ 314ff9112dfSStefan Roese {0x000016A0, 0xC1420016}, 315ff9112dfSStefan Roese /*6 2 3 6 */ 316ff9112dfSStefan Roese {0x000016A0, 0xC1820109}, 317ff9112dfSStefan Roese /*7 2 1 31 */ 318ff9112dfSStefan Roese {0x000016A0, 0xC1C20010}, 319ff9112dfSStefan Roese /*8 2 2 22 */ 320ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 321ff9112dfSStefan Roese 322ff9112dfSStefan Roese /* Write Leveling */ 323ff9112dfSStefan Roese /*0 */ 324ff9112dfSStefan Roese {0x000016A0, 0xC000b11F}, 325ff9112dfSStefan Roese /*1 */ 326ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 327ff9112dfSStefan Roese /*2 */ 328ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 329ff9112dfSStefan Roese /*3 */ 330ff9112dfSStefan Roese {0x000016A0, 0xC0C0a81D}, 331ff9112dfSStefan Roese /*4 */ 332ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 333ff9112dfSStefan Roese /*5 */ 334ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 335ff9112dfSStefan Roese /*6 */ 336ff9112dfSStefan Roese {0x000016A0, 0xC180ad1e}, 337ff9112dfSStefan Roese /*7 */ 338ff9112dfSStefan Roese {0x000016A0, 0xC1C04d06}, 339ff9112dfSStefan Roese /*8 */ 340ff9112dfSStefan Roese {0x000016A0, 0xC2008514}, 341ff9112dfSStefan Roese 342ff9112dfSStefan Roese /*center DQS on read cycle */ 343ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 344ff9112dfSStefan Roese 345ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 346ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 347ff9112dfSStefan Roese 348ff9112dfSStefan Roese /*init DRAM */ 349ff9112dfSStefan Roese {0x00001480, 0x00000001}, 350ff9112dfSStefan Roese {0x0, 0x0} 351ff9112dfSStefan Roese }; 352ff9112dfSStefan Roese 353ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = { 354ff9112dfSStefan Roese 355ff9112dfSStefan Roese /* Read Leveling */ 356ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 357ff9112dfSStefan Roese /*0 2 3 1 */ 358ff9112dfSStefan Roese {0x000016A0, 0xC0020213}, 359ff9112dfSStefan Roese /*1 2 2 6 */ 360ff9112dfSStefan Roese {0x000016A0, 0xC0420108}, 361ff9112dfSStefan Roese /*2 2 3 16 */ 362ff9112dfSStefan Roese {0x000016A0, 0xC0820210}, 363ff9112dfSStefan Roese /*3 2 1 26 */ 364ff9112dfSStefan Roese {0x000016A0, 0xC0C20108}, 365ff9112dfSStefan Roese /*4 2 2 29 */ 366ff9112dfSStefan Roese {0x000016A0, 0xC102011A}, 367ff9112dfSStefan Roese /*5 2 2 13 */ 368ff9112dfSStefan Roese {0x000016A0, 0xC1420300}, 369ff9112dfSStefan Roese /*6 2 3 6 */ 370ff9112dfSStefan Roese {0x000016A0, 0xC1820204}, 371ff9112dfSStefan Roese /*7 2 1 31 */ 372ff9112dfSStefan Roese {0x000016A0, 0xC1C20106}, 373ff9112dfSStefan Roese /*8 2 2 22 */ 374ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 375ff9112dfSStefan Roese 376ff9112dfSStefan Roese /* Write Leveling */ 377ff9112dfSStefan Roese /*0 */ 378ff9112dfSStefan Roese {0x000016A0, 0xC000620B}, 379ff9112dfSStefan Roese /*1 */ 380ff9112dfSStefan Roese {0x000016A0, 0xC0408D16}, 381ff9112dfSStefan Roese /*2 */ 382ff9112dfSStefan Roese {0x000016A0, 0xC0806A0D}, 383ff9112dfSStefan Roese /*3 */ 384ff9112dfSStefan Roese {0x000016A0, 0xC0C03D02}, 385ff9112dfSStefan Roese /*4 */ 386ff9112dfSStefan Roese {0x000016A0, 0xC1004a05}, 387ff9112dfSStefan Roese /*5 */ 388ff9112dfSStefan Roese {0x000016A0, 0xC140A11B}, 389ff9112dfSStefan Roese /*6 */ 390ff9112dfSStefan Roese {0x000016A0, 0xC1805E0A}, 391ff9112dfSStefan Roese /*7 */ 392ff9112dfSStefan Roese {0x000016A0, 0xC1C06D0E}, 393ff9112dfSStefan Roese /*8 */ 394ff9112dfSStefan Roese {0x000016A0, 0xC200AD1E}, 395ff9112dfSStefan Roese 396ff9112dfSStefan Roese /*center DQS on read cycle */ 397ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 398ff9112dfSStefan Roese 399ff9112dfSStefan Roese {0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */ 400ff9112dfSStefan Roese {0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */ 401ff9112dfSStefan Roese 402ff9112dfSStefan Roese /*init DRAM */ 403ff9112dfSStefan Roese {0x00001480, 0x00000001}, 404ff9112dfSStefan Roese {0x0, 0x0} 405ff9112dfSStefan Roese }; 406ff9112dfSStefan Roese 407ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = { 408ff9112dfSStefan Roese /* Read Leveling */ 409ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 410ff9112dfSStefan Roese /*0 */ 411ff9112dfSStefan Roese {0x000016A0, 0xC002010E}, 412ff9112dfSStefan Roese /*1 */ 413ff9112dfSStefan Roese {0x000016A0, 0xC042001E}, 414ff9112dfSStefan Roese /*2 */ 415ff9112dfSStefan Roese {0x000016A0, 0xC0820118}, 416ff9112dfSStefan Roese /*3 */ 417ff9112dfSStefan Roese {0x000016A0, 0xC0C2001E}, 418ff9112dfSStefan Roese /*4 */ 419ff9112dfSStefan Roese {0x000016A0, 0xC102010C}, 420ff9112dfSStefan Roese /*5 */ 421ff9112dfSStefan Roese {0x000016A0, 0xC1420102}, 422ff9112dfSStefan Roese /*6 */ 423ff9112dfSStefan Roese {0x000016A0, 0xC1820111}, 424ff9112dfSStefan Roese /*7 */ 425ff9112dfSStefan Roese {0x000016A0, 0xC1C2001C}, 426ff9112dfSStefan Roese /*8 */ 427ff9112dfSStefan Roese {0x000016A0, 0xC2020109}, 428ff9112dfSStefan Roese 429ff9112dfSStefan Roese /* Write Leveling */ 430ff9112dfSStefan Roese /*0 */ 431ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 432ff9112dfSStefan Roese /*1 */ 433ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 434ff9112dfSStefan Roese /*2 */ 435ff9112dfSStefan Roese {0x000016A0, 0xC0805207}, 436ff9112dfSStefan Roese /*3 */ 437ff9112dfSStefan Roese {0x000016A0, 0xC0C0A81D}, 438ff9112dfSStefan Roese /*4 */ 439ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 440ff9112dfSStefan Roese /*5 */ 441ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 442ff9112dfSStefan Roese /*6 */ 443ff9112dfSStefan Roese {0x000016A0, 0xC1803E02}, 444ff9112dfSStefan Roese /*7 */ 445ff9112dfSStefan Roese {0x000016A0, 0xC1C05107}, 446ff9112dfSStefan Roese /*8 */ 447ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 448ff9112dfSStefan Roese 449ff9112dfSStefan Roese /*center DQS on read cycle */ 450ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 451ff9112dfSStefan Roese 452ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 453ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 454ff9112dfSStefan Roese 455ff9112dfSStefan Roese /*init DRAM */ 456ff9112dfSStefan Roese {0x00001480, 0x00000001}, 457ff9112dfSStefan Roese {0x0, 0x0} 458ff9112dfSStefan Roese }; 459ff9112dfSStefan Roese 460ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = { 461ff9112dfSStefan Roese /* Read Leveling */ 462ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 463ff9112dfSStefan Roese /*0 */ 464ff9112dfSStefan Roese {0x000016A0, 0xC0020106}, 465ff9112dfSStefan Roese /*1 */ 466ff9112dfSStefan Roese {0x000016A0, 0xC0420016}, 467ff9112dfSStefan Roese /*2 */ 468ff9112dfSStefan Roese {0x000016A0, 0xC0820117}, 469ff9112dfSStefan Roese /*3 */ 470ff9112dfSStefan Roese {0x000016A0, 0xC0C2000F}, 471ff9112dfSStefan Roese /*4 */ 472ff9112dfSStefan Roese {0x000016A0, 0xC1020105}, 473ff9112dfSStefan Roese /*5 */ 474ff9112dfSStefan Roese {0x000016A0, 0xC142001B}, 475ff9112dfSStefan Roese /*6 */ 476ff9112dfSStefan Roese {0x000016A0, 0xC182010C}, 477ff9112dfSStefan Roese /*7 */ 478ff9112dfSStefan Roese {0x000016A0, 0xC1C20011}, 479ff9112dfSStefan Roese /*8 */ 480ff9112dfSStefan Roese {0x000016A0, 0xC2020101}, 481ff9112dfSStefan Roese 482ff9112dfSStefan Roese /* Write Leveling */ 483ff9112dfSStefan Roese /*0 */ 484ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 485ff9112dfSStefan Roese /*1 */ 486ff9112dfSStefan Roese {0x000016A0, 0xC0406D0E}, 487ff9112dfSStefan Roese /*2 */ 488ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 489ff9112dfSStefan Roese /*3 */ 490ff9112dfSStefan Roese {0x000016A0, 0xC0C04504}, 491ff9112dfSStefan Roese /*4 */ 492ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 493ff9112dfSStefan Roese /*5 */ 494ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 495ff9112dfSStefan Roese /*6 */ 496ff9112dfSStefan Roese {0x000016A0, 0xC1803600}, 497ff9112dfSStefan Roese /*7 */ 498ff9112dfSStefan Roese {0x000016A0, 0xC1C0610B}, 499ff9112dfSStefan Roese /*8 */ 500ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 501ff9112dfSStefan Roese 502ff9112dfSStefan Roese /*center DQS on read cycle */ 503ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 504ff9112dfSStefan Roese 505ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 506ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 507ff9112dfSStefan Roese 508ff9112dfSStefan Roese /*init DRAM */ 509ff9112dfSStefan Roese {0x00001480, 0x00000001}, 510ff9112dfSStefan Roese {0x0, 0x0} 511ff9112dfSStefan Roese }; 512ff9112dfSStefan Roese 513ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = { 514ff9112dfSStefan Roese /* Read Leveling */ 515ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 516ff9112dfSStefan Roese /*0 */ 517ff9112dfSStefan Roese {0x000016A0, 0xC002010C}, 518ff9112dfSStefan Roese /*1 */ 519ff9112dfSStefan Roese {0x000016A0, 0xC042001B}, 520ff9112dfSStefan Roese /*2 */ 521ff9112dfSStefan Roese {0x000016A0, 0xC082011D}, 522ff9112dfSStefan Roese /*3 */ 523ff9112dfSStefan Roese {0x000016A0, 0xC0C20015}, 524ff9112dfSStefan Roese /*4 */ 525ff9112dfSStefan Roese {0x000016A0, 0xC102010B}, 526ff9112dfSStefan Roese /*5 */ 527ff9112dfSStefan Roese {0x000016A0, 0xC1420101}, 528ff9112dfSStefan Roese /*6 */ 529ff9112dfSStefan Roese {0x000016A0, 0xC1820113}, 530ff9112dfSStefan Roese /*7 */ 531ff9112dfSStefan Roese {0x000016A0, 0xC1C20017}, 532ff9112dfSStefan Roese /*8 */ 533ff9112dfSStefan Roese {0x000016A0, 0xC2020107}, 534ff9112dfSStefan Roese 535ff9112dfSStefan Roese /* Write Leveling */ 536ff9112dfSStefan Roese /*0 */ 537ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 538ff9112dfSStefan Roese /*1 */ 539ff9112dfSStefan Roese {0x000016A0, 0xC0406D0E}, 540ff9112dfSStefan Roese /*2 */ 541ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 542ff9112dfSStefan Roese /*3 */ 543ff9112dfSStefan Roese {0x000016A0, 0xC0C04504}, 544ff9112dfSStefan Roese /*4 */ 545ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 546ff9112dfSStefan Roese /*5 */ 547ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 548ff9112dfSStefan Roese /*6 */ 549ff9112dfSStefan Roese {0x000016A0, 0xC180B11F}, 550ff9112dfSStefan Roese /*7 */ 551ff9112dfSStefan Roese {0x000016A0, 0xC1C0610B}, 552ff9112dfSStefan Roese /*8 */ 553ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 554ff9112dfSStefan Roese 555ff9112dfSStefan Roese /*center DQS on read cycle */ 556ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 557ff9112dfSStefan Roese 558ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 559ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 560ff9112dfSStefan Roese 561ff9112dfSStefan Roese /*init DRAM */ 562ff9112dfSStefan Roese {0x00001480, 0x00000001}, 563ff9112dfSStefan Roese {0x0, 0x0} 564ff9112dfSStefan Roese }; 565ff9112dfSStefan Roese 566ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = { 567ff9112dfSStefan Roese /* Read Leveling */ 568ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 569ff9112dfSStefan Roese /* CS 0 */ 570ff9112dfSStefan Roese /*0 2 3 1 */ 571ff9112dfSStefan Roese {0x000016A0, 0xC0020103}, 572ff9112dfSStefan Roese /*1 2 2 6 */ 573ff9112dfSStefan Roese {0x000016A0, 0xC0420012}, 574ff9112dfSStefan Roese /*2 2 3 16 */ 575ff9112dfSStefan Roese {0x000016A0, 0xC0820113}, 576ff9112dfSStefan Roese /*3 2 1 26 */ 577ff9112dfSStefan Roese {0x000016A0, 0xC0C20012}, 578ff9112dfSStefan Roese /*4 2 2 29 */ 579ff9112dfSStefan Roese {0x000016A0, 0xC1020100}, 580ff9112dfSStefan Roese /*5 2 2 13 */ 581ff9112dfSStefan Roese {0x000016A0, 0xC1420016}, 582ff9112dfSStefan Roese /*6 2 3 6 */ 583ff9112dfSStefan Roese {0x000016A0, 0xC1820109}, 584ff9112dfSStefan Roese /*7 2 1 31 */ 585ff9112dfSStefan Roese {0x000016A0, 0xC1C20010}, 586ff9112dfSStefan Roese /*8 2 2 22 */ 587ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 588ff9112dfSStefan Roese 589ff9112dfSStefan Roese /* Write Leveling */ 590ff9112dfSStefan Roese /*0 */ 591ff9112dfSStefan Roese {0x000016A0, 0xC000b11F}, 592ff9112dfSStefan Roese /*1 */ 593ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 594ff9112dfSStefan Roese /*2 */ 595ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 596ff9112dfSStefan Roese /*3 */ 597ff9112dfSStefan Roese {0x000016A0, 0xC0C0a81D}, 598ff9112dfSStefan Roese /*4 */ 599ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 600ff9112dfSStefan Roese /*5 */ 601ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 602ff9112dfSStefan Roese /*6 */ 603ff9112dfSStefan Roese {0x000016A0, 0xC180ad1e}, 604ff9112dfSStefan Roese /*7 */ 605ff9112dfSStefan Roese {0x000016A0, 0xC1C04d06}, 606ff9112dfSStefan Roese /*8 */ 607ff9112dfSStefan Roese {0x000016A0, 0xC2008514}, 608ff9112dfSStefan Roese 609ff9112dfSStefan Roese /*center DQS on read cycle */ 610ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 611ff9112dfSStefan Roese 612ff9112dfSStefan Roese /* CS 1 */ 613ff9112dfSStefan Roese 614ff9112dfSStefan Roese {0x000016A0, 0xC0060103}, 615ff9112dfSStefan Roese /*1 2 2 6 */ 616ff9112dfSStefan Roese {0x000016A0, 0xC0460012}, 617ff9112dfSStefan Roese /*2 2 3 16 */ 618ff9112dfSStefan Roese {0x000016A0, 0xC0860113}, 619ff9112dfSStefan Roese /*3 2 1 26 */ 620ff9112dfSStefan Roese {0x000016A0, 0xC0C60012}, 621ff9112dfSStefan Roese /*4 2 2 29 */ 622ff9112dfSStefan Roese {0x000016A0, 0xC1060100}, 623ff9112dfSStefan Roese /*5 2 2 13 */ 624ff9112dfSStefan Roese {0x000016A0, 0xC1460016}, 625ff9112dfSStefan Roese /*6 2 3 6 */ 626ff9112dfSStefan Roese {0x000016A0, 0xC1860109}, 627ff9112dfSStefan Roese /*7 2 1 31 */ 628ff9112dfSStefan Roese {0x000016A0, 0xC1C60010}, 629ff9112dfSStefan Roese /*8 2 2 22 */ 630ff9112dfSStefan Roese {0x000016A0, 0xC2060112}, 631ff9112dfSStefan Roese 632ff9112dfSStefan Roese /* Write Leveling */ 633ff9112dfSStefan Roese /*0 */ 634ff9112dfSStefan Roese {0x000016A0, 0xC004b11F}, 635ff9112dfSStefan Roese /*1 */ 636ff9112dfSStefan Roese {0x000016A0, 0xC044690D}, 637ff9112dfSStefan Roese /*2 */ 638ff9112dfSStefan Roese {0x000016A0, 0xC0843600}, 639ff9112dfSStefan Roese /*3 */ 640ff9112dfSStefan Roese {0x000016A0, 0xC0C4a81D}, 641ff9112dfSStefan Roese /*4 */ 642ff9112dfSStefan Roese {0x000016A0, 0xC1049919}, 643ff9112dfSStefan Roese /*5 */ 644ff9112dfSStefan Roese {0x000016A0, 0xC1447911}, 645ff9112dfSStefan Roese /*6 */ 646ff9112dfSStefan Roese {0x000016A0, 0xC184ad1e}, 647ff9112dfSStefan Roese /*7 */ 648ff9112dfSStefan Roese {0x000016A0, 0xC1C44d06}, 649ff9112dfSStefan Roese /*8 */ 650ff9112dfSStefan Roese {0x000016A0, 0xC2048514}, 651ff9112dfSStefan Roese 652ff9112dfSStefan Roese /*center DQS on read cycle */ 653ff9112dfSStefan Roese {0x000016A0, 0xC807000F}, 654ff9112dfSStefan Roese 655ff9112dfSStefan Roese /* Both CS */ 656ff9112dfSStefan Roese 657ff9112dfSStefan Roese {0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */ 658ff9112dfSStefan Roese {0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */ 659ff9112dfSStefan Roese 660ff9112dfSStefan Roese /*init DRAM */ 661ff9112dfSStefan Roese {0x00001480, 0x00000001}, 662ff9112dfSStefan Roese {0x0, 0x0} 663ff9112dfSStefan Roese }; 664ff9112dfSStefan Roese 665ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = { 666ff9112dfSStefan Roese /* Read Leveling */ 667ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 668ff9112dfSStefan Roese /*0 */ 669ff9112dfSStefan Roese {0x000016A0, 0xC0020118}, 670ff9112dfSStefan Roese /*1 */ 671ff9112dfSStefan Roese {0x000016A0, 0xC0420108}, 672ff9112dfSStefan Roese /*2 */ 673ff9112dfSStefan Roese {0x000016A0, 0xC0820202}, 674ff9112dfSStefan Roese /*3 */ 675ff9112dfSStefan Roese {0x000016A0, 0xC0C20108}, 676ff9112dfSStefan Roese /*4 */ 677ff9112dfSStefan Roese {0x000016A0, 0xC1020117}, 678ff9112dfSStefan Roese /*5 */ 679ff9112dfSStefan Roese {0x000016A0, 0xC142010C}, 680ff9112dfSStefan Roese /*6 */ 681ff9112dfSStefan Roese {0x000016A0, 0xC182011B}, 682ff9112dfSStefan Roese /*7 */ 683ff9112dfSStefan Roese {0x000016A0, 0xC1C20107}, 684ff9112dfSStefan Roese /*8 */ 685ff9112dfSStefan Roese {0x000016A0, 0xC2020113}, 686ff9112dfSStefan Roese 687ff9112dfSStefan Roese /* Write Leveling */ 688ff9112dfSStefan Roese /*0 */ 689ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 690ff9112dfSStefan Roese /*1 */ 691ff9112dfSStefan Roese {0x000016A0, 0xC0406D0E}, 692ff9112dfSStefan Roese /*2 */ 693ff9112dfSStefan Roese {0x000016A0, 0xC0805207}, 694ff9112dfSStefan Roese /*3 */ 695ff9112dfSStefan Roese {0x000016A0, 0xC0C0A81D}, 696ff9112dfSStefan Roese /*4 */ 697ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 698ff9112dfSStefan Roese /*5 */ 699ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 700ff9112dfSStefan Roese /*6 */ 701ff9112dfSStefan Roese {0x000016A0, 0xC1803E02}, 702ff9112dfSStefan Roese /*7 */ 703ff9112dfSStefan Roese {0x000016A0, 0xC1C04D06}, 704ff9112dfSStefan Roese /*8 */ 705ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 706ff9112dfSStefan Roese 707ff9112dfSStefan Roese /*center DQS on read cycle */ 708ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 709ff9112dfSStefan Roese 710ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 711ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 712ff9112dfSStefan Roese 713ff9112dfSStefan Roese /*init DRAM */ 714ff9112dfSStefan Roese {0x00001480, 0x00000001}, 715ff9112dfSStefan Roese {0x0, 0x0} 716ff9112dfSStefan Roese }; 717ff9112dfSStefan Roese 718ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = { 719ff9112dfSStefan Roese /* Read Leveling */ 720ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 721ff9112dfSStefan Roese /*0 */ 722ff9112dfSStefan Roese {0x000016A0, 0xC0020404}, 723ff9112dfSStefan Roese /* 1 2 2 6 */ 724ff9112dfSStefan Roese {0x000016A0, 0xC042031E}, 725ff9112dfSStefan Roese /* 2 2 3 16 */ 726ff9112dfSStefan Roese {0x000016A0, 0xC0820411}, 727ff9112dfSStefan Roese /* 3 2 1 26 */ 728ff9112dfSStefan Roese {0x000016A0, 0xC0C20400}, 729ff9112dfSStefan Roese /* 4 2 2 29 */ 730ff9112dfSStefan Roese {0x000016A0, 0xC1020404}, 731ff9112dfSStefan Roese /* 5 2 2 13 */ 732ff9112dfSStefan Roese {0x000016A0, 0xC142031D}, 733ff9112dfSStefan Roese /* 6 2 3 6 */ 734ff9112dfSStefan Roese {0x000016A0, 0xC182040C}, 735ff9112dfSStefan Roese /* 7 2 1 31 */ 736ff9112dfSStefan Roese {0x000016A0, 0xC1C2031B}, 737ff9112dfSStefan Roese /* 8 2 2 22 */ 738ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 739ff9112dfSStefan Roese 740ff9112dfSStefan Roese /* Write Leveling */ 741ff9112dfSStefan Roese /* 0 */ 742ff9112dfSStefan Roese {0x000016A0, 0xC0004905}, 743ff9112dfSStefan Roese /* 1 */ 744ff9112dfSStefan Roese {0x000016A0, 0xC040A81D}, 745ff9112dfSStefan Roese /* 2 */ 746ff9112dfSStefan Roese {0x000016A0, 0xC0804504}, 747ff9112dfSStefan Roese /* 3 */ 748ff9112dfSStefan Roese {0x000016A0, 0xC0C08013}, 749ff9112dfSStefan Roese /* 4 */ 750ff9112dfSStefan Roese {0x000016A0, 0xC1004504}, 751ff9112dfSStefan Roese /* 5 */ 752ff9112dfSStefan Roese {0x000016A0, 0xC140A81D}, 753ff9112dfSStefan Roese /* 6 */ 754ff9112dfSStefan Roese {0x000016A0, 0xC1805909}, 755ff9112dfSStefan Roese /* 7 */ 756ff9112dfSStefan Roese {0x000016A0, 0xC1C09418}, 757ff9112dfSStefan Roese /* 8 */ 758ff9112dfSStefan Roese {0x000016A0, 0xC2006D0E}, 759ff9112dfSStefan Roese 760ff9112dfSStefan Roese /*center DQS on read cycle */ 761ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 762ff9112dfSStefan Roese {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ 763ff9112dfSStefan Roese {0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */ 764ff9112dfSStefan Roese /* init DRAM */ 765ff9112dfSStefan Roese {0x00001480, 0x00000001}, 766ff9112dfSStefan Roese {0x0, 0x0} 767ff9112dfSStefan Roese }; 768ff9112dfSStefan Roese 769ff9112dfSStefan Roese #endif /* __AXP_TRAINING_STATIC_H */ 770