1*83d290c5STom Rini# SPDX-License-Identifier: GPL-2.0+ 2f214a20eSMichael Walle# 3f214a20eSMichael Walle# Copyright (c) 2012 Michael Walle 4f214a20eSMichael Walle# Michael Walle <michael@walle.cc> 5b1e6c4c3SAnatolij Gustschin# Refer doc/README.kwbimage for more details about how-to configure 6f214a20eSMichael Walle# and create kirkwood boot image 7f214a20eSMichael Walle# 8f214a20eSMichael Walle 9f214a20eSMichael Walle# Boot Media configurations 10f214a20eSMichael WalleBOOT_FROM spi 11f214a20eSMichael Walle 12f214a20eSMichael Walle# SOC registers configuration using bootrom header extension 13f214a20eSMichael Walle# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 14f214a20eSMichael Walle 15f214a20eSMichael Walle# Configure RGMII-0/1 interface pad voltage to 1.8V 16f214a20eSMichael WalleDATA 0xFFD100E0 0x1B1B9B9B 17f214a20eSMichael Walle 18f214a20eSMichael Walle# L2 RAM Timing 0 19f214a20eSMichael WalleDATA 0xFFD20134 0xBBBBBBBB 20f214a20eSMichael Walle# not further specified in HW manual, timing taken from original vendor port 21f214a20eSMichael Walle 22f214a20eSMichael Walle# L2 RAM Timing 1 23f214a20eSMichael WalleDATA 0xFFD20138 0x00BBBBBB 24f214a20eSMichael Walle# not further specified in HW manual, timing taken from original vendor port 25f214a20eSMichael Walle 26f214a20eSMichael Walle# DDR Configuration register 27f214a20eSMichael WalleDATA 0xFFD01400 0x43000618 28f214a20eSMichael Walle# bit13-0: 0x618, 1560 DDR2 clks refresh rate 29f214a20eSMichael Walle# bit23-14: 0 required 30f214a20eSMichael Walle# bit24: 1, enable exit self refresh mode on DDR access 31f214a20eSMichael Walle# bit25: 1 required 32f214a20eSMichael Walle# bit29-26: 0 required 33f214a20eSMichael Walle# bit31-30: 0b01 required 34f214a20eSMichael Walle 35f214a20eSMichael Walle# DDR Controller Control Low 36f214a20eSMichael WalleDATA 0xFFD01404 0x39543010 37f214a20eSMichael Walle# bit3-0: 0 required 38f214a20eSMichael Walle# bit4: 1, T2 mode, addr/cmd are driven for two cycles 39f214a20eSMichael Walle# bit5: 0, clk is driven during self refresh, we don't care for APX 40f214a20eSMichael Walle# bit6: 0, use recommended falling edge of clk for addr/cmd 41f214a20eSMichael Walle# bit11-7: 0 required 42f214a20eSMichael Walle# bit12: 1 required 43f214a20eSMichael Walle# bit13: 1 required 44f214a20eSMichael Walle# bit14: 0, input buffer always powered up 45f214a20eSMichael Walle# bit17-15: 0 required 46f214a20eSMichael Walle# bit18: 1, cpu lock transaction enabled 47f214a20eSMichael Walle# bit19: 0 required 48f214a20eSMichael Walle# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 49f214a20eSMichael Walle# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 50f214a20eSMichael Walle# bit30-28: 3 required 51f214a20eSMichael Walle# bit31: 0, no additional STARTBURST delay 52f214a20eSMichael Walle 53f214a20eSMichael Walle# DDR Timing (Low) 54f214a20eSMichael WalleDATA 0xFFD01408 0x22125441 55f214a20eSMichael Walle# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) 56f214a20eSMichael Walle# bit7-4: 4, 5 cycle tRCD 57f214a20eSMichael Walle# bit11-8: 4, 5 cyle tRP 58f214a20eSMichael Walle# bit15-12: 5, 6 cyle tWR 59f214a20eSMichael Walle# bit19-16: 2, 3 cyle tWTR 60f214a20eSMichael Walle# bit20: 1, 18 cycle tRAS (tRAS[4]) 61f214a20eSMichael Walle# bit23-21: 0 required 62f214a20eSMichael Walle# bit27-24: 2, 3 cycle tRRD 63f214a20eSMichael Walle# bit31-28: 2, 3 cyle tRTP 64f214a20eSMichael Walle 65f214a20eSMichael Walle# DDR Timing (High) 66f214a20eSMichael WalleDATA 0xFFD0140C 0x00000832 67f214a20eSMichael Walle# bit6-0: 0x32, 50 cycle tRFC 68f214a20eSMichael Walle# bit8-7: 0, 1 cycle tR2R 69f214a20eSMichael Walle# bit10-9: 0, 1 cyle tR2W 70f214a20eSMichael Walle# bit12-11: 1, 2 cylce tW2W 71f214a20eSMichael Walle# bit31-13: 0 required 72f214a20eSMichael Walle 73f214a20eSMichael Walle# DDR Address Control 74f214a20eSMichael WalleDATA 0xFFD01410 0x0000000C 75f214a20eSMichael Walle# bit1-0: 0, Cs0width=x8 76f214a20eSMichael Walle# bit3-2: 3, Cs0size=1Gbit 77f214a20eSMichael Walle# bit5-4: 0, Cs1width=nonexistent 78f214a20eSMichael Walle# bit7-6: 0, Cs1size=nonexistent 79f214a20eSMichael Walle# bit9-8: 0, Cs2width=nonexistent 80f214a20eSMichael Walle# bit11-10: 0, Cs2size=nonexistent 81f214a20eSMichael Walle# bit13-12: 0, Cs3width=nonexistent 82f214a20eSMichael Walle# bit15-14: 0, Cs3size=nonexistent 83f214a20eSMichael Walle# bit16: 0, Cs0AddrSel 84f214a20eSMichael Walle# bit17: 0, Cs1AddrSel 85f214a20eSMichael Walle# bit18: 0, Cs2AddrSel 86f214a20eSMichael Walle# bit19: 0, Cs3AddrSel 87f214a20eSMichael Walle# bit31-20: 0 required 88f214a20eSMichael Walle 89f214a20eSMichael Walle# DDR Open Pages Control 90f214a20eSMichael WalleDATA 0xFFD01414 0x00000000 91f214a20eSMichael Walle# bit0: 0, OPEn=OpenPage enabled 92f214a20eSMichael Walle# bit31-1: 0 required 93f214a20eSMichael Walle 94f214a20eSMichael Walle# DDR Operation 95f214a20eSMichael WalleDATA 0xFFD01418 0x00000000 96f214a20eSMichael Walle# bit3-0: 0, Cmd=Normal SDRAM Mode 97f214a20eSMichael Walle# bit31-4: 0 required 98f214a20eSMichael Walle 99f214a20eSMichael Walle# DDR Mode 100f214a20eSMichael WalleDATA 0xFFD0141C 0x00000652 101f214a20eSMichael Walle# bit2-0: 2, Burst Length (2 required) 102f214a20eSMichael Walle# bit3: 0, Burst Type (0 required) 103f214a20eSMichael Walle# bit6-4: 5, CAS Latency (CL) 5 104f214a20eSMichael Walle# bit7: 0, (Test Mode) Normal operation 105f214a20eSMichael Walle# bit8: 0, (Reset DLL) Normal operation 106f214a20eSMichael Walle# bit11-9: 3, Write recovery for auto-precharge (3 required) 107f214a20eSMichael Walle# bit12: 0, Fast Active power down exit time (0 required) 108f214a20eSMichael Walle# bit31-13: 0 required 109f214a20eSMichael Walle 110f214a20eSMichael Walle# DDR Extended Mode 111f214a20eSMichael WalleDATA 0xFFD01420 0x00000006 112f214a20eSMichael Walle# bit0: 0, DRAM DLL enabled 113f214a20eSMichael Walle# bit1: 1, DRAM drive strength reduced 114f214a20eSMichael Walle# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) 115f214a20eSMichael Walle# bit5-3: 0 required 116f214a20eSMichael Walle# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) 117f214a20eSMichael Walle# bit9-7: 0 required 118f214a20eSMichael Walle# bit10: 0, differential DQS enabled 119f214a20eSMichael Walle# bit11: 0 required 120f214a20eSMichael Walle# bit12: 0, DRAM output buffer enabled 121f214a20eSMichael Walle# bit31-13: 0 required 122f214a20eSMichael Walle 123f214a20eSMichael Walle# DDR Controller Control High 124f214a20eSMichael WalleDATA 0xFFD01424 0x0000F17F 125f214a20eSMichael Walle# bit2-0: 0x7 required 126f214a20eSMichael Walle# bit3: 1, MBUS Burst Chop disabled 127f214a20eSMichael Walle# bit6-4: 0x7 required 128f214a20eSMichael Walle# bit7: 0 required (???) 129f214a20eSMichael Walle# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 130f214a20eSMichael Walle# bit9: 0, no half clock cycle addition to dataout 131f214a20eSMichael Walle# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 132f214a20eSMichael Walle# bit11: 0, 1/4 clock cycle skew disabled for write mesh 133f214a20eSMichael Walle# bit15-12: 0xf required 134f214a20eSMichael Walle# bit31-16: 0 required 135f214a20eSMichael Walle 136f214a20eSMichael Walle# DDR2 ODT Read Timing (default values) 137f214a20eSMichael WalleDATA 0xFFD01428 0x00085520 138f214a20eSMichael Walle# bit3-0: 0 required 139f214a20eSMichael Walle# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal 140f214a20eSMichael Walle# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal 141f214a20eSMichael Walle# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal 142f214a20eSMichael Walle# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 143f214a20eSMichael Walle# bit31-20: 0 required 144f214a20eSMichael Walle 145f214a20eSMichael Walle# DDR2 ODT Write Timing (default values) 146f214a20eSMichael WalleDATA 0xFFD0147C 0x00008552 147f214a20eSMichael Walle# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal 148f214a20eSMichael Walle# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal 149f214a20eSMichael Walle# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal 150f214a20eSMichael Walle# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 151f214a20eSMichael Walle# bit31-16: 0 required 152f214a20eSMichael Walle 153f214a20eSMichael Walle# CS[0]n Base address 154f214a20eSMichael WalleDATA 0xFFD01500 0x00000000 155f214a20eSMichael Walle# at 0x0 156f214a20eSMichael Walle 157f214a20eSMichael Walle# CS[0]n Size 158f214a20eSMichael WalleDATA 0xFFD01504 0x0FFFFFF1 159f214a20eSMichael Walle# bit0: 1, Window enabled 160f214a20eSMichael Walle# bit1: 0, Write Protect disabled 161f214a20eSMichael Walle# bit3-2: 0x0, CS0 hit selected 162f214a20eSMichael Walle# bit23-4: 0xfffff required 163f214a20eSMichael Walle# bit31-24: 0x0f, Size (i.e. 256MB) 164f214a20eSMichael Walle 165f214a20eSMichael Walle# CS[1]n Size 166f214a20eSMichael WalleDATA 0xFFD0150C 0x00000000 167f214a20eSMichael Walle# window disabled 168f214a20eSMichael Walle 169f214a20eSMichael Walle# CS[2]n Size 170f214a20eSMichael WalleDATA 0xFFD01514 0x00000000 171f214a20eSMichael Walle# window disabled 172f214a20eSMichael Walle 173f214a20eSMichael Walle# CS[3]n Size 174f214a20eSMichael WalleDATA 0xFFD0151C 0x00000000 175f214a20eSMichael Walle# window disabled 176f214a20eSMichael Walle 177f214a20eSMichael Walle# DDR ODT Control (Low) 178f214a20eSMichael WalleDATA 0xFFD01494 0x00010000 179f214a20eSMichael Walle# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM 180f214a20eSMichael Walle# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM 181f214a20eSMichael Walle# bit15-8: 0 required 182f214a20eSMichael Walle# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 183f214a20eSMichael Walle# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM 184f214a20eSMichael Walle# bit31-24: 0 required 185f214a20eSMichael Walle 186f214a20eSMichael Walle# DDR ODT Control (High) 187f214a20eSMichael WalleDATA 0xFFD01498 0x00000000 188f214a20eSMichael Walle# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register 189f214a20eSMichael Walle# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register 190f214a20eSMichael Walle# bit31-4 0 required 191f214a20eSMichael Walle 192f214a20eSMichael Walle# CPU ODT Control 193f214a20eSMichael WalleDATA 0xFFD0149C 0x0000E80F 194f214a20eSMichael Walle# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 195f214a20eSMichael Walle# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 196f214a20eSMichael Walle# bit9-8: 0, Internal ODT assertion is controlled by fiels 197f214a20eSMichael Walle# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm 198f214a20eSMichael Walle# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm 199f214a20eSMichael Walle# bit14: 1, M_STARTBURST_IN ODT enabled 200f214a20eSMichael Walle# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values 201f214a20eSMichael Walle# bit20-16: 0, Pad N channel driving strength for ODT 202f214a20eSMichael Walle# bit25-21: 0, Pad P channel driving strength for ODT 203f214a20eSMichael Walle# bit31-26: 0 required 204f214a20eSMichael Walle 205f214a20eSMichael Walle# DDR Initialization Control 206f214a20eSMichael WalleDATA 0xFFD01480 0x00000001 207f214a20eSMichael Walle# bit0: 1, enable DDR init upon this register write 208f214a20eSMichael Walle# bit31-1: 0, required 209f214a20eSMichael Walle 210f214a20eSMichael Walle# End of Header extension 211f214a20eSMichael WalleDATA 0x0 0x0 212