1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c4775476SKuo-Jung Su /* 3c4775476SKuo-Jung Su * Faraday 10/100Mbps Ethernet Controller 4c4775476SKuo-Jung Su * 5102a8cd3SKuo-Jung Su * (C) Copyright 2013 Faraday Technology 6c4775476SKuo-Jung Su * Dante Su <dantesu@faraday-tech.com> 7c4775476SKuo-Jung Su */ 8c4775476SKuo-Jung Su 9c4775476SKuo-Jung Su #ifndef _FTMAC110_H 10c4775476SKuo-Jung Su #define _FTMAC110_H 11c4775476SKuo-Jung Su 12c4775476SKuo-Jung Su struct ftmac110_regs { 13c4775476SKuo-Jung Su uint32_t isr; /* 0x00: Interrups Status Register */ 14c4775476SKuo-Jung Su uint32_t imr; /* 0x04: Interrupt Mask Register */ 15c4775476SKuo-Jung Su uint32_t mac[2]; /* 0x08: MAC Address */ 16c4775476SKuo-Jung Su uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */ 17c4775476SKuo-Jung Su uint32_t txpd; /* 0x18: Tx Poll Demand Register */ 18c4775476SKuo-Jung Su uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */ 19c4775476SKuo-Jung Su uint32_t txba; /* 0x20: Tx Ring Base Address Register */ 20c4775476SKuo-Jung Su uint32_t rxba; /* 0x24: Rx Ring Base Address Register */ 21c4775476SKuo-Jung Su uint32_t itc; /* 0x28: Interrupt Timer Control Register */ 22c4775476SKuo-Jung Su uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */ 23c4775476SKuo-Jung Su uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */ 24c4775476SKuo-Jung Su uint32_t revr; /* 0x34: Revision Register */ 25c4775476SKuo-Jung Su uint32_t fear; /* 0x38: Feature Register */ 26c4775476SKuo-Jung Su uint32_t rsvd[19]; 27c4775476SKuo-Jung Su uint32_t maccr; /* 0x88: MAC Control Register */ 28c4775476SKuo-Jung Su uint32_t macsr; /* 0x8C: MAC Status Register */ 29c4775476SKuo-Jung Su uint32_t phycr; /* 0x90: PHY Control Register */ 30c4775476SKuo-Jung Su uint32_t phydr; /* 0x94: PHY Data Register */ 31c4775476SKuo-Jung Su uint32_t fcr; /* 0x98: Flow Control Register */ 32c4775476SKuo-Jung Su uint32_t bpr; /* 0x9C: Back Pressure Register */ 33c4775476SKuo-Jung Su }; 34c4775476SKuo-Jung Su 35c4775476SKuo-Jung Su /* 36c4775476SKuo-Jung Su * Interrupt status/mask register(ISR/IMR) bits 37c4775476SKuo-Jung Su */ 38c4775476SKuo-Jung Su #define ISR_ALL 0x3ff 39c4775476SKuo-Jung Su #define ISR_PHYSTCHG (1 << 9) /* phy status change */ 40c4775476SKuo-Jung Su #define ISR_AHBERR (1 << 8) /* bus error */ 41c4775476SKuo-Jung Su #define ISR_RXLOST (1 << 7) /* rx lost */ 42c4775476SKuo-Jung Su #define ISR_RXFIFO (1 << 6) /* rx to fifo */ 43c4775476SKuo-Jung Su #define ISR_TXLOST (1 << 5) /* tx lost */ 44c4775476SKuo-Jung Su #define ISR_TXOK (1 << 4) /* tx to ethernet */ 45c4775476SKuo-Jung Su #define ISR_NOTXBUF (1 << 3) /* out of tx buffer */ 46c4775476SKuo-Jung Su #define ISR_TXFIFO (1 << 2) /* tx to fifo */ 47c4775476SKuo-Jung Su #define ISR_NORXBUF (1 << 1) /* out of rx buffer */ 48c4775476SKuo-Jung Su #define ISR_RXOK (1 << 0) /* rx to buffer */ 49c4775476SKuo-Jung Su 50c4775476SKuo-Jung Su /* 51c4775476SKuo-Jung Su * MACCR control bits 52c4775476SKuo-Jung Su */ 53c4775476SKuo-Jung Su #define MACCR_100M (1 << 18) /* 100Mbps mode */ 54c4775476SKuo-Jung Su #define MACCR_RXBCST (1 << 17) /* rx broadcast packet */ 55c4775476SKuo-Jung Su #define MACCR_RXMCST (1 << 16) /* rx multicast packet */ 56c4775476SKuo-Jung Su #define MACCR_FD (1 << 15) /* full duplex */ 57c4775476SKuo-Jung Su #define MACCR_CRCAPD (1 << 14) /* tx crc append */ 58c4775476SKuo-Jung Su #define MACCR_RXALL (1 << 12) /* rx all packets */ 59c4775476SKuo-Jung Su #define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */ 60c4775476SKuo-Jung Su #define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */ 61c4775476SKuo-Jung Su #define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */ 62c4775476SKuo-Jung Su #define MACCR_RXEN (1 << 8) /* rx enable */ 63c4775476SKuo-Jung Su #define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */ 64c4775476SKuo-Jung Su #define MACCR_TXEN (1 << 5) /* tx enable */ 65c4775476SKuo-Jung Su #define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */ 66c4775476SKuo-Jung Su #define MACCR_LOOPBACK (1 << 3) /* loop-back */ 67c4775476SKuo-Jung Su #define MACCR_RESET (1 << 2) /* reset */ 68c4775476SKuo-Jung Su #define MACCR_RXDMAEN (1 << 1) /* rx dma enable */ 69c4775476SKuo-Jung Su #define MACCR_TXDMAEN (1 << 0) /* tx dma enable */ 70c4775476SKuo-Jung Su 71c4775476SKuo-Jung Su /* 72c4775476SKuo-Jung Su * PHYCR control bits 73c4775476SKuo-Jung Su */ 74c4775476SKuo-Jung Su #define PHYCR_READ (1 << 26) 75c4775476SKuo-Jung Su #define PHYCR_WRITE (1 << 27) 76c4775476SKuo-Jung Su #define PHYCR_REG_SHIFT 21 77c4775476SKuo-Jung Su #define PHYCR_ADDR_SHIFT 16 78c4775476SKuo-Jung Su 79c4775476SKuo-Jung Su /* 80c4775476SKuo-Jung Su * ITC control bits 81c4775476SKuo-Jung Su */ 82c4775476SKuo-Jung Su 83c4775476SKuo-Jung Su /* Tx Cycle Length */ 84c4775476SKuo-Jung Su #define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */ 85c4775476SKuo-Jung Su #define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */ 86c4775476SKuo-Jung Su /* Tx Threshold: Aggregate n interrupts as 1 interrupt */ 87c4775476SKuo-Jung Su #define ITC_TX_THR(n) (((n) & 0x7) << 12) 88c4775476SKuo-Jung Su /* Tx Interrupt Timeout = n * Tx Cycle */ 89c4775476SKuo-Jung Su #define ITC_TX_ITMO(n) (((n) & 0xf) << 8) 90c4775476SKuo-Jung Su /* Rx Cycle Length */ 91c4775476SKuo-Jung Su #define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */ 92c4775476SKuo-Jung Su #define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */ 93c4775476SKuo-Jung Su /* Rx Threshold: Aggregate n interrupts as 1 interrupt */ 94c4775476SKuo-Jung Su #define ITC_RX_THR(n) (((n) & 0x7) << 4) 95c4775476SKuo-Jung Su /* Rx Interrupt Timeout = n * Rx Cycle */ 96c4775476SKuo-Jung Su #define ITC_RX_ITMO(n) (((n) & 0xf) << 0) 97c4775476SKuo-Jung Su 98c4775476SKuo-Jung Su #define ITC_DEFAULT \ 99c4775476SKuo-Jung Su (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0)) 100c4775476SKuo-Jung Su 101c4775476SKuo-Jung Su /* 102c4775476SKuo-Jung Su * APTC contrl bits 103c4775476SKuo-Jung Su */ 104c4775476SKuo-Jung Su 105c4775476SKuo-Jung Su /* Tx Cycle Length */ 106c4775476SKuo-Jung Su #define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */ 107c4775476SKuo-Jung Su #define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */ 108c4775476SKuo-Jung Su /* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */ 109c4775476SKuo-Jung Su #define APTC_TX_PTMO(n) (((n) & 0xf) << 8) 110c4775476SKuo-Jung Su /* Rx Cycle Length */ 111c4775476SKuo-Jung Su #define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */ 112c4775476SKuo-Jung Su #define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */ 113c4775476SKuo-Jung Su /* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */ 114c4775476SKuo-Jung Su #define APTC_RX_PTMO(n) (((n) & 0xf) << 0) 115c4775476SKuo-Jung Su 116c4775476SKuo-Jung Su #define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1)) 117c4775476SKuo-Jung Su 118c4775476SKuo-Jung Su /* 119c4775476SKuo-Jung Su * DBLAC contrl bits 120c4775476SKuo-Jung Su */ 121c4775476SKuo-Jung Su #define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */ 122c4775476SKuo-Jung Su #define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */ 123c4775476SKuo-Jung Su #define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */ 124c4775476SKuo-Jung Su #define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */ 125c4775476SKuo-Jung Su #define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */ 126c4775476SKuo-Jung Su #define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */ 127c4775476SKuo-Jung Su #define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */ 128c4775476SKuo-Jung Su #define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */ 129c4775476SKuo-Jung Su #define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */ 130c4775476SKuo-Jung Su 131c4775476SKuo-Jung Su #define DBLAC_DEFAULT \ 132c4775476SKuo-Jung Su (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2)) 133c4775476SKuo-Jung Su 134c4775476SKuo-Jung Su /* 135c4775476SKuo-Jung Su * descriptor structure 136c4775476SKuo-Jung Su */ 1370628cb26SKuo-Jung Su struct ftmac110_desc { 1380628cb26SKuo-Jung Su uint64_t ctrl; 1390628cb26SKuo-Jung Su uint32_t pbuf; 1400628cb26SKuo-Jung Su void *vbuf; 141c4775476SKuo-Jung Su }; 142c4775476SKuo-Jung Su 1430628cb26SKuo-Jung Su #define FTMAC110_RXD_END ((uint64_t)1 << 63) 1440628cb26SKuo-Jung Su #define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32) 145c4775476SKuo-Jung Su 1460628cb26SKuo-Jung Su #define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ 1470628cb26SKuo-Jung Su #define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */ 1480628cb26SKuo-Jung Su #define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */ 1490628cb26SKuo-Jung Su #define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */ 1500628cb26SKuo-Jung Su #define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */ 1510628cb26SKuo-Jung Su #define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */ 1520628cb26SKuo-Jung Su #define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */ 1530628cb26SKuo-Jung Su #define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */ 1540628cb26SKuo-Jung Su #define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18) 1550628cb26SKuo-Jung Su #define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */ 1560628cb26SKuo-Jung Su #define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */ 1570628cb26SKuo-Jung Su #define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff)) 158c4775476SKuo-Jung Su 1590628cb26SKuo-Jung Su #define FTMAC110_RXD_CLRMASK \ 1600628cb26SKuo-Jung Su (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff)) 161c4775476SKuo-Jung Su 1620628cb26SKuo-Jung Su #define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */ 1630628cb26SKuo-Jung Su #define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */ 1640628cb26SKuo-Jung Su #define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */ 1650628cb26SKuo-Jung Su #define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */ 1660628cb26SKuo-Jung Su #define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */ 1670628cb26SKuo-Jung Su #define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32) 168c4775476SKuo-Jung Su 1690628cb26SKuo-Jung Su #define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ 1700628cb26SKuo-Jung Su #define FTMAC110_TXD_COL ((uint64_t)3) /* collision */ 1710628cb26SKuo-Jung Su 1720628cb26SKuo-Jung Su #define FTMAC110_TXD_CLRMASK \ 1730628cb26SKuo-Jung Su (FTMAC110_TXD_END) 174c4775476SKuo-Jung Su 175c4775476SKuo-Jung Su #endif /* FTMAC110_H */ 176