1# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (c) 2012 Michael Walle
4# Michael Walle <michael@walle.cc>
5# Refer doc/README.kwbimage for more details about how-to configure
6# and create kirkwood boot image
7#
8
9# Boot Media configurations
10BOOT_FROM spi
11
12# SOC registers configuration using bootrom header extension
13# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
14
15# Configure RGMII-0/1 interface pad voltage to 1.8V
16DATA 0xFFD100E0 0x1B1B1B9B
17
18# L2 RAM Timing 0
19DATA 0xFFD20134 0xBBBBBBBB
20# not further specified in HW manual, timing taken from original vendor port
21
22# L2 RAM Timing 1
23DATA 0xFFD20138 0x00BBBBBB
24# not further specified in HW manual, timing taken from original vendor port
25
26# DDR Configuration register
27DATA 0xFFD01400 0x43000618
28# bit13-0:  0x618, 1560 DDR2 clks refresh rate
29# bit23-14: 0 required
30# bit24:    1, enable exit self refresh mode on DDR access
31# bit25:    1 required
32# bit29-26: 0 required
33# bit31-30: 0b01 required
34
35# DDR Controller Control Low
36DATA 0xFFD01404 0x39543000
37# bit3-0:   0 required
38# bit4:     0, addr/cmd in same cycle
39# bit5:     0, clk is driven during self refresh, we don't care for APX
40# bit6:     0, use recommended falling edge of clk for addr/cmd
41# bit11-7:  0 required
42# bit12:    1 required
43# bit13:    1 required
44# bit14:    0, input buffer always powered up
45# bit17-15: 0 required
46# bit18:    1, cpu lock transaction enabled
47# bit19:    0 required
48# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
49# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
50# bit30-28: 3 required
51# bit31:    0, no additional STARTBURST delay
52
53# DDR Timing (Low)
54DATA 0xFFD01408 0x3302444F
55# bit3-0:   0xf, 16 cycle tRAS (tRAS[3-0])
56# bit7-4:   4, 5 cycle tRCD
57# bit11-8:  4, 5 cyle tRP
58# bit15-12: 4, 5 cyle tWR
59# bit19-16: 2, 3 cyle tWTR
60# bit20:    0, 16 cycle tRAS (tRAS[4])
61# bit23-21: 0 required
62# bit27-24: 3, 4 cycle tRRD
63# bit31-28: 3, 4 cyle tRTP
64
65# DDR Timing (High)
66DATA 0xFFD0140C 0x00000823
67# bit6-0:   0x23, 35 cycle tRFC
68# bit8-7:   0, 1 cycle tR2R
69# bit10-9:  0, 1 cyle tR2W
70# bit12-11: 1, 2 cylce tW2W
71# bit31-13: 0 required
72
73# DDR Address Control
74DATA 0xFFD01410 0x00000009
75# bit1-0:   1, Cs0width=x16
76# bit3-2:   2, Cs0size=512Mbit
77# bit5-4:   0, Cs1width=nonexistent
78# bit7-6:   0, Cs1size=nonexistent
79# bit9-8:   0, Cs2width=nonexistent
80# bit11-10: 0, Cs2size=nonexistent
81# bit13-12: 0, Cs3width=nonexistent
82# bit15-14: 0, Cs3size=nonexistent
83# bit16:    0, Cs0AddrSel
84# bit17:    0, Cs1AddrSel
85# bit18:    0, Cs2AddrSel
86# bit19:    0, Cs3AddrSel
87# bit31-20: 0 required
88
89# DDR Open Pages Control
90DATA 0xFFD01414 0x00000000
91# bit0:    0, OPEn=OpenPage enabled
92# bit31-1: 0 required
93
94# DDR Operation
95DATA 0xFFD01418 0x00000000
96# bit3-0:   0, Cmd=Normal SDRAM Mode
97# bit31-4:  0 required
98
99# DDR Mode
100DATA 0xFFD0141C 0x00000652
101# bit2-0:   2, Burst Length (2 required)
102# bit3:     0, Burst Type (0 required)
103# bit6-4:   5, CAS Latency (CL) 5
104# bit7:     0, (Test Mode) Normal operation
105# bit8:     0, (Reset DLL) Normal operation
106# bit11-9:  3, Write recovery for auto-precharge (3 required)
107# bit12:    0, Fast Active power down exit time (0 required)
108# bit31-13: 0 required
109
110# DDR Extended Mode
111DATA 0xFFD01420 0x00000042
112# bit0:     0, DRAM DLL enabled
113# bit1:     1, DRAM drive strength reduced
114# bit2:     0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
115# bit5-3:   0 required
116# bit6:     1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
117# bit9-7:   0 required
118# bit10:    0, differential DQS enabled
119# bit11:    0 required
120# bit12:    0, DRAM output buffer enabled
121# bit31-13: 0 required
122
123# DDR Controller Control High
124DATA 0xFFD01424 0x0000F17F
125# bit2-0:   0x7 required
126# bit3:     1, MBUS Burst Chop disabled
127# bit6-4:   0x7 required
128# bit7:     0 required (???)
129# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
130# bit9:     0, no half clock cycle addition to dataout
131# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
132# bit11:    0, 1/4 clock cycle skew disabled for write mesh
133# bit15-12: 0xf required
134# bit31-16: 0 required
135
136# DDR2 ODT Read Timing (default values)
137DATA 0xFFD01428 0x00085520
138# bit3-0:   0 required
139# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
140# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
141# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
143# bit31-20: 0 required
144
145# DDR2 ODT Write Timing (default values)
146DATA 0xFFD0147C 0x00008552
147# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
148# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
149# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
151# bit31-16: 0 required
152
153# CS[0]n Base address
154DATA 0xFFD01500 0x00000000
155# at 0x0
156
157# CS[0]n Size
158DATA 0xFFD01504 0x03FFFFF1
159# bit0:     1, Window enabled
160# bit1:     0, Write Protect disabled
161# bit3-2:   0x0, CS0 hit selected
162# bit23-4:  0xfffff required
163# bit31-24: 0x03, Size (i.e. 64MB)
164
165# CS[1]n Size
166DATA 0xFFD0150C 0x00000000
167# window disabled
168
169# CS[2]n Size
170DATA 0xFFD01514 0x00000000
171# window disabled
172
173# CS[3]n Size
174DATA 0xFFD0151C 0x00000000
175# window disabled
176
177# DDR ODT Control (Low)
178DATA 0xFFD01494 0x003C0000
179# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
180# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
181# bit15-8:  0 required
182# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
183# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
184# bit31-24: 0 required
185
186# DDR ODT Control (High)
187DATA 0xFFD01498 0x00000000
188# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
189# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
190# bit31-4   0 required
191
192# CPU ODT Control
193DATA 0xFFD0149C 0x0000E80F
194# bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
195# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
196# bit9-8:   0, Internal ODT assertion is controlled by fiels
197# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
198# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
199# bit14:    1, M_STARTBURST_IN ODT enabled
200# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
201# bit20-16: 0, Pad N channel driving strength for ODT
202# bit25-21: 0, Pad P channel driving strength for ODT
203# bit31-26: 0 required
204
205# DDR Initialization Control
206DATA 0xFFD01480 0x00000001
207# bit0:     1, enable DDR init upon this register write
208# bit31-1:  0, required
209
210# End of Header extension
211DATA 0x0 0x0
212