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/openbmc/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
52 and $16,7,$3 /* E0 */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
[all …]
H A Dev6-memchr.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memchr.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9 * - memory accessed as aligned quadwords only
10 * - uses cmpbge to compare 8 bytes in parallel
11 * - does binary search to find 0 byte in last
18 * - only minimum number of quadwords may be accessed
19 * - the third argument is an unsigned long
24 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26 * E - either cluster
[all …]
/openbmc/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
69 Reading 3 temp2 Internal thermal diode
80 ------------------
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle3 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
4 source /usr/libexec/phosphor-state-manager/power-cmd
6 #Sled cycle
[all...]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
38 # bit4: 0, addr/cmd in same cycle
41 # bit11-7: 0 required
[all …]
H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
36 # bit4: 0, addr/cmd in smame cycle
[all …]
/openbmc/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
27 * MTU5 contains 3 timer counter registers and is totaly different
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
35 #define RZ_MTU3_TCR 3 /* Timer control register */
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
27 * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
33 #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
54 #define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
74 #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
75 * 2=4096 3=8192 refresh
81 * cycle delay > 0
85 * cycle delay 1..4
[all …]
/openbmc/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
12 "BriefDescription": "Total number uOps assigned to pipe 3.",
13 …-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric op…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
/openbmc/openbmc/meta-facebook/meta-minerva/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle3 # shellcheck source=meta-facebook/meta-minerva/recipes-minerva/plat-tool/files/minerva-common-funct…
4 source /usr/libexec/minerva-common-functions
6 # Minerva CMM Sled Power Cycle and Chassis Power Cycle
8 cmm-hsc-power-cycle() {
10 # [3]:
13 …# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1
23 ret1=$(i2cset -y -f 0 0x44 0xfd 0x00)
24 ret2=$(i2cset -y -f 0 0x44 0xfd 0x0b)
27 ret3=$(i2cset -f -y 0 0x43 0xec)
29 if [ "$ret3" -ne 0 ] && { [ "$ret1" -ne 0 ] || [ "$ret2" -ne 0 ]; }; then
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * STATIC_TRAINING - Set only if static parameters for training are set and
23 /*3 */
43 /*3 */
56 /*center DQS on read cycle */
76 /*3 */
96 /*3 */
116 /*3 */
129 /*center DQS on read cycle */
149 /*3 2 4 0 */
[all …]
/openbmc/openbmc/meta-facebook/meta-ventura/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle3 # Ventura RMC Sled Power Cycle
5 rmc-hsc-power-cycle() {
7 # [3]:
10 …# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1
20 ret1=$(i2cget -y -f 10 0x44)
21 ret2=$(i2cget -y -f 10 0x14)
23 if [[ "$ret1" =~ ^0x[0-9A-Fa-f]+$ ]]; then
25 i2cset -y -f 10 0x44 0xfd 0x00
26 i2cset -y -f 10 0x44 0xfd 0x0b
27 elif [[ "$ret2" =~ ^0x[0-9A-Fa-f]+$ ]]; then
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
42 u32 reg, cycle, ctl; in ar934x_ddr_init() local
51 cycle = 0xffff; in ar934x_ddr_init()
54 if (gd->arch.rev) { in ar934x_ddr_init()
55 ctl = BIT(6); /* Undocumented bit :-( */ in ar934x_ddr_init()
56 if (reg & BIT(3)) in ar934x_ddr_init()
57 cycle = 0xff; in ar934x_ddr_init()
59 cycle = 0xffff; in ar934x_ddr_init()
63 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
80 cycle = 0xffffffff; in ar934x_ddr_init()
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0 */
66 #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
67 #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
69 #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
70 #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
72 #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
73 #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
74 #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
75 #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
80 #define SPIBAR_SSFS_ERROR (1 << 3)
/openbmc/linux/drivers/pwm/
H A Dpwm-sl28cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
21 * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns |
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
30 * - The duty cycle will switch immediately and not after a complete cycle.
[all …]
/openbmc/u-boot/drivers/pwm/
H A DKconfig2 bool "Enable support for pulse-width modulation devices (PWM)"
5 A pulse-width modulator emits a pulse of varying width and provides
6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
26 programmable period and duty cycle. A 32-bit counter is used.
28 continuous/single-shot) are not supported by the driver.
33 This is a sandbox PWM used for testing. It provides 3 channels and
43 four channels with a programmable period and duty cycle. Only a
44 32KHz clock is supported by the driver but the duty cycle is
52 programmable period and duty cycle. A 16-bit counter is used.
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Dfloating-point.json6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
12 "BriefDescription": "Total number uOps assigned to pipe 3.",
13 …-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric op…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …ly-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired …
53 …are root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
59 …Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/openbmc/u-boot/drivers/net/
H A Dftmac110.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
45 #define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
66 #define MACCR_LOOPBACK (1 << 3) /* loop-back */
83 /* Tx Cycle Length */
88 /* Tx Interrupt Timeout = n * Tx Cycle */
90 /* Rx Cycle Length */
95 /* Rx Interrupt Timeout = n * Rx Cycle */
105 /* Tx Cycle Length */
108 /* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
[all …]

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