| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
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| H A D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
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| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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| H A D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
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| H A D | vt8500.txt | 1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
15 Required properties for PLL clocks:
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| H A D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
8 Please refer to the Reference Manual for details.
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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| H A D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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| H A D | mvebu-gated-clock.txt | 1 * Gated Clock bindings for Marvell EBU SoCs
4 peripheral clocks to be gated to save some power. The clock consumer
5 should specify the desired clock by having the clock ID in its
6 "clocks" phandle cell. The clock ID is directly mapped to the
7 corresponding clock gating control bit in HW to ease manual clock
10 The following is a list of provided IDs for Armada 370:
11 ID Clock Peripheral
12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
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| H A D | armada3700-periph-clock.txt | 1 * Peripheral Clock bindings for Marvell Armada 37xx SoCs
4 used as clock source for the peripheral of the SoC.
9 The peripheral clock consumer should specify the desired clock by
10 having the clock ID in its "clocks" phandle cell.
12 The following is a list of provided IDs for Armada 3700 North bridge clocks:
13 ID Clock name Description
14 -----------------------------------
27 12 ddr_fclk DDR F clock
33 The following is a list of provided IDs for Armada 3700 South bridge clocks:
34 ID Clock name Description
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| H A D | imx7ulp-scg-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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| H A D | imx7ulp-pcc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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| /openbmc/linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
46 bool "PLL Driver for HSDK platform"
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
58 Say yes here to build support for Texas Instruments' LMK04832 Ultra
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | gate.txt | 1 Binding for Texas Instruments gate clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
9 will be controlled instead and the corresponding hw-ops for
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
17 - compatible : shall be one of:
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| H A D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
9 In order to provide the support for ATL and its output clocks (which can be used
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MediaTek Clock Drivers
5 menu "Clock driver for MediaTek SoC"
12 MediaTek SoCs' clock support.
15 bool "clock driver for MediaTek FHCTL hardware control"
22 bool "Clock driver for MediaTek MT2701"
30 bool "Clock driver for MediaTek MT2701 mmsys"
36 bool "Clock driver for MediaTek MT2701 imgsys"
42 bool "Clock driver for MediaTek MT2701 vdecsys"
48 bool "Clock driver for MediaTek MT2701 hifsys"
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| /openbmc/qemu/docs/devel/ |
| H A D | clocks.rst | 1 Modelling a clock tree in QEMU
5 ----------------
7 Clocks are QOM objects developed for the purpose of modelling the
10 They allow us to model the clock distribution of a platform and detect
11 configuration errors in the clock tree such as badly configured PLL, clock
12 source selection or disabled clock.
14 The object is *Clock* and its QOM name is ``clock`` (in C code, the macro
21 In these cases a Clock object is a child of a Device object, but this
22 is not a requirement. Clocks can be independent of devices. For
23 example it is possible to create a clock outside of any device to
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| /openbmc/linux/sound/soc/qcom/qdsp6/ |
| H A D | q6afe.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <dt-bindings/sound/qcom,q6afe.h>
26 /* Clock ID for Primary I2S IBIT */
28 /* Clock ID for Primary I2S EBIT */
30 /* Clock ID for Secondary I2S IBIT */
32 /* Clock ID for Secondary I2S EBIT */
34 /* Clock ID for Tertiary I2S IBIT */
36 /* Clock ID for Tertiary I2S EBIT */
38 /* Clock ID for Quartnery I2S IBIT */
40 /* Clock ID for Quartnery I2S EBIT */
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| H A D | q6prm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Clock ID for Primary I2S IBIT */
8 /* Clock ID for Primary I2S EBIT */
10 /* Clock ID for Secondary I2S IBIT */
12 /* Clock ID for Secondary I2S EBIT */
14 /* Clock ID for Tertiary I2S IBIT */
16 /* Clock ID for Tertiary I2S EBIT */
18 /* Clock ID for Quartnery I2S IBIT */
20 /* Clock ID for Quartnery I2S EBIT */
22 /* Clock ID for Speaker I2S IBIT */
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
26 Support for the A53 PLL on MSM8916 devices. It provides
32 tristate "A7 PLL driver for SDX55 and SDX65"
34 Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
55 Say Y if you want to support CPU clock scaling using CPUfreq
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| /openbmc/linux/include/linux/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
30 * ABORT_RATE_CHANGE: called if the rate change failed for some reason
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
46 * @notifier_head: a blocking_notifier_head for this clk
61 * struct clk_notifier_data - rate data to pass to the notifier callback
66 * For a pre-notifier, old_rate is the clk's rate before this rate
67 * change, and new_rate is what the rate will be in the future. For a
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
17 Build the driver for PX30 Clock Driver.
20 bool "Rockchip RV110x clock controller support"
24 Build the driver for RV110x Clock Driver.
27 bool "Rockchip RV1126 clock controller support"
31 Build the driver for RV1126 Clock Driver.
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| /openbmc/u-boot/drivers/clk/ |
| H A D | Kconfig | 1 menu "Clock" menu
4 bool "Enable clock driver support"
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
11 choose the source for each clock.
14 bool "Enable clock support in SPL"
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
21 used as U-Boot proper.
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | renesas,du.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
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| /openbmc/qemu/include/hw/ |
| H A D | clock.h | 4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
22 #define TYPE_CLOCK "clock"
23 OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK)
32 ClockUpdate = 1, /* Clock period has just updated */
33 ClockPreUpdate = 2, /* Clock period is about to update */
39 * clock store a value representing the clock's period in 2^-32ns unit.
41 * + periods from 2^-32ns up to 4seconds
58 * Clock:
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| /openbmc/linux/drivers/clk/bcm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 Enable common clock framework support for the Broadcom BCM2711
15 bool "Broadcom BCM2835 clock support"
20 Enable common clock framework support for Broadcom BCM2835
24 bool "Broadcom BCM63xx clock support"
29 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
33 bool "Broadcom BCM63xx gated clock support"
37 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
41 bool "Broadcom BCM63268 timer clock and reset support"
46 Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs
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