19a0e5d6fSSrinivas Kandagatla /* SPDX-License-Identifier: GPL-2.0 */ 29a0e5d6fSSrinivas Kandagatla 39a0e5d6fSSrinivas Kandagatla #ifndef __Q6PRM_H__ 49a0e5d6fSSrinivas Kandagatla #define __Q6PRM_H__ 59a0e5d6fSSrinivas Kandagatla 69a0e5d6fSSrinivas Kandagatla /* Clock ID for Primary I2S IBIT */ 79a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 89a0e5d6fSSrinivas Kandagatla /* Clock ID for Primary I2S EBIT */ 99a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101 109a0e5d6fSSrinivas Kandagatla /* Clock ID for Secondary I2S IBIT */ 119a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102 129a0e5d6fSSrinivas Kandagatla /* Clock ID for Secondary I2S EBIT */ 139a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103 149a0e5d6fSSrinivas Kandagatla /* Clock ID for Tertiary I2S IBIT */ 159a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104 169a0e5d6fSSrinivas Kandagatla /* Clock ID for Tertiary I2S EBIT */ 179a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105 189a0e5d6fSSrinivas Kandagatla /* Clock ID for Quartnery I2S IBIT */ 199a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106 209a0e5d6fSSrinivas Kandagatla /* Clock ID for Quartnery I2S EBIT */ 219a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107 229a0e5d6fSSrinivas Kandagatla /* Clock ID for Speaker I2S IBIT */ 239a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108 249a0e5d6fSSrinivas Kandagatla /* Clock ID for Speaker I2S EBIT */ 259a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109 269a0e5d6fSSrinivas Kandagatla /* Clock ID for Speaker I2S OSR */ 279a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A 289a0e5d6fSSrinivas Kandagatla 299a0e5d6fSSrinivas Kandagatla /* Clock ID for QUINARY I2S IBIT */ 309a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B 319a0e5d6fSSrinivas Kandagatla /* Clock ID for QUINARY I2S EBIT */ 329a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C 339a0e5d6fSSrinivas Kandagatla /* Clock ID for SENARY I2S IBIT */ 349a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D 359a0e5d6fSSrinivas Kandagatla /* Clock ID for SENARY I2S EBIT */ 369a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E 379a0e5d6fSSrinivas Kandagatla /* Clock ID for INT0 I2S IBIT */ 389a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F 399a0e5d6fSSrinivas Kandagatla /* Clock ID for INT1 I2S IBIT */ 409a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110 419a0e5d6fSSrinivas Kandagatla /* Clock ID for INT2 I2S IBIT */ 429a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111 439a0e5d6fSSrinivas Kandagatla /* Clock ID for INT3 I2S IBIT */ 449a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112 459a0e5d6fSSrinivas Kandagatla /* Clock ID for INT4 I2S IBIT */ 469a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113 479a0e5d6fSSrinivas Kandagatla /* Clock ID for INT5 I2S IBIT */ 489a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114 499a0e5d6fSSrinivas Kandagatla /* Clock ID for INT6 I2S IBIT */ 509a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115 519a0e5d6fSSrinivas Kandagatla 529a0e5d6fSSrinivas Kandagatla /* Clock ID for QUINARY MI2S OSR CLK */ 539a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 549a0e5d6fSSrinivas Kandagatla 559a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305 569a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306 579a0e5d6fSSrinivas Kandagatla 589a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307 599a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308 609a0e5d6fSSrinivas Kandagatla 619a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c 629a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d 639a0e5d6fSSrinivas Kandagatla 649a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e 659a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f 669a0e5d6fSSrinivas Kandagatla 67*ea15d3bdSSrinivas Kandagatla /* Clock ID for MCLK for WSA2 core */ 68*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310 69*ea15d3bdSSrinivas Kandagatla /* Clock ID for NPL MCLK for WSA2 core */ 70*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311 71*ea15d3bdSSrinivas Kandagatla /* Clock ID for RX Core TX MCLK */ 72*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312 73*ea15d3bdSSrinivas Kandagatla /* Clock ID for RX CORE TX 2X MCLK */ 74*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313 75*ea15d3bdSSrinivas Kandagatla /* Clock ID for WSA core TX MCLK */ 76*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314 77*ea15d3bdSSrinivas Kandagatla /* Clock ID for WSA core TX 2X MCLK */ 78*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315 79*ea15d3bdSSrinivas Kandagatla /* Clock ID for WSA2 core TX MCLK */ 80*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316 81*ea15d3bdSSrinivas Kandagatla /* Clock ID for WSA2 core TX 2X MCLK */ 82*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317 83*ea15d3bdSSrinivas Kandagatla /* Clock ID for RX CORE MCLK2 2X MCLK */ 84*ea15d3bdSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318 85*ea15d3bdSSrinivas Kandagatla 869a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_SRC_INTERNAL 1 879a0e5d6fSSrinivas Kandagatla #define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0 889a0e5d6fSSrinivas Kandagatla #define Q6PRM_HW_CORE_ID_LPASS 1 899a0e5d6fSSrinivas Kandagatla #define Q6PRM_HW_CORE_ID_DCODEC 2 909a0e5d6fSSrinivas Kandagatla 919a0e5d6fSSrinivas Kandagatla int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, 929a0e5d6fSSrinivas Kandagatla int clk_root, unsigned int freq); 939a0e5d6fSSrinivas Kandagatla int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 949a0e5d6fSSrinivas Kandagatla const char *client_name, uint32_t *client_handle); 959a0e5d6fSSrinivas Kandagatla int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 969a0e5d6fSSrinivas Kandagatla uint32_t client_handle); 979a0e5d6fSSrinivas Kandagatla #endif /* __Q6PRM_H__ */ 98