17fa2d70fSSrinivas Kandagatla /* SPDX-License-Identifier: GPL-2.0 */ 27fa2d70fSSrinivas Kandagatla 37fa2d70fSSrinivas Kandagatla #ifndef __Q6AFE_H__ 47fa2d70fSSrinivas Kandagatla #define __Q6AFE_H__ 57fa2d70fSSrinivas Kandagatla 67fa2d70fSSrinivas Kandagatla #include <dt-bindings/sound/qcom,q6afe.h> 77fa2d70fSSrinivas Kandagatla 8*d0293e2aSGabriel David #define AFE_PORT_MAX 129 97fa2d70fSSrinivas Kandagatla 107fa2d70fSSrinivas Kandagatla #define MSM_AFE_PORT_TYPE_RX 0 117fa2d70fSSrinivas Kandagatla #define MSM_AFE_PORT_TYPE_TX 1 127fa2d70fSSrinivas Kandagatla #define AFE_MAX_PORTS AFE_PORT_MAX 137fa2d70fSSrinivas Kandagatla 14d3839145SSrinivas Kandagatla #define Q6AFE_MAX_MI2S_LINES 4 15d3839145SSrinivas Kandagatla 164d430d5aSSrinivas Kandagatla #define AFE_MAX_CHAN_COUNT 8 174d430d5aSSrinivas Kandagatla #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8 184d430d5aSSrinivas Kandagatla 19a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 20a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 21a4ae3af5SSrinivas Kandagatla 22a4ae3af5SSrinivas Kandagatla #define LPAIF_DIG_CLK 1 23a4ae3af5SSrinivas Kandagatla #define LPAIF_BIT_CLK 2 24a4ae3af5SSrinivas Kandagatla #define LPAIF_OSR_CLK 3 25a4ae3af5SSrinivas Kandagatla 26a4ae3af5SSrinivas Kandagatla /* Clock ID for Primary I2S IBIT */ 27a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 28a4ae3af5SSrinivas Kandagatla /* Clock ID for Primary I2S EBIT */ 29a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101 30a4ae3af5SSrinivas Kandagatla /* Clock ID for Secondary I2S IBIT */ 31a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102 32a4ae3af5SSrinivas Kandagatla /* Clock ID for Secondary I2S EBIT */ 33a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103 34a4ae3af5SSrinivas Kandagatla /* Clock ID for Tertiary I2S IBIT */ 35a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104 36a4ae3af5SSrinivas Kandagatla /* Clock ID for Tertiary I2S EBIT */ 37a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105 38a4ae3af5SSrinivas Kandagatla /* Clock ID for Quartnery I2S IBIT */ 39a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106 40a4ae3af5SSrinivas Kandagatla /* Clock ID for Quartnery I2S EBIT */ 41a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107 42a4ae3af5SSrinivas Kandagatla /* Clock ID for Speaker I2S IBIT */ 43a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108 44a4ae3af5SSrinivas Kandagatla /* Clock ID for Speaker I2S EBIT */ 45a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109 46a4ae3af5SSrinivas Kandagatla /* Clock ID for Speaker I2S OSR */ 47a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A 48a4ae3af5SSrinivas Kandagatla 49a4ae3af5SSrinivas Kandagatla /* Clock ID for QUINARY I2S IBIT */ 50a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B 51a4ae3af5SSrinivas Kandagatla /* Clock ID for QUINARY I2S EBIT */ 52a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C 53a4ae3af5SSrinivas Kandagatla /* Clock ID for SENARY I2S IBIT */ 54a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D 55a4ae3af5SSrinivas Kandagatla /* Clock ID for SENARY I2S EBIT */ 56a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E 57a4ae3af5SSrinivas Kandagatla /* Clock ID for INT0 I2S IBIT */ 58a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F 59a4ae3af5SSrinivas Kandagatla /* Clock ID for INT1 I2S IBIT */ 60a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110 61a4ae3af5SSrinivas Kandagatla /* Clock ID for INT2 I2S IBIT */ 62a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111 63a4ae3af5SSrinivas Kandagatla /* Clock ID for INT3 I2S IBIT */ 64a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112 65a4ae3af5SSrinivas Kandagatla /* Clock ID for INT4 I2S IBIT */ 66a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113 67a4ae3af5SSrinivas Kandagatla /* Clock ID for INT5 I2S IBIT */ 68a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114 69a4ae3af5SSrinivas Kandagatla /* Clock ID for INT6 I2S IBIT */ 70a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115 71a4ae3af5SSrinivas Kandagatla 72a4ae3af5SSrinivas Kandagatla /* Clock ID for QUINARY MI2S OSR CLK */ 73a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 74a4ae3af5SSrinivas Kandagatla 75a4ae3af5SSrinivas Kandagatla /* Clock ID for Primary PCM IBIT */ 76a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200 77a4ae3af5SSrinivas Kandagatla /* Clock ID for Primary PCM EBIT */ 78a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201 79a4ae3af5SSrinivas Kandagatla /* Clock ID for Secondary PCM IBIT */ 80a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202 81a4ae3af5SSrinivas Kandagatla /* Clock ID for Secondary PCM EBIT */ 82a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203 83a4ae3af5SSrinivas Kandagatla /* Clock ID for Tertiary PCM IBIT */ 84a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204 85a4ae3af5SSrinivas Kandagatla /* Clock ID for Tertiary PCM EBIT */ 86a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205 87a4ae3af5SSrinivas Kandagatla /* Clock ID for Quartery PCM IBIT */ 88a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206 89a4ae3af5SSrinivas Kandagatla /* Clock ID for Quartery PCM EBIT */ 90a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207 91a4ae3af5SSrinivas Kandagatla /* Clock ID for Quinary PCM IBIT */ 92a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208 93a4ae3af5SSrinivas Kandagatla /* Clock ID for Quinary PCM EBIT */ 94a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209 95a4ae3af5SSrinivas Kandagatla /* Clock ID for QUINARY PCM OSR */ 96a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A 97a4ae3af5SSrinivas Kandagatla 98a4ae3af5SSrinivas Kandagatla /** Clock ID for Primary TDM IBIT */ 99a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200 100a4ae3af5SSrinivas Kandagatla /** Clock ID for Primary TDM EBIT */ 101a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201 102a4ae3af5SSrinivas Kandagatla /** Clock ID for Secondary TDM IBIT */ 103a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202 104a4ae3af5SSrinivas Kandagatla /** Clock ID for Secondary TDM EBIT */ 105a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203 106a4ae3af5SSrinivas Kandagatla /** Clock ID for Tertiary TDM IBIT */ 107a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204 108a4ae3af5SSrinivas Kandagatla /** Clock ID for Tertiary TDM EBIT */ 109a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205 110a4ae3af5SSrinivas Kandagatla /** Clock ID for Quartery TDM IBIT */ 111a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206 112a4ae3af5SSrinivas Kandagatla /** Clock ID for Quartery TDM EBIT */ 113a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207 114a4ae3af5SSrinivas Kandagatla /** Clock ID for Quinary TDM IBIT */ 115a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208 116a4ae3af5SSrinivas Kandagatla /** Clock ID for Quinary TDM EBIT */ 117a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209 118a4ae3af5SSrinivas Kandagatla /** Clock ID for Quinary TDM OSR */ 119a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A 120a4ae3af5SSrinivas Kandagatla 121a4ae3af5SSrinivas Kandagatla /* Clock ID for MCLK1 */ 122a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300 123a4ae3af5SSrinivas Kandagatla /* Clock ID for MCLK2 */ 124a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301 125a4ae3af5SSrinivas Kandagatla /* Clock ID for MCLK3 */ 126a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302 127a4ae3af5SSrinivas Kandagatla /* Clock ID for MCLK4 */ 128a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304 129a4ae3af5SSrinivas Kandagatla /* Clock ID for Internal Digital Codec Core */ 130a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303 131a4ae3af5SSrinivas Kandagatla /* Clock ID for INT MCLK0 */ 132a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305 133a4ae3af5SSrinivas Kandagatla /* Clock ID for INT MCLK1 */ 134a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306 135a4ae3af5SSrinivas Kandagatla 1360c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309 1370c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a 1380c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c 1390c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d 1400c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e 1410c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f 1420c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b 1430c3e35fcSSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310 1440c3e35fcSSrinivas Kandagatla 14555e07531SSrinivas Kandagatla #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2 14655e07531SSrinivas Kandagatla #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3 14755e07531SSrinivas Kandagatla #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4 14855e07531SSrinivas Kandagatla 149a4ae3af5SSrinivas Kandagatla /* Clock attribute for invalid use (reserved for internal usage) */ 150a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0 151a4ae3af5SSrinivas Kandagatla /* Clock attribute for no couple case */ 152a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 153a4ae3af5SSrinivas Kandagatla /* Clock attribute for dividend couple case */ 154a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 155a4ae3af5SSrinivas Kandagatla /* Clock attribute for divisor couple case */ 156a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 157a4ae3af5SSrinivas Kandagatla /* Clock attribute for invert and no couple case */ 158a4ae3af5SSrinivas Kandagatla #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4 159a4ae3af5SSrinivas Kandagatla 160dea1ffbeSSrinivas Kandagatla #define Q6AFE_CMAP_INVALID 0xFFFF 161dea1ffbeSSrinivas Kandagatla 1627fa2d70fSSrinivas Kandagatla struct q6afe_hdmi_cfg { 1637fa2d70fSSrinivas Kandagatla u16 datatype; 1647fa2d70fSSrinivas Kandagatla u16 channel_allocation; 1657fa2d70fSSrinivas Kandagatla u32 sample_rate; 1667fa2d70fSSrinivas Kandagatla u16 bit_width; 1677fa2d70fSSrinivas Kandagatla }; 1687fa2d70fSSrinivas Kandagatla 1694d430d5aSSrinivas Kandagatla struct q6afe_slim_cfg { 1704d430d5aSSrinivas Kandagatla u32 sample_rate; 1714d430d5aSSrinivas Kandagatla u16 bit_width; 1724d430d5aSSrinivas Kandagatla u16 data_format; 1734d430d5aSSrinivas Kandagatla u16 num_channels; 1744d430d5aSSrinivas Kandagatla u8 ch_mapping[AFE_MAX_CHAN_COUNT]; 1754d430d5aSSrinivas Kandagatla }; 1764d430d5aSSrinivas Kandagatla 177d3839145SSrinivas Kandagatla struct q6afe_i2s_cfg { 178d3839145SSrinivas Kandagatla u32 sample_rate; 179d3839145SSrinivas Kandagatla u16 bit_width; 180d3839145SSrinivas Kandagatla u16 data_format; 181d3839145SSrinivas Kandagatla u16 num_channels; 182d3839145SSrinivas Kandagatla u32 sd_line_mask; 183d3839145SSrinivas Kandagatla int fmt; 184d3839145SSrinivas Kandagatla }; 185d3839145SSrinivas Kandagatla 186dea1ffbeSSrinivas Kandagatla struct q6afe_tdm_cfg { 187dea1ffbeSSrinivas Kandagatla u16 num_channels; 188dea1ffbeSSrinivas Kandagatla u32 sample_rate; 189dea1ffbeSSrinivas Kandagatla u16 bit_width; 190dea1ffbeSSrinivas Kandagatla u16 data_format; 191dea1ffbeSSrinivas Kandagatla u16 sync_mode; 192dea1ffbeSSrinivas Kandagatla u16 sync_src; 193dea1ffbeSSrinivas Kandagatla u16 nslots_per_frame; 194dea1ffbeSSrinivas Kandagatla u16 slot_width; 195dea1ffbeSSrinivas Kandagatla u16 slot_mask; 196dea1ffbeSSrinivas Kandagatla u32 data_align_type; 197dea1ffbeSSrinivas Kandagatla u16 ch_mapping[AFE_MAX_CHAN_COUNT]; 198dea1ffbeSSrinivas Kandagatla }; 199dea1ffbeSSrinivas Kandagatla 200150b2e86SSrinivas Kandagatla struct q6afe_cdc_dma_cfg { 201150b2e86SSrinivas Kandagatla u16 sample_rate; 202150b2e86SSrinivas Kandagatla u16 bit_width; 203150b2e86SSrinivas Kandagatla u16 data_format; 204150b2e86SSrinivas Kandagatla u16 num_channels; 205150b2e86SSrinivas Kandagatla u16 active_channels_mask; 206150b2e86SSrinivas Kandagatla }; 207150b2e86SSrinivas Kandagatla 208150b2e86SSrinivas Kandagatla 2097fa2d70fSSrinivas Kandagatla struct q6afe_port_config { 2107fa2d70fSSrinivas Kandagatla struct q6afe_hdmi_cfg hdmi; 2114d430d5aSSrinivas Kandagatla struct q6afe_slim_cfg slim; 212d3839145SSrinivas Kandagatla struct q6afe_i2s_cfg i2s_cfg; 213dea1ffbeSSrinivas Kandagatla struct q6afe_tdm_cfg tdm; 214150b2e86SSrinivas Kandagatla struct q6afe_cdc_dma_cfg dma_cfg; 2157fa2d70fSSrinivas Kandagatla }; 2167fa2d70fSSrinivas Kandagatla 2177fa2d70fSSrinivas Kandagatla struct q6afe_port; 2187fa2d70fSSrinivas Kandagatla 2197fa2d70fSSrinivas Kandagatla struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id); 2207fa2d70fSSrinivas Kandagatla int q6afe_port_start(struct q6afe_port *port); 2217fa2d70fSSrinivas Kandagatla int q6afe_port_stop(struct q6afe_port *port); 2227fa2d70fSSrinivas Kandagatla void q6afe_port_put(struct q6afe_port *port); 2237fa2d70fSSrinivas Kandagatla int q6afe_get_port_id(int index); 2247fa2d70fSSrinivas Kandagatla void q6afe_hdmi_port_prepare(struct q6afe_port *port, 2257fa2d70fSSrinivas Kandagatla struct q6afe_hdmi_cfg *cfg); 2264d430d5aSSrinivas Kandagatla void q6afe_slim_port_prepare(struct q6afe_port *port, 2274d430d5aSSrinivas Kandagatla struct q6afe_slim_cfg *cfg); 228d3839145SSrinivas Kandagatla int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg); 229dea1ffbeSSrinivas Kandagatla void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg); 230150b2e86SSrinivas Kandagatla void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 231150b2e86SSrinivas Kandagatla struct q6afe_cdc_dma_cfg *cfg); 2327fa2d70fSSrinivas Kandagatla 233a4ae3af5SSrinivas Kandagatla int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 234a4ae3af5SSrinivas Kandagatla int clk_src, int clk_root, 235a4ae3af5SSrinivas Kandagatla unsigned int freq, int dir); 23632d4e59cSPierre-Louis Bossart int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 2370c3e35fcSSrinivas Kandagatla int clk_root, unsigned int freq); 23855e07531SSrinivas Kandagatla int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 23996fadf7eSDmitry Baryshkov const char *client_name, uint32_t *client_handle); 24055e07531SSrinivas Kandagatla int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 24155e07531SSrinivas Kandagatla uint32_t client_handle); 2427fa2d70fSSrinivas Kandagatla #endif /* __Q6AFE_H__ */ 243