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Searched full:clk_m (Results 1 – 25 of 43) sorted by relevance

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/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c269 "clk_m"};
285 "pll_p", "pll_c", "pll_m", "clk_m"
293 "pll_p", "pll_c", "clk_32k", "clk_m"
298 "pll_a_out0", "pll_c", "pll_p", "clk_m"
303 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
310 "pll_p", "clk_m"
317 "pll_p", "clk_m"
324 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
332 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
347 "clk_m", "pll_c", "pll_p", "pll_a_out0"
[all …]
H A Dclk-tegra-super-gen4.c45 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
49 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
55 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
69 static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
73 static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
79 static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
H A Dclk-tegra20.c465 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
697 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
700 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
749 "clk_m" };
751 "clk_m" };
752 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
754 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
756 "clk_m" };
811 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
816 clk_register_divider(NULL, "dev1_osc_div", "clk_m", in tegra20_periph_clk_init()
[all …]
H A Dclk-tegra30.c592 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
877 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
880 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
884 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
972 "clk_m" };
973 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
975 "clk_m" };
979 "pll_d2_out0", "clk_m" };
982 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1012 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
[all …]
H A Dclk-tegra-fixed.c76 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", in tegra_osc_clk_init()
H A Dclk-tegra20-emc.c36 "pll_m", "pll_c", "pll_p", "clk_m",
H A Dclk-sdmmc-mux.c30 "pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra234-xusb.yaml60 - const: clk_m
144 "xusb_fs_src", "pll_u_480m", "clk_m",
H A Dnvidia,tegra194-xusb.yaml56 - const: clk_m
159 "xusb_fs_src", "pll_u_480m", "clk_m",
H A Dnvidia,tegra186-xusb.yaml56 - const: clk_m
156 "pll_u_480m", "clk_m", "pll_e";
H A Dnvidia,tegra124-xusb.yaml70 - const: clk_m
183 "clk_m", "pll_e";
H A Dnvidia,tegra210-xusb.yaml62 - const: clk_m
167 "pll_u_480m", "clk_m", "pll_e";
/openbmc/u-boot/include/configs/
H A Dp2371-2180.h31 /* Crystal is 38.4MHz. clk_m runs at half that rate */
H A Dp2771-0000.h43 /* Crystal is 38.4MHz. clk_m runs at half that rate */
/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c13 #define CLK_M 0 macro
222 if (dom == CLK_M) in get_hclk_sys()
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c25 * Letters are obvious, except for T which means CLK_M, and S which means the
26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
719 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); in arch_timer_init()
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra186-timer.yaml15 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt137 106 clk_m
/openbmc/linux/drivers/video/fbdev/
H A Dimsttfb.c426 __u32 clk_m, clk_n, clk_p; in getclkMHz() local
428 clk_m = par->init.pclk_m; in getclkMHz()
432 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1)); in getclkMHz()
438 __u32 clk_m, clk_n, x, stage, spilled; in setclkMHz() local
440 clk_m = clk_n = 0; in setclkMHz()
445 clk_m++; in setclkMHz()
451 x = 20 * (clk_m + 1) / (clk_n + 1); in setclkMHz()
462 par->init.pclk_m = clk_m; in setclkMHz()
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c26 * Letters are obvious, except for T which means CLK_M, and S which means the
27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dcpu.c115 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17) in t30_init_clocks()
H A Dclock.c25 * Letters are obvious, except for T which means CLK_M, and S which means the
26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
/openbmc/linux/drivers/usb/host/
H A Dxhci-tegra.c284 struct clk *clk_m; member
447 /* Reparent to CLK_M */ in tegra_xusb_set_ss_clk()
448 err = clk_set_parent(clk, tegra->clk_m); in tegra_xusb_set_ss_clk()
1656 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); in tegra_xusb_probe()
1657 if (IS_ERR(tegra->clk_m)) { in tegra_xusb_probe()
1658 err = PTR_ERR(tegra->clk_m); in tegra_xusb_probe()
1659 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); in tegra_xusb_probe()
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c25 * Letters are obvious, except for T which means CLK_M, and S which means the
26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
917 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); in arch_timer_init()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c26 * Letters are obvious, except for T which means CLK_M, and S which means the
27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
1050 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); in arch_timer_init()

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