1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 210a03382SStephen Warren /* 310a03382SStephen Warren * Copyright (c) 2013-2016, NVIDIA CORPORATION. 410a03382SStephen Warren */ 510a03382SStephen Warren 610a03382SStephen Warren #ifndef _P2771_0000_H 710a03382SStephen Warren #define _P2771_0000_H 810a03382SStephen Warren 910a03382SStephen Warren #include <linux/sizes.h> 1010a03382SStephen Warren 1110a03382SStephen Warren #include "tegra186-common.h" 1210a03382SStephen Warren 1310a03382SStephen Warren /* High-level configuration options */ 1410a03382SStephen Warren #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" 1510a03382SStephen Warren 1610a03382SStephen Warren /* Environment in eMMC, at the end of 2nd "boot sector" */ 1710a03382SStephen Warren #define CONFIG_SYS_MMC_ENV_DEV 0 1810a03382SStephen Warren #define CONFIG_SYS_MMC_ENV_PART 2 1910a03382SStephen Warren #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 2010a03382SStephen Warren 21e43effc1SStephen Warren #define BOARD_EXTRA_ENV_SETTINGS \ 22e43effc1SStephen Warren "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ 23e43effc1SStephen Warren "ramdisk_addr_r\0" \ 24e43effc1SStephen Warren "kernel_addr_r_align=00200000\0" \ 25e43effc1SStephen Warren "kernel_addr_r_offset=00080000\0" \ 26e43effc1SStephen Warren "kernel_addr_r_size=02000000\0" \ 27e43effc1SStephen Warren "kernel_addr_r_aliases=loadaddr\0" \ 28e43effc1SStephen Warren "fdt_addr_r_align=00200000\0" \ 29e43effc1SStephen Warren "fdt_addr_r_offset=00000000\0" \ 30e43effc1SStephen Warren "fdt_addr_r_size=00200000\0" \ 31e43effc1SStephen Warren "scriptaddr_align=00200000\0" \ 32e43effc1SStephen Warren "scriptaddr_offset=00000000\0" \ 33e43effc1SStephen Warren "scriptaddr_size=00200000\0" \ 34e43effc1SStephen Warren "pxefile_addr_r_align=00200000\0" \ 35e43effc1SStephen Warren "pxefile_addr_r_offset=00000000\0" \ 36e43effc1SStephen Warren "pxefile_addr_r_size=00200000\0" \ 37e43effc1SStephen Warren "ramdisk_addr_r_align=00200000\0" \ 38e43effc1SStephen Warren "ramdisk_addr_r_offset=00000000\0" \ 39e43effc1SStephen Warren "ramdisk_addr_r_size=02000000\0" 40e43effc1SStephen Warren 4110a03382SStephen Warren #include "tegra-common-post.h" 4210a03382SStephen Warren 4310a03382SStephen Warren /* Crystal is 38.4MHz. clk_m runs at half that rate */ 4410a03382SStephen Warren #define COUNTER_FREQUENCY 19200000 4510a03382SStephen Warren 4610a03382SStephen Warren #endif 47