clk/tegra/clk-tegra20.c

465 	{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
697 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
700 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
749 				      "clk_m" };
751 				      "clk_m" };
752 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
754 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
756 					 "clk_m" };
811 	clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,  in tegra20_periph_clk_init()
816 	clk_register_divider(NULL, "dev1_osc_div", "clk_m",  in tegra20_periph_clk_init()
822 	clk_register_divider(NULL, "dev2_osc_div", "clk_m",  in tegra20_periph_clk_init()
863 	/* clk_m */  in tegra20_osc_clk_init()
864 	clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,  in tegra20_osc_clk_init()
870 	clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",  in tegra20_osc_clk_init()
936 	/* switch coresite to clk_m, save off original source */  in tegra20_cpu_clock_suspend()