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/openbmc/libpldm/include/libpldm/
H A Dpldm_types.h14 uint8_t bit0 : 1; member
41 uint8_t bit0 : 1; member
63 uint8_t bit0 : 1; member
101 uint8_t bit0 : 1; member
/openbmc/u-boot/drivers/pch/
H A Dpch9.c33 * Note we don't need check bit0 here, because the Tunnel Creek in pch9_get_gpio_base()
34 * GPIO base address register bit0 is reserved (read returns 0), in pch9_get_gpio_base()
35 * while on the Ivybridge the bit0 is used to indicate it is an in pch9_get_gpio_base()
H A Dpch7.c49 * Note we don't need check bit0 here, because the Tunnel Creek in pch7_get_gpio_base()
50 * GPIO base address register bit0 is reserved (read returns 0), in pch7_get_gpio_base()
51 * while on the Ivybridge the bit0 is used to indicate it is an in pch7_get_gpio_base()
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
145 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/arch/x86/lib/
H A Di8254.c39 * To start a beep, set both bit0 and bit1 of port 0x61. in i8254_init()
40 * To stop it, clear both bit0 and bit1 of port 0x61. in i8254_init()
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
H A Dkwbimage-is2.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
H A Dkwbimage-ns2l.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
124 # bit0: 1, Window enabled
144 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/tools/
H A Dvybridimage.c42 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc() local
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
55 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
56 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
150 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 0x1, Window enabled
146 # bit0: 0x1, enable DDR init upon this register write
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
127 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 1, Window enabled
142 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
141 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
141 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg85 # bit0: 0, OPEn=OpenPage enabled
103 # bit0: 0, DRAM DLL enabled
143 # bit0: 1, Window enabled
151 # bit0: 1, Window enabled
186 # bit0: 1, enable DDR init upon this register write
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg96 # bit0: 0, OpenPage enabled
105 # bit0: 0, DDR DLL enabled
132 # bit0: 1, Window enabled
158 # bit0=1, enable DDR init upon this register write
H A Dkwbimage-memphis.cfg99 # bit0: 0, OpenPage enabled
108 # bit0: 0, DDR DLL enabled
147 # bit0: 1, Window enabled
176 # bit0=1, enable DDR init upon this register write
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 0x1, Window enabled
147 # bit0: 0x1, enable DDR init upon this register write
/openbmc/qemu/target/i386/emulate/
H A Dx86_emu.c935 uint32_t bit0, bit7; in exec_rol() local
940 bit0 = ((uint8_t)decode->op[0].val & 1); in exec_rol()
942 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); in exec_rol()
953 bit0 = (res & 1); in exec_rol()
955 SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0); in exec_rol()
961 uint32_t bit0, bit15; in exec_rol() local
966 bit0 = ((uint16_t)decode->op[0].val & 0x1); in exec_rol()
969 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); in exec_rol()
977 bit0 = (res & 0x1); in exec_rol()
980 SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0); in exec_rol()
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg91 # bit0: 0, OPEn=OpenPage enabled
112 # bit0: 0, DRAM DLL enabled
159 # bit0: 1, Window enabled
207 # bit0: 1, enable DDR init upon this register write

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