1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Google, Inc
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <pch.h>
9
10 #define GPIO_BASE 0x48
11 #define IO_BASE 0x4c
12 #define SBASE_ADDR 0x54
13
pch9_get_spi_base(struct udevice * dev,ulong * sbasep)14 static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
15 {
16 uint32_t sbase_addr;
17
18 dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
19 *sbasep = sbase_addr & 0xfffffe00;
20
21 return 0;
22 }
23
pch9_get_gpio_base(struct udevice * dev,u32 * gbasep)24 static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
25 {
26 u32 base;
27
28 /*
29 * GPIO_BASE moved to its current offset with ICH6, but prior to
30 * that it was unused (or undocumented). Check that it looks
31 * okay: not all ones or zeros.
32 *
33 * Note we don't need check bit0 here, because the Tunnel Creek
34 * GPIO base address register bit0 is reserved (read returns 0),
35 * while on the Ivybridge the bit0 is used to indicate it is an
36 * I/O space.
37 */
38 dm_pci_read_config32(dev, GPIO_BASE, &base);
39 if (base == 0x00000000 || base == 0xffffffff) {
40 debug("%s: unexpected BASE value\n", __func__);
41 return -ENODEV;
42 }
43
44 /*
45 * Okay, I guess we're looking at the right device. The actual
46 * GPIO registers are in the PCI device's I/O space, starting
47 * at the offset that we just read. Bit 0 indicates that it's
48 * an I/O address, not a memory address, so mask that off.
49 */
50 *gbasep = base & 1 ? base & ~3 : base & ~15;
51
52 return 0;
53 }
54
pch9_get_io_base(struct udevice * dev,u32 * iobasep)55 static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
56 {
57 u32 base;
58
59 dm_pci_read_config32(dev, IO_BASE, &base);
60 if (base == 0x00000000 || base == 0xffffffff) {
61 debug("%s: unexpected BASE value\n", __func__);
62 return -ENODEV;
63 }
64
65 *iobasep = base & 1 ? base & ~3 : base & ~15;
66
67 return 0;
68 }
69
70 static const struct pch_ops pch9_ops = {
71 .get_spi_base = pch9_get_spi_base,
72 .get_gpio_base = pch9_get_gpio_base,
73 .get_io_base = pch9_get_io_base,
74 };
75
76 static const struct udevice_id pch9_ids[] = {
77 { .compatible = "intel,pch9" },
78 { }
79 };
80
81 U_BOOT_DRIVER(pch9_drv) = {
82 .name = "intel-pch9",
83 .id = UCLASS_PCH,
84 .of_match = pch9_ids,
85 .ops = &pch9_ops,
86 };
87