xref: /openbmc/u-boot/drivers/pch/pch9.c (revision e8f80a5a)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
281afac12SSimon Glass /*
381afac12SSimon Glass  * Copyright (C) 2014 Google, Inc
481afac12SSimon Glass  */
581afac12SSimon Glass 
681afac12SSimon Glass #include <common.h>
781afac12SSimon Glass #include <dm.h>
881afac12SSimon Glass #include <pch.h>
981afac12SSimon Glass 
10ec2af6f8SBin Meng #define GPIO_BASE	0x48
114f106bc8SBin Meng #define IO_BASE		0x4c
1281afac12SSimon Glass #define SBASE_ADDR	0x54
1381afac12SSimon Glass 
pch9_get_spi_base(struct udevice * dev,ulong * sbasep)143e389d8bSBin Meng static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
1581afac12SSimon Glass {
1681afac12SSimon Glass 	uint32_t sbase_addr;
1781afac12SSimon Glass 
1881afac12SSimon Glass 	dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
1981afac12SSimon Glass 	*sbasep = sbase_addr & 0xfffffe00;
2081afac12SSimon Glass 
2181afac12SSimon Glass 	return 0;
2281afac12SSimon Glass }
2381afac12SSimon Glass 
pch9_get_gpio_base(struct udevice * dev,u32 * gbasep)24ec2af6f8SBin Meng static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
25ec2af6f8SBin Meng {
26ec2af6f8SBin Meng 	u32 base;
27ec2af6f8SBin Meng 
28ec2af6f8SBin Meng 	/*
29ec2af6f8SBin Meng 	 * GPIO_BASE moved to its current offset with ICH6, but prior to
30ec2af6f8SBin Meng 	 * that it was unused (or undocumented). Check that it looks
31ec2af6f8SBin Meng 	 * okay: not all ones or zeros.
32ec2af6f8SBin Meng 	 *
33ec2af6f8SBin Meng 	 * Note we don't need check bit0 here, because the Tunnel Creek
34ec2af6f8SBin Meng 	 * GPIO base address register bit0 is reserved (read returns 0),
35ec2af6f8SBin Meng 	 * while on the Ivybridge the bit0 is used to indicate it is an
36ec2af6f8SBin Meng 	 * I/O space.
37ec2af6f8SBin Meng 	 */
38ec2af6f8SBin Meng 	dm_pci_read_config32(dev, GPIO_BASE, &base);
39ec2af6f8SBin Meng 	if (base == 0x00000000 || base == 0xffffffff) {
40ec2af6f8SBin Meng 		debug("%s: unexpected BASE value\n", __func__);
41ec2af6f8SBin Meng 		return -ENODEV;
42ec2af6f8SBin Meng 	}
43ec2af6f8SBin Meng 
44ec2af6f8SBin Meng 	/*
45ec2af6f8SBin Meng 	 * Okay, I guess we're looking at the right device. The actual
46ec2af6f8SBin Meng 	 * GPIO registers are in the PCI device's I/O space, starting
47ec2af6f8SBin Meng 	 * at the offset that we just read. Bit 0 indicates that it's
48ec2af6f8SBin Meng 	 * an I/O address, not a memory address, so mask that off.
49ec2af6f8SBin Meng 	 */
50ec2af6f8SBin Meng 	*gbasep = base & 1 ? base & ~3 : base & ~15;
51ec2af6f8SBin Meng 
52ec2af6f8SBin Meng 	return 0;
53ec2af6f8SBin Meng }
54ec2af6f8SBin Meng 
pch9_get_io_base(struct udevice * dev,u32 * iobasep)554f106bc8SBin Meng static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
564f106bc8SBin Meng {
574f106bc8SBin Meng 	u32 base;
584f106bc8SBin Meng 
594f106bc8SBin Meng 	dm_pci_read_config32(dev, IO_BASE, &base);
604f106bc8SBin Meng 	if (base == 0x00000000 || base == 0xffffffff) {
614f106bc8SBin Meng 		debug("%s: unexpected BASE value\n", __func__);
624f106bc8SBin Meng 		return -ENODEV;
634f106bc8SBin Meng 	}
644f106bc8SBin Meng 
654f106bc8SBin Meng 	*iobasep = base & 1 ? base & ~3 : base & ~15;
664f106bc8SBin Meng 
674f106bc8SBin Meng 	return 0;
684f106bc8SBin Meng }
694f106bc8SBin Meng 
7081afac12SSimon Glass static const struct pch_ops pch9_ops = {
713e389d8bSBin Meng 	.get_spi_base	= pch9_get_spi_base,
72ec2af6f8SBin Meng 	.get_gpio_base	= pch9_get_gpio_base,
734f106bc8SBin Meng 	.get_io_base	= pch9_get_io_base,
7481afac12SSimon Glass };
7581afac12SSimon Glass 
7681afac12SSimon Glass static const struct udevice_id pch9_ids[] = {
7781afac12SSimon Glass 	{ .compatible = "intel,pch9" },
7881afac12SSimon Glass 	{ }
7981afac12SSimon Glass };
8081afac12SSimon Glass 
8181afac12SSimon Glass U_BOOT_DRIVER(pch9_drv) = {
8281afac12SSimon Glass 	.name		= "intel-pch9",
8381afac12SSimon Glass 	.id		= UCLASS_PCH,
8481afac12SSimon Glass 	.of_match	= pch9_ids,
8581afac12SSimon Glass 	.ops		= &pch9_ops,
8681afac12SSimon Glass };
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