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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxlnx,axi-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI PCIe Root Port Bridge
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,axi-pcie-host-1.00.a
20 maxItems: 1
23 maxItems: 1
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
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H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
[all …]
H A Dcdns-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe Host
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: cdns-pcie.yaml#
17 cdns,max-outbound-regions:
20 minimum: 1
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H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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/openbmc/linux/drivers/pci/controller/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 tristate "Aardvark PCIe controller"
13 Add support for Aardvark 64bit PCIe Host Controller. This
18 tristate "Altera PCIe controller"
21 Say Y here if you want to enable PCIe controller support on Altera
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
38 tristate "Apple PCIe controller"
44 Say Y here if you want to enable PCIe controller support on Apple
45 system-on-chips, like the Apple M1. This is required for the USB
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H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
43 #define CFG_ADDR_CFG_TYPE_1 1
56 #define CFG_RD_UR 1
73 #define OARR_SIZE_CFG_SHIFT 1
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
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H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
9 * Bits taken from Synopsys DesignWare Host controller driver and
10 * ARM PCI Host generic driver.
24 #include <linux/pci-ecam.h>
43 #define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
70 /* Root Port Interrupt FIFO Read Register 1 definitions */
94 * struct xilinx_pcie - PCIe port information
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H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip AXI PCIe Bridge host controller driver
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/pci-ecam.h>
26 /* PCIe Bridge Phy and Controller Phy offsets */
33 /* PCIe Bridge Phy Regs */
43 #define DMA_END_ENGINE_1_SHIFT 1
89 /* PCIe Master table init defines */
92 #define ATR0_PCIE_ATR_SIZE_SHIFT 1
98 /* PCIe AXI slave table init defines */
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H A Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
10 * Bits taken from Synopsys DesignWare Host controller driver and
11 * ARM PCI Host generic driver.
25 #include "pcie-rockchip.h"
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
35 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
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/openbmc/u-boot/cmd/
H A Dotp_info.h7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
33 { 0, 1, 0, "Disable Secure Boot" },
34 { 0, 1, 1, "Enable Secure Boot" },
35 { 1, 1, 0, "Disable boot from eMMC" },
36 { 1, 1, 1, "Enable boot from eMMC" },
37 { 2, 1, 0, "Disable Boot from debug SPI" },
38 { 2, 1, 1, "Enable Boot from debug SPI" },
39 { 3, 1, 0, "Enable ARM CM3" },
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/openbmc/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
21 * mobiveil_pcie_sel_page - routine to access paged register
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dimg,boston.dts1 /dts-v1/;
3 #include <dt-bindings/clock/boston-clock.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
14 stdout-path = &uart0;
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpcie_xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXI Bridge for PCI Express Driver
15 * struct xilinx_pcie - Xilinx PCIe controller state
27 * pcie_xilinx_link_up() - Check whether the PCIe link is up
28 * @pcie: Pointer to the PCI controller state
30 * Checks whether the PCIe link for the given device is up or down.
34 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) in pcie_xilinx_link_up() argument
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
42 * pcie_xilinx_config_address() - Calculate the address of a config access
44 * @bdf: Identifies the PCIe device to access
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/openbmc/linux/arch/mips/boot/dts/img/
H A Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
[all …]
/openbmc/openbmc/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/
H A Dibm.json19 "number_id": 1,
65 "Disable Auto Boot from VUART2 over PCIE": true,
84 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
89 "CPU/AXI clock ratio": { "value": "2:1" },
94 "Enable PCIe EHCI": { "value": false },
97 "Enable dedicate PCIe RC reset": { "value": false },
99 "Internal bridge speed selection": { "value": "1x" },
105 "Disable debug 1": { "value": false },
110 "Enable boot SPI 3B address mode auto-clear": { "value": false },
115 "Enable host SPI ABR": { "value": false },
[all …]
H A Dips.json19 "number_id": 1,
72 "Disable Auto Boot from VUART2 over PCIE": true,
91 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
96 "CPU/AXI clock ratio": { "value": "2:1" },
101 "Enable PCIe EHCI": { "value": false },
104 "Enable dedicate PCIe RC reset": { "value": false },
106 "Internal bridge speed selection": { "value": "1x" },
112 "Disable debug 1": { "value": false },
117 "Enable boot SPI 3B address mode auto-clear": { "value": false },
122 "Enable host SPI ABR": { "value": false },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
16 AXI memory resource.
17 5th optional memory resource shall be the host
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/openbmc/qemu/hw/pci-host/
H A Dxilinx-pcie.c2 * Xilinx PCIe host controller emulation.
25 #include "hw/qdev-properties.h"
27 #include "hw/pci-host/xilinx-pcie.h"
36 #define ROOTCFG_INTMASK_INTX (1 << 16)
38 #define ROOTCFG_INTMASK_MSI (1 << 17)
43 #define ROOTCFG_PSCR_LINK_UP (1 << 11)
48 #define ROOTCFG_RPSCR_BRIDGEEN (1 << 0)
50 #define ROOTCFG_RPSCR_INTNEMPTY (1 << 18)
52 #define ROOTCFG_RPSCR_INTOVF (1 << 19)
54 /* Root Port Interrupt FIFO Read Register 1 */
[all …]
/openbmc/linux/include/dt-bindings/memory/
H A Dtegra186-mc.h117 /* PCIE reads */
119 /* High-definition audio (HDA) reads */
121 /* Host channel data reads */
126 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
129 /* PCIE writes */
131 /* High-definition audio (HDA) writes */
133 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
199 /* 3D, ltcx reads instance 1 */
201 /* 3D, ltcx writes instance 1 */
203 /* AXI Switch read client */
[all …]
/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-host.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
[all …]
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe Endpoint controller driver
18 #include <linux/phy/pcie.h>
26 #include "pcie-designware.h"
61 #define PARF_INT_ALL_LINK_DOWN BIT(1)
84 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
92 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
97 #define PARF_MSTR_AXI_CLK_EN BIT(1)
116 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
122 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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