1029ab5eaSThierry Reding #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H 2029ab5eaSThierry Reding #define DT_BINDINGS_MEMORY_TEGRA186_MC_H 3029ab5eaSThierry Reding 4029ab5eaSThierry Reding /* special clients */ 5029ab5eaSThierry Reding #define TEGRA186_SID_INVALID 0x00 6029ab5eaSThierry Reding #define TEGRA186_SID_PASSTHROUGH 0x7f 7029ab5eaSThierry Reding 8029ab5eaSThierry Reding /* host1x clients */ 9029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X 0x01 10029ab5eaSThierry Reding #define TEGRA186_SID_CSI 0x02 11029ab5eaSThierry Reding #define TEGRA186_SID_VIC 0x03 12029ab5eaSThierry Reding #define TEGRA186_SID_VI 0x04 13029ab5eaSThierry Reding #define TEGRA186_SID_ISP 0x05 14029ab5eaSThierry Reding #define TEGRA186_SID_NVDEC 0x06 15029ab5eaSThierry Reding #define TEGRA186_SID_NVENC 0x07 16029ab5eaSThierry Reding #define TEGRA186_SID_NVJPG 0x08 17029ab5eaSThierry Reding #define TEGRA186_SID_NVDISPLAY 0x09 18029ab5eaSThierry Reding #define TEGRA186_SID_TSEC 0x0a 19029ab5eaSThierry Reding #define TEGRA186_SID_TSECB 0x0b 20029ab5eaSThierry Reding #define TEGRA186_SID_SE 0x0c 21029ab5eaSThierry Reding #define TEGRA186_SID_SE1 0x0d 22029ab5eaSThierry Reding #define TEGRA186_SID_SE2 0x0e 23029ab5eaSThierry Reding #define TEGRA186_SID_SE3 0x0f 24029ab5eaSThierry Reding 25029ab5eaSThierry Reding /* GPU clients */ 26029ab5eaSThierry Reding #define TEGRA186_SID_GPU 0x10 27029ab5eaSThierry Reding 28029ab5eaSThierry Reding /* other SoC clients */ 29029ab5eaSThierry Reding #define TEGRA186_SID_AFI 0x11 30029ab5eaSThierry Reding #define TEGRA186_SID_HDA 0x12 31029ab5eaSThierry Reding #define TEGRA186_SID_ETR 0x13 32029ab5eaSThierry Reding #define TEGRA186_SID_EQOS 0x14 33029ab5eaSThierry Reding #define TEGRA186_SID_UFSHC 0x15 34029ab5eaSThierry Reding #define TEGRA186_SID_AON 0x16 35029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC4 0x17 36029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC3 0x18 37029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC2 0x19 38029ab5eaSThierry Reding #define TEGRA186_SID_SDMMC1 0x1a 39029ab5eaSThierry Reding #define TEGRA186_SID_XUSB_HOST 0x1b 40029ab5eaSThierry Reding #define TEGRA186_SID_XUSB_DEV 0x1c 41029ab5eaSThierry Reding #define TEGRA186_SID_SATA 0x1d 42029ab5eaSThierry Reding #define TEGRA186_SID_APE 0x1e 43029ab5eaSThierry Reding #define TEGRA186_SID_SCE 0x1f 44029ab5eaSThierry Reding 45029ab5eaSThierry Reding /* GPC DMA clients */ 46029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_0 0x20 47029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_1 0x21 48029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_2 0x22 49029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_3 0x23 50029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_4 0x24 51029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_5 0x25 52029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_6 0x26 53029ab5eaSThierry Reding #define TEGRA186_SID_GPCDMA_7 0x27 54029ab5eaSThierry Reding 55029ab5eaSThierry Reding /* APE DMA clients */ 56029ab5eaSThierry Reding #define TEGRA186_SID_APE_1 0x28 57029ab5eaSThierry Reding #define TEGRA186_SID_APE_2 0x29 58029ab5eaSThierry Reding 59029ab5eaSThierry Reding /* camera RTCPU */ 60029ab5eaSThierry Reding #define TEGRA186_SID_RCE 0x2a 61029ab5eaSThierry Reding 62029ab5eaSThierry Reding /* camera RTCPU on host1x address space */ 63029ab5eaSThierry Reding #define TEGRA186_SID_RCE_1X 0x2b 64029ab5eaSThierry Reding 65029ab5eaSThierry Reding /* APE DMA clients */ 66029ab5eaSThierry Reding #define TEGRA186_SID_APE_3 0x2c 67029ab5eaSThierry Reding 68029ab5eaSThierry Reding /* camera RTCPU running on APE */ 69029ab5eaSThierry Reding #define TEGRA186_SID_APE_CAM 0x2d 70029ab5eaSThierry Reding #define TEGRA186_SID_APE_CAM_1X 0x2e 71029ab5eaSThierry Reding 72029ab5eaSThierry Reding /* 73029ab5eaSThierry Reding * The BPMP has its SID value hardcoded in the firmware. Changing it requires 74029ab5eaSThierry Reding * considerable effort. 75029ab5eaSThierry Reding */ 76029ab5eaSThierry Reding #define TEGRA186_SID_BPMP 0x32 77029ab5eaSThierry Reding 78029ab5eaSThierry Reding /* for SMMU tests */ 79029ab5eaSThierry Reding #define TEGRA186_SID_SMMU_TEST 0x33 80029ab5eaSThierry Reding 81029ab5eaSThierry Reding /* host1x virtualization channels */ 82029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX0 0x38 83029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX1 0x39 84029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX2 0x3a 85029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX3 0x3b 86029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX4 0x3c 87029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX5 0x3d 88029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX6 0x3e 89029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_CTX7 0x3f 90029ab5eaSThierry Reding 91029ab5eaSThierry Reding /* host1x command buffers */ 92029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM0 0x40 93029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM1 0x41 94029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM2 0x42 95029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM3 0x43 96029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM4 0x44 97029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM5 0x45 98029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM6 0x46 99029ab5eaSThierry Reding #define TEGRA186_SID_HOST1X_VM7 0x47 100029ab5eaSThierry Reding 101029ab5eaSThierry Reding /* SE data buffers */ 102029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM0 0x48 103029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM1 0x49 104029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM2 0x4a 105029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM3 0x4b 106029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM4 0x4c 107029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM5 0x4d 108029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM6 0x4e 109029ab5eaSThierry Reding #define TEGRA186_SID_SE_VM7 0x4f 110029ab5eaSThierry Reding 11196b0239bSThierry Reding /* 11296b0239bSThierry Reding * memory client IDs 11396b0239bSThierry Reding */ 11496b0239bSThierry Reding 11596b0239bSThierry Reding /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 11696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_PTCR 0x00 11796b0239bSThierry Reding /* PCIE reads */ 11896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AFIR 0x0e 11996b0239bSThierry Reding /* High-definition audio (HDA) reads */ 12096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_HDAR 0x15 12196b0239bSThierry Reding /* Host channel data reads */ 12296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 12396b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c 12496b0239bSThierry Reding /* SATA reads */ 12596b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SATAR 0x1f 12696b0239bSThierry Reding /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 12796b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 12896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b 12996b0239bSThierry Reding /* PCIE writes */ 13096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AFIW 0x31 13196b0239bSThierry Reding /* High-definition audio (HDA) writes */ 13296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_HDAW 0x35 13396b0239bSThierry Reding /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 13496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 13596b0239bSThierry Reding /* SATA writes */ 13696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SATAW 0x3d 13796b0239bSThierry Reding /* ISP Read client for Crossbar A */ 13896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 13996b0239bSThierry Reding /* ISP Write client for Crossbar A */ 14096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 14196b0239bSThierry Reding /* ISP Write client Crossbar B */ 14296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 14396b0239bSThierry Reding /* XUSB reads */ 14496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a 14596b0239bSThierry Reding /* XUSB_HOST writes */ 14696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b 14796b0239bSThierry Reding /* XUSB reads */ 14896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c 14996b0239bSThierry Reding /* XUSB_DEV writes */ 15096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d 15196b0239bSThierry Reding /* TSEC Memory Return Data Client Description */ 15296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 15396b0239bSThierry Reding /* TSEC Memory Write Client Description */ 15496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 15596b0239bSThierry Reding /* 3D, ltcx reads instance 0 */ 15696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 15796b0239bSThierry Reding /* 3D, ltcx writes instance 0 */ 15896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 15996b0239bSThierry Reding /* sdmmca memory read client */ 16096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 16196b0239bSThierry Reding /* sdmmcbmemory read client */ 16296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 16396b0239bSThierry Reding /* sdmmc memory read client */ 16496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 16596b0239bSThierry Reding /* sdmmcd memory read client */ 16696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 16796b0239bSThierry Reding /* sdmmca memory write client */ 16896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 16996b0239bSThierry Reding /* sdmmcb memory write client */ 17096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 17196b0239bSThierry Reding /* sdmmc memory write client */ 17296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 17396b0239bSThierry Reding /* sdmmcd memory write client */ 17496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 17596b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c 17696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d 17796b0239bSThierry Reding /* VI Write client */ 17896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_VIW 0x72 17996b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 18096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 18196b0239bSThierry Reding /* Audio Processing (APE) engine reads */ 18296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_APER 0x7a 18396b0239bSThierry Reding /* Audio Processing (APE) engine writes */ 18496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_APEW 0x7b 18596b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e 18696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f 18796b0239bSThierry Reding /* SE Memory Return Data Client Description */ 18896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SESRD 0x80 18996b0239bSThierry Reding /* SE Memory Write Client Description */ 19096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SESWR 0x81 19196b0239bSThierry Reding /* ETR reads */ 19296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_ETRR 0x84 19396b0239bSThierry Reding /* ETR writes */ 19496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_ETRW 0x85 19596b0239bSThierry Reding /* TSECB Memory Return Data Client Description */ 19696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 19796b0239bSThierry Reding /* TSECB Memory Write Client Description */ 19896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 19996b0239bSThierry Reding /* 3D, ltcx reads instance 1 */ 20096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 20196b0239bSThierry Reding /* 3D, ltcx writes instance 1 */ 20296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 20396b0239bSThierry Reding /* AXI Switch read client */ 20496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AXISR 0x8c 20596b0239bSThierry Reding /* AXI Switch write client */ 20696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AXISW 0x8d 20796b0239bSThierry Reding /* EQOS read client */ 20896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e 20996b0239bSThierry Reding /* EQOS write client */ 21096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f 21196b0239bSThierry Reding /* UFSHC read client */ 21296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 21396b0239bSThierry Reding /* UFSHC write client */ 21496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 21596b0239bSThierry Reding /* NVDISPLAY read client */ 21696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 21796b0239bSThierry Reding /* BPMP read client */ 21896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 21996b0239bSThierry Reding /* BPMP write client */ 22096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 22196b0239bSThierry Reding /* BPMPDMA read client */ 22296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 22396b0239bSThierry Reding /* BPMPDMA write client */ 22496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 22596b0239bSThierry Reding /* AON read client */ 22696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AONR 0x97 22796b0239bSThierry Reding /* AON write client */ 22896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AONW 0x98 22996b0239bSThierry Reding /* AONDMA read client */ 23096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 23196b0239bSThierry Reding /* AONDMA write client */ 23296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a 23396b0239bSThierry Reding /* SCE read client */ 23496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SCER 0x9b 23596b0239bSThierry Reding /* SCE write client */ 23696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SCEW 0x9c 23796b0239bSThierry Reding /* SCEDMA read client */ 23896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d 23996b0239bSThierry Reding /* SCEDMA write client */ 24096b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e 24196b0239bSThierry Reding /* APEDMA read client */ 24296b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f 24396b0239bSThierry Reding /* APEDMA write client */ 24496b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 24596b0239bSThierry Reding /* NVDISPLAY read client instance 2 */ 24696b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 24796b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 24896b0239bSThierry Reding #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 24996b0239bSThierry Reding 250029ab5eaSThierry Reding #endif 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