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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,armv7m-systick.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv7M System Timer
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
13 description: ARMv7-M includes a system timer, known as SysTick.
17 const: arm,armv7m-systick
25 clock-frequency: true
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/openbmc/qemu/include/hw/arm/
H A Darmv7m.h2 * ARMv7M CPU object
20 #define TYPE_BITBAND "ARM-bitband-memory"
34 #define TYPE_ARMV7M "armv7m"
35 OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
39 /* ARMv7M container object.
44 * + Property "cpu-type": CPU type to instantiate
45 * + Property "num-irq": number of external IRQ lines
46 * + Property "num-prio-bits": number of priority bits in the NVIC
48 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
51 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
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/openbmc/qemu/hw/arm/
H A Darmv7m.c2 * ARMV7M System emulation.
4 * Copyright (c) 2006-2007 CodeSourcery.
11 #include "hw/arm/armv7m.h"
16 #include "hw/qdev-properties.h"
17 #include "hw/qdev-clock.h"
20 #include "qemu/error-report.h"
25 #include "target/arm/cpu-features.h"
26 #include "target/arm/cpu-qom.h"
34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()
49 addr = bitband_addr(s, offset) & (-size); in bitband_read()
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H A Dmsf2-soc.c4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
28 #include "exec/address-spaces.h"
29 #include "hw/char/serial-mm.h"
30 #include "hw/arm/msf2-soc.h"
32 #include "hw/qdev-clock.h"
66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()
68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()
70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()
73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()
76 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); in m2sxxx_soc_initfn()
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H A Dmps2.c17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
19 * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
20 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
24 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
31 #include "qemu/error-report.h"
33 #include "hw/arm/armv7m.h"
34 #include "hw/or-irq.h"
36 #include "exec/address-spaces.h"
38 #include "hw/qdev-properties.h"
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H A Dnrf51_soc.c8 * the COPYING file in the top-level directory.
15 #include "hw/qdev-clock.h"
24 * are supported in the future, add a sub-class of NRF51SoC for
47 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", in clock_write()
64 if (!s->board_memory) { in nrf51_soc_realize()
73 if (clock_has_source(s->sysclk)) { in nrf51_soc_realize()
77 /* This clock doesn't need migration because it is fixed-frequency */ in nrf51_soc_realize()
78 clock_set_hz(s->sysclk, HCLK_FRQ); in nrf51_soc_realize()
79 qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk); in nrf51_soc_realize()
81 * This SoC has no systick device, so don't connect refclk. in nrf51_soc_realize()
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H A Darmsse.c23 #include "hw/arm/armsse-version.h"
26 #include "hw/qdev-clock.h"
29 * The SSE-300 puts some devices in different places to the
30 * SSE-200 (and original IoTKit). We use an array of these structs
36 #define NO_IRQ -1
37 #define NO_PPC -1
54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
115 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
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H A Dstellaris.c12 #include "hw/core/split-irq.h"
22 #include "exec/address-spaces.h"
24 #include "hw/arm/armv7m.h"
28 #include "hw/watchdog/cmsdk-apb-watchdog.h"
31 #include "hw/timer/stellaris-gptm.h"
32 #include "hw/qdev-clock.h"
66 #define TYPE_STELLARIS_SYS "stellaris-sys"
87 /* Properties (all read-only registers) */
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
152 uint32_t did0 = s->did0; in ssys_board_class()
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/openbmc/u-boot/arch/arm/dts/
H A Darmv7-m.dtsi4 nvic: interrupt-controller@e000e100 {
5 compatible = "arm,armv7m-nvic";
6 interrupt-controller;
7 #interrupt-cells = <1>;
11 systick: timer@e000e010 { label
12 compatible = "arm,armv7m-systick";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 interrupt-parent = <&nvic>;
/openbmc/linux/arch/arm/boot/dts/
H A Darmv7-m.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 nvic: interrupt-controller@e000e100 {
4 compatible = "arm,armv7m-nvic";
5 interrupt-controller;
6 #interrupt-cells = <1>;
10 systick: timer@e000e010 { label
11 compatible = "arm,armv7m-systick";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 compatible = "simple-bus";
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/openbmc/qemu/include/hw/timer/
H A Darmv7m_systick.h2 * ARMv7M SysTick timer
4 * Copyright (c) 2006-2007 CodeSourcery.
22 OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
/openbmc/qemu/hw/timer/
H A Darmv7m_systick.c2 * ARMv7M SysTick timer
4 * Copyright (c) 2006-2007 CodeSourcery.
17 #include "hw/qdev-clock.h"
31 #define SYSCALIB_TENMS ((1U << 24) - 1)
39 if (s->control & SYSTICK_CLKSOURCE) { in systick_set_period_from_clock()
40 ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); in systick_set_period_from_clock()
42 ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); in systick_set_period_from_clock()
52 s->control |= SYSTICK_COUNTFLAG; in systick_timer_tick()
53 if (s->control & SYSTICK_TICKINT) { in systick_timer_tick()
54 /* Tell the NVIC to pend the SysTick exception */ in systick_timer_tick()
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/openbmc/linux/drivers/clocksource/
H A Darmv7m_systick.c1 // SPDX-License-Identifier: GPL-2.0-only
34 pr_warn("system-timer: invalid base address\n"); in system_timer_of_register()
35 return -ENXIO; in system_timer_of_register()
38 ret = of_property_read_u32(np, "clock-frequency", &rate); in system_timer_of_register()
52 ret = -EINVAL; in system_timer_of_register()
85 TIMER_OF_DECLARE(arm_systick, "arm,armv7m-systick",
/openbmc/linux/arch/arm/kernel/
H A Dentry-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-v7m.S
7 * Low-level vector interface routines for the ARMv7-M architecture
14 #include "entry-header.S"
17 #error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
77 @ registers r0-r3 and r12 are automatically restored on exception
78 @ return. r4-r7 were not clobbered in v7m_exception_entry so for
79 @ correctness they don't need to be restored. So only r8-r11 must be
80 @ restored here. The easiest way to do so is to restore r0-r7, too.
81 ldmia sp!, {r0-r11}
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/openbmc/qemu/include/hw/intc/
H A Darmv7m_nvic.h2 * ARMv7M NVIC object
13 #include "target/arm/cpu-qom.h"
27 /* Exception priorities can range from -3 to 255; only the unmodifiable
48 * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
54 * Entries in sec_vectors[] for non-banked exception numbers are unused.
66 * - vectpending
67 * - vectpending_is_secure
68 * - exception_prio
69 * - vectpending_prio
91 * @secure: false for non-banked exceptions or for the nonsecure
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/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c4 * Copyright (c) 2006-2007 CodeSourcery.
9 * The ARMv7M System controller is fairly tightly tied in with the
20 #include "hw/qdev-properties.h"
24 #include "target/arm/cpu-features.h"
25 #include "exec/exec-all.h"
33 * the num-irq property counts the number of external IRQ lines
44 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
56 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
62 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
71 if (qemu_irq_is_connected(s->sysresetreq)) { in signal_sysresetreq()
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/openbmc/
Dopengrok1.0.log1 2025-01-23 03:00:35.620-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-01-23 03:00:35.747-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-01-22 03:00:43.118-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-01-22 03:00:43.231-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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/openbmc/linux/
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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