Lines Matching +full:armv7m +full:- +full:systick
12 #include "hw/core/split-irq.h"
22 #include "exec/address-spaces.h"
24 #include "hw/arm/armv7m.h"
28 #include "hw/watchdog/cmsdk-apb-watchdog.h"
31 #include "hw/timer/stellaris-gptm.h"
32 #include "hw/qdev-clock.h"
66 #define TYPE_STELLARIS_SYS "stellaris-sys"
87 /* Properties (all read-only registers) */
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
152 uint32_t did0 = s->did0; in ssys_board_class()
178 return s->did0; in ssys_read()
180 return s->did1; in ssys_read()
182 return s->dc0; in ssys_read()
184 return s->dc1; in ssys_read()
186 return s->dc2; in ssys_read()
188 return s->dc3; in ssys_read()
190 return s->dc4; in ssys_read()
192 return s->pborctl; in ssys_read()
194 return s->ldopctl; in ssys_read()
202 return s->int_status; in ssys_read()
204 return s->int_mask; in ssys_read()
206 return s->int_status & s->int_mask; in ssys_read()
208 return s->resc; in ssys_read()
210 return s->rcc; in ssys_read()
214 xtal = (s->rcc >> 6) & 0xf; in ssys_read()
225 return s->rcc2; in ssys_read()
227 return s->rcgc[0]; in ssys_read()
229 return s->rcgc[1]; in ssys_read()
231 return s->rcgc[2]; in ssys_read()
233 return s->scgc[0]; in ssys_read()
235 return s->scgc[1]; in ssys_read()
237 return s->scgc[2]; in ssys_read()
239 return s->dcgc[0]; in ssys_read()
241 return s->dcgc[1]; in ssys_read()
243 return s->dcgc[2]; in ssys_read()
245 return s->clkvclr; in ssys_read()
247 return s->ldoarst; in ssys_read()
249 return s->user0; in ssys_read()
251 return s->user1; in ssys_read()
261 return (s->rcc2 >> 31) & 0x1; in ssys_use_rcc2()
267 * from migration post-load.
278 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); in ssys_calculate_system_clock()
280 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1); in ssys_calculate_system_clock()
282 clock_set_ns(s->sysclk, period_ns); in ssys_calculate_system_clock()
284 clock_propagate(s->sysclk); in ssys_calculate_system_clock()
295 s->pborctl = value & 0xffff; in ssys_write()
298 s->ldopctl = value & 0x1f; in ssys_write()
306 s->int_mask = value & 0x7f; in ssys_write()
309 s->int_status &= ~value; in ssys_write()
312 s->resc = value & 0x3f; in ssys_write()
315 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
317 s->int_status |= (1 << 6); in ssys_write()
319 s->rcc = value; in ssys_write()
327 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { in ssys_write()
329 s->int_status |= (1 << 6); in ssys_write()
331 s->rcc2 = value; in ssys_write()
335 s->rcgc[0] = value; in ssys_write()
338 s->rcgc[1] = value; in ssys_write()
341 s->rcgc[2] = value; in ssys_write()
344 s->scgc[0] = value; in ssys_write()
347 s->scgc[1] = value; in ssys_write()
350 s->scgc[2] = value; in ssys_write()
353 s->dcgc[0] = value; in ssys_write()
356 s->dcgc[1] = value; in ssys_write()
359 s->dcgc[2] = value; in ssys_write()
362 s->clkvclr = value; in ssys_write()
365 s->ldoarst = value; in ssys_write()
384 s->pborctl = 0x7ffd; in stellaris_sys_reset_enter()
385 s->rcc = 0x078e3ac0; in stellaris_sys_reset_enter()
388 s->rcc2 = 0; in stellaris_sys_reset_enter()
390 s->rcc2 = 0x07802810; in stellaris_sys_reset_enter()
392 s->rcgc[0] = 1; in stellaris_sys_reset_enter()
393 s->scgc[0] = 1; in stellaris_sys_reset_enter()
394 s->dcgc[0] = 1; in stellaris_sys_reset_enter()
436 /* No field for sysclk -- handled in post-load instead */
459 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); in stellaris_sys_instance_init()
460 sysbus_init_mmio(sbd, &s->iomem); in stellaris_sys_instance_init()
461 sysbus_init_irq(sbd, &s->irq); in stellaris_sys_instance_init()
462 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); in stellaris_sys_instance_init()
470 #define TYPE_STELLARIS_I2C "stellaris-i2c"
503 return s->msa; in stellaris_i2c_read()
506 return s->mcs | STELLARIS_I2C_MCS_IDLE; in stellaris_i2c_read()
508 return s->mdr; in stellaris_i2c_read()
510 return s->mtpr; in stellaris_i2c_read()
512 return s->mimr; in stellaris_i2c_read()
514 return s->mris; in stellaris_i2c_read()
516 return s->mris & s->mimr; in stellaris_i2c_read()
518 return s->mcr; in stellaris_i2c_read()
530 level = (s->mris & s->mimr) != 0; in stellaris_i2c_update()
531 qemu_set_irq(s->irq, level); in stellaris_i2c_update()
541 s->msa = value & 0xff; in stellaris_i2c_write()
544 if ((s->mcr & 0x10) == 0) { in stellaris_i2c_write()
549 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { in stellaris_i2c_write()
550 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { in stellaris_i2c_write()
551 s->mcs |= STELLARIS_I2C_MCS_ARBLST; in stellaris_i2c_write()
553 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; in stellaris_i2c_write()
554 s->mcs |= STELLARIS_I2C_MCS_BUSBSY; in stellaris_i2c_write()
558 if (!i2c_bus_busy(s->bus) in stellaris_i2c_write()
559 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { in stellaris_i2c_write()
560 s->mcs |= STELLARIS_I2C_MCS_ERROR; in stellaris_i2c_write()
563 s->mcs &= ~STELLARIS_I2C_MCS_ERROR; in stellaris_i2c_write()
567 if (s->msa & 1) { in stellaris_i2c_write()
569 s->mdr = i2c_recv(s->bus); in stellaris_i2c_write()
572 i2c_send(s->bus, s->mdr); in stellaris_i2c_write()
575 s->mris |= 1; in stellaris_i2c_write()
579 i2c_end_transfer(s->bus); in stellaris_i2c_write()
580 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; in stellaris_i2c_write()
584 s->mdr = value & 0xff; in stellaris_i2c_write()
587 s->mtpr = value & 0xff; in stellaris_i2c_write()
590 s->mimr = 1; in stellaris_i2c_write()
593 s->mris &= ~value; in stellaris_i2c_write()
604 s->mcr = value & 0x31; in stellaris_i2c_write()
617 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) in stellaris_i2c_reset_enter()
618 i2c_end_transfer(s->bus); in stellaris_i2c_reset_enter()
625 s->msa = 0; in stellaris_i2c_reset_hold()
626 s->mcs = 0; in stellaris_i2c_reset_hold()
627 s->mdr = 0; in stellaris_i2c_reset_hold()
628 s->mtpr = 1; in stellaris_i2c_reset_hold()
629 s->mimr = 0; in stellaris_i2c_reset_hold()
630 s->mris = 0; in stellaris_i2c_reset_hold()
631 s->mcr = 0; in stellaris_i2c_reset_hold()
670 sysbus_init_irq(sbd, &s->irq); in stellaris_i2c_init()
672 s->bus = bus; in stellaris_i2c_init()
674 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, in stellaris_i2c_init()
676 sysbus_init_mmio(sbd, &s->iomem); in stellaris_i2c_init()
693 #define TYPE_STELLARIS_ADC "stellaris-adc"
723 tail = s->fifo[n].state & 0xf; in stellaris_adc_fifo_read()
724 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { in stellaris_adc_fifo_read()
725 s->ustat |= 1 << n; in stellaris_adc_fifo_read()
727 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); in stellaris_adc_fifo_read()
728 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; in stellaris_adc_fifo_read()
729 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) in stellaris_adc_fifo_read()
730 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; in stellaris_adc_fifo_read()
732 return s->fifo[n].data[tail]; in stellaris_adc_fifo_read()
742 head = (s->fifo[n].state >> 4) & 0xf; in stellaris_adc_fifo_write()
743 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { in stellaris_adc_fifo_write()
744 s->ostat |= 1 << n; in stellaris_adc_fifo_write()
747 s->fifo[n].data[head] = value; in stellaris_adc_fifo_write()
749 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; in stellaris_adc_fifo_write()
750 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); in stellaris_adc_fifo_write()
751 if ((s->fifo[n].state & 0xf) == head) in stellaris_adc_fifo_write()
752 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; in stellaris_adc_fifo_write()
761 level = (s->ris & s->im & (1 << n)) != 0; in stellaris_adc_update()
762 qemu_set_irq(s->irq[n], level); in stellaris_adc_update()
772 if ((s->actss & (1 << n)) == 0) { in stellaris_adc_trigger()
776 if (((s->emux >> (n * 4)) & 0xff) != 5) { in stellaris_adc_trigger()
782 s->noise = s->noise * 314159 + 1; in stellaris_adc_trigger()
784 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); in stellaris_adc_trigger()
785 s->ris |= (1 << n); in stellaris_adc_trigger()
796 s->ssmux[n] = 0; in stellaris_adc_reset_hold()
797 s->ssctl[n] = 0; in stellaris_adc_reset_hold()
798 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; in stellaris_adc_reset_hold()
810 n = (offset - 0x40) >> 5; in stellaris_adc_read()
813 return s->ssmux[n]; in stellaris_adc_read()
815 return s->ssctl[n]; in stellaris_adc_read()
819 return s->fifo[n].state; in stellaris_adc_read()
826 return s->actss; in stellaris_adc_read()
828 return s->ris; in stellaris_adc_read()
830 return s->im; in stellaris_adc_read()
832 return s->ris & s->im; in stellaris_adc_read()
834 return s->ostat; in stellaris_adc_read()
836 return s->emux; in stellaris_adc_read()
838 return s->ustat; in stellaris_adc_read()
840 return s->sspri; in stellaris_adc_read()
842 return s->sac; in stellaris_adc_read()
858 n = (offset - 0x40) >> 5; in stellaris_adc_write()
861 s->ssmux[n] = value & 0x33333333; in stellaris_adc_write()
869 s->ssctl[n] = value; in stellaris_adc_write()
877 s->actss = value & 0xf; in stellaris_adc_write()
880 s->im = value; in stellaris_adc_write()
883 s->ris &= ~value; in stellaris_adc_write()
886 s->ostat &= ~value; in stellaris_adc_write()
889 s->emux = value; in stellaris_adc_write()
892 s->ustat &= ~value; in stellaris_adc_write()
895 s->sspri = value; in stellaris_adc_write()
901 s->sac = value; in stellaris_adc_write()
958 sysbus_init_irq(sbd, &s->irq[n]); in stellaris_adc_init()
961 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, in stellaris_adc_init()
963 sysbus_init_mmio(sbd, &s->iomem); in stellaris_adc_init()
1053 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; in stellaris_init()
1054 sram_size = ((board->dc0 >> 18) + 1) * 1024; in stellaris_init()
1069 * Create the system-registers object early, because we will in stellaris_init()
1077 * Generate a MAC address now, if there isn't a matching -nic for it. in stellaris_init()
1081 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a)); in stellaris_init()
1090 qdev_prop_set_uint32(ssys_dev, "did0", board->did0); in stellaris_init()
1091 qdev_prop_set_uint32(ssys_dev, "did1", board->did1); in stellaris_init()
1092 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0); in stellaris_init()
1093 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1); in stellaris_init()
1094 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2); in stellaris_init()
1095 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3); in stellaris_init()
1096 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); in stellaris_init()
1101 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); in stellaris_init()
1102 qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); in stellaris_init()
1103 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); in stellaris_init()
1104 qdev_prop_set_bit(nvic, "enable-bitband", true); in stellaris_init()
1107 /* This SoC does not connect the systick reference clock */ in stellaris_init()
1117 if (board->dc1 & (1 << 16)) { in stellaris_init()
1129 if (board->dc2 & (0x10000 << i)) { in stellaris_init()
1146 if (board->dc1 & (1 << 3)) { /* watchdog present */ in stellaris_init()
1163 if (board->dc4 & (1 << i)) { in stellaris_init()
1174 if (board->dc2 & (1 << 12)) { in stellaris_init()
1178 if (board->peripherals & BP_OLED_I2C) { in stellaris_init()
1184 if (board->dc2 & (1 << i)) { in stellaris_init()
1196 if (board->dc2 & (1 << 4)) { in stellaris_init()
1199 if (board->peripherals & BP_OLED_SSI) { in stellaris_init()
1218 * - GPIO pin D0 is wired to the active-low SD card chip select in stellaris_init()
1219 * - GPIO pin A3 is wired to the active-low OLED chip select in stellaris_init()
1220 * - The SoC wiring of the PL061 "auxiliary function" for A3 is in stellaris_init()
1223 * transmits a frame, so it can work as a chip-select signal. in stellaris_init()
1224 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx in stellaris_init()
1226 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx in stellaris_init()
1227 * and the OLED display-data-in in stellaris_init()
1228 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED in stellaris_init()
1229 * serial-clock input in stellaris_init()
1231 * to make pins A2, A3, A5 aux-function, so they are connected in stellaris_init()
1235 * as aux-function, but leaves A3 as a software-controlled GPIO in stellaris_init()
1236 * line. It asserts the SD card chip-select by using the PL061 in stellaris_init()
1239 * usual, but because A3 is not set to aux-function this is not in stellaris_init()
1243 * - GPIO pin D0 is wired to the active-low SD card chip select, in stellaris_init()
1244 * and also to the OLED chip-select which is implemented in stellaris_init()
1245 * as *active-high* in stellaris_init()
1246 * - SSI controller signals go to the devices regardless of in stellaris_init()
1247 * whether the guest programs A2, A4, A5 as aux-function or not in stellaris_init()
1255 * never gets the chip-select assert it needs. We work around in stellaris_init()
1261 * - Implement aux-function support in the PL061, with an in stellaris_init()
1265 * - Wire the AFOUT for D0 up to either a line from the in stellaris_init()
1267 * or at least to an always-0 line here on the board in stellaris_init()
1268 * - Make the ssd0323 OLED controller chipselect active-low in stellaris_init()
1271 sddev = ssi_create_peripheral(bus, "ssi-sd"); in stellaris_init()
1278 qdev_get_child_bus(sddev, "sd-bus"), in stellaris_init()
1289 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); in stellaris_init()
1305 if (board->dc4 & (1 << 28)) { in stellaris_init()
1320 if (board->peripherals & BP_GAMEPAD) { in stellaris_init()
1348 if (board->dc4 & (1 << i)) { in stellaris_init()
1360 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); in stellaris_init()
1361 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); in stellaris_init()
1363 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); in stellaris_init()
1364 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); in stellaris_init()
1365 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); in stellaris_init()
1367 create_unimplemented_device("flash-control", 0x400fd000, 0x1000); in stellaris_init()
1369 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size); in stellaris_init()
1387 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; in lm3s811evb_class_init()
1388 mc->init = lm3s811evb_init; in lm3s811evb_class_init()
1389 mc->ignore_memory_transaction_failures = true; in lm3s811evb_class_init()
1390 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); in lm3s811evb_class_init()
1403 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; in lm3s6965evb_class_init()
1404 mc->init = lm3s6965evb_init; in lm3s6965evb_class_init()
1405 mc->ignore_memory_transaction_failures = true; in lm3s6965evb_class_init()
1406 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); in lm3s6965evb_class_init()
1428 rc->phases.enter = stellaris_i2c_reset_enter; in type_init()
1429 rc->phases.hold = stellaris_i2c_reset_hold; in type_init()
1430 rc->phases.exit = stellaris_i2c_reset_exit; in type_init()
1431 dc->vmsd = &vmstate_stellaris_i2c; in type_init()
1447 rc->phases.hold = stellaris_adc_reset_hold; in stellaris_adc_class_init()
1448 dc->vmsd = &vmstate_stellaris_adc; in stellaris_adc_class_init()
1464 dc->vmsd = &vmstate_stellaris_sys; in stellaris_sys_class_init()
1465 rc->phases.enter = stellaris_sys_reset_enter; in stellaris_sys_class_init()
1466 rc->phases.hold = stellaris_sys_reset_hold; in stellaris_sys_class_init()
1467 rc->phases.exit = stellaris_sys_reset_exit; in stellaris_sys_class_init()