Lines Matching +full:armv7m +full:- +full:systick
23 #include "hw/arm/armsse-version.h"
26 #include "hw/qdev-clock.h"
29 * The SSE-300 puts some devices in different places to the
30 * SSE-200 (and original IoTKit). We use an array of these structs
36 #define NO_IRQ -1
37 #define NO_PPC -1
54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
85 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
115 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
187 .name = "armsse-sysinfo",
195 .name = "armsse-sysctl",
271 .name = "armsse-sysinfo",
279 .name = "armsse-sysctl",
429 .name = "armsse-sysinfo",
437 .name = "armsse-sysctl",
485 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
488 /* 6, 7: per-CPU MHU interrupts */
490 /* 13: per-CPU icache interrupt */
496 /* 28, 29: per-CPU CTI interrupts */
502 /* 6, 7: per-CPU MHU interrupts */
506 /* 17-25: reserved */
508 /* 28, 29: per-CPU CTI interrupts */
516 .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
537 .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"),
558 .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"),
583 switch (info->sse_version) { in armsse_sys_config_value()
586 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
587 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); in armsse_sys_config_value()
591 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
592 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); in armsse_sys_config_value()
594 if (info->num_cpus > 1) { in armsse_sys_config_value()
596 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); in armsse_sys_config_value()
602 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
603 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); in armsse_sys_config_value()
604 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ in armsse_sys_config_value()
624 memory_region_add_subregion_overlap(container, base, mr, -1500); in make_alias()
638 s->nsccfg = level; in nsccfg_handler()
649 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; in armsse_forward_ppc()
651 DeviceState *dev_secctl = DEVICE(&s->secctl); in armsse_forward_ppc()
679 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); in armsse_forward_ppc()
680 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); in armsse_forward_ppc()
682 s->irq_status_in[ppcnum], name, 1); in armsse_forward_ppc()
692 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); in armsse_forward_sec_resp_cfg()
694 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); in armsse_forward_sec_resp_cfg()
695 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, in armsse_forward_sec_resp_cfg()
696 s->sec_resp_cfg, 1); in armsse_forward_sec_resp_cfg()
697 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); in armsse_forward_sec_resp_cfg()
704 const ARMSSEInfo *info = asc->info; in armsse_init()
708 assert(info->sram_banks <= MAX_SRAM_BANKS); in armsse_init()
709 assert(info->num_cpus <= SSE_MAX_CPUS); in armsse_init()
711 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0); in armsse_init()
712 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); in armsse_init()
714 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); in armsse_init()
716 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
724 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); in armsse_init()
725 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); in armsse_init()
728 name = g_strdup_printf("armv7m%d", i); in armsse_init()
729 object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], in armsse_init()
731 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type); in armsse_init()
733 name = g_strdup_printf("arm-sse-cpu-container%d", i); in armsse_init()
734 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); in armsse_init()
737 name = g_strdup_printf("arm-sse-container-alias%d", i); in armsse_init()
738 memory_region_init_alias(&s->container_alias[i - 1], obj, in armsse_init()
739 name, &s->container, 0, UINT64_MAX); in armsse_init()
744 for (devinfo = info->devinfo; devinfo->name; devinfo++) { in armsse_init()
745 assert(devinfo->ppc == NO_PPC || devinfo->ppc < ARRAY_SIZE(s->apb_ppc)); in armsse_init()
746 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { in armsse_init()
747 assert(devinfo->index < ARRAY_SIZE(s->timer)); in armsse_init()
748 object_initialize_child(obj, devinfo->name, in armsse_init()
749 &s->timer[devinfo->index], in armsse_init()
751 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { in armsse_init()
752 assert(devinfo->index == 0); in armsse_init()
753 object_initialize_child(obj, devinfo->name, &s->dualtimer, in armsse_init()
755 } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) { in armsse_init()
756 assert(devinfo->index < ARRAY_SIZE(s->sse_timer)); in armsse_init()
757 object_initialize_child(obj, devinfo->name, in armsse_init()
758 &s->sse_timer[devinfo->index], in armsse_init()
760 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { in armsse_init()
761 assert(devinfo->index < ARRAY_SIZE(s->cmsdk_watchdog)); in armsse_init()
762 object_initialize_child(obj, devinfo->name, in armsse_init()
763 &s->cmsdk_watchdog[devinfo->index], in armsse_init()
765 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { in armsse_init()
766 assert(devinfo->index == 0); in armsse_init()
767 object_initialize_child(obj, devinfo->name, &s->sysinfo, in armsse_init()
769 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { in armsse_init()
770 assert(devinfo->index == 0); in armsse_init()
771 object_initialize_child(obj, devinfo->name, &s->sysctl, in armsse_init()
773 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { in armsse_init()
774 assert(devinfo->index < ARRAY_SIZE(s->unimp)); in armsse_init()
775 object_initialize_child(obj, devinfo->name, in armsse_init()
776 &s->unimp[devinfo->index], in armsse_init()
783 object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); in armsse_init()
785 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) { in armsse_init()
786 g_autofree char *name = g_strdup_printf("apb-ppc%d", i); in armsse_init()
787 object_initialize_child(obj, name, &s->apb_ppc[i], TYPE_TZ_PPC); in armsse_init()
790 for (i = 0; i < info->sram_banks; i++) { in armsse_init()
792 object_initialize_child(obj, name, &s->mpc[i], TYPE_TZ_MPC); in armsse_init()
795 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, in armsse_init()
798 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { in armsse_init()
799 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); in armsse_init()
800 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; in armsse_init()
806 if (info->has_mhus) { in armsse_init()
807 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); in armsse_init()
808 object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); in armsse_init()
810 if (info->has_cachectrl) { in armsse_init()
811 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
814 object_initialize_child(obj, name, &s->cachectrl[i], in armsse_init()
819 if (info->has_cpusecctrl) { in armsse_init()
820 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
823 object_initialize_child(obj, name, &s->cpusecctrl[i], in armsse_init()
828 if (info->has_cpuid) { in armsse_init()
829 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
832 object_initialize_child(obj, name, &s->cpuid[i], in armsse_init()
837 if (info->has_cpu_pwrctrl) { in armsse_init()
838 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
841 object_initialize_child(obj, name, &s->cpu_pwrctrl[i], in armsse_init()
846 if (info->has_sse_counter) { in armsse_init()
847 object_initialize_child(obj, "sse-counter", &s->sse_counter, in armsse_init()
851 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); in armsse_init()
852 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, in armsse_init()
854 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, in armsse_init()
856 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { in armsse_init()
857 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); in armsse_init()
858 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; in armsse_init()
863 if (info->num_cpus > 1) { in armsse_init()
864 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { in armsse_init()
865 if (info->irq_is_common[i]) { in armsse_init()
866 char *name = g_strdup_printf("cpu-irq-splitter%d", i); in armsse_init()
867 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; in armsse_init()
886 qemu_set_irq(s->mpcexp_status_in[n], level); in armsse_mpcexp_status()
896 const ARMSSEInfo *info = asc->info; in armsse_get_common_irq_in()
898 assert(info->irq_is_common[irqno]); in armsse_get_common_irq_in()
900 if (info->num_cpus == 1) { in armsse_get_common_irq_in()
901 /* Only one CPU -- just connect directly to it */ in armsse_get_common_irq_in()
902 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); in armsse_get_common_irq_in()
905 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); in armsse_get_common_irq_in()
914 const ARMSSEInfo *info = asc->info; in armsse_realize()
926 if (!s->board_memory) { in armsse_realize()
931 if (!clock_has_source(s->mainclk)) { in armsse_realize()
934 if (!clock_has_source(s->s32kclk)) { in armsse_realize()
938 assert(info->num_cpus <= SSE_MAX_CPUS); in armsse_realize()
940 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ in armsse_realize()
941 assert(is_power_of_2(info->sram_banks)); in armsse_realize()
942 addr_width_max = 24 - ctz32(info->sram_banks); in armsse_realize()
943 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { in armsse_realize()
952 * devices exist in both address spaces but with hard-wired security in armsse_realize()
953 * permissions that will cause the CPU to fault for non-secure accesses. in armsse_realize()
956 * which specifies hard-wired security permissions for different in armsse_realize()
964 * into a non-secure region. They sit behind either a Memory in armsse_realize()
967 * configuration of whether non-secure accesses are permitted. in armsse_realize()
985 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); in armsse_realize()
987 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
988 DeviceState *cpudev = DEVICE(&s->armv7m[i]); in armsse_realize()
989 Object *cpuobj = OBJECT(&s->armv7m[i]); in armsse_realize()
993 qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk); in armsse_realize()
994 /* The SSE subsystems do not wire up a systick refclk */ in armsse_realize()
996 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS); in armsse_realize()
1001 * sysctl register, from this object's QOM init-svtor property. in armsse_realize()
1003 * code in iotkit-sysctl.c will update the CPU init-svtor property in armsse_realize()
1004 * (which will then take effect on the next CPU warm-reset). in armsse_realize()
1006 * Note that typically a board using the SSE-200 will have a system in armsse_realize()
1011 * (using the init-svtor property on the ARMSSE object) to match in armsse_realize()
1014 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); in armsse_realize()
1018 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and in armsse_realize()
1020 * start CPU0 and leave CPU1 powered off, we hard-code that in in armsse_realize()
1021 * info->cpuwait_rst for now. We can add QOM properties for this in armsse_realize()
1024 if (extract32(info->cpuwait_rst, i, 1)) { in armsse_realize()
1025 object_property_set_bool(cpuobj, "start-powered-off", true, in armsse_realize()
1028 if (!s->cpu_fpu[i]) { in armsse_realize()
1033 if (!s->cpu_dsp[i]) { in armsse_realize()
1038 if (!object_property_set_uint(cpuobj, "mpu-ns-regions", in armsse_realize()
1039 s->cpu_mpu_ns[i], errp)) { in armsse_realize()
1042 if (!object_property_set_uint(cpuobj, "mpu-s-regions", in armsse_realize()
1043 s->cpu_mpu_s[i], errp)) { in armsse_realize()
1048 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, in armsse_realize()
1049 &s->container_alias[i - 1], -1); in armsse_realize()
1051 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, in armsse_realize()
1052 &s->container, -1); in armsse_realize()
1055 OBJECT(&s->cpu_container[i]), &error_abort); in armsse_realize()
1061 * The cluster must be realized after the armv7m container, as in armsse_realize()
1066 if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) { in armsse_realize()
1071 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); in armsse_realize()
1072 for (j = 0; j < s->exp_numirq; j++) { in armsse_realize()
1073 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS); in armsse_realize()
1081 s->exp_irqs[i], in armsse_realize()
1082 gpioname, s->exp_numirq); in armsse_realize()
1087 if (info->num_cpus > 1) { in armsse_realize()
1088 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { in armsse_realize()
1089 if (info->irq_is_common[i]) { in armsse_realize()
1090 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); in armsse_realize()
1094 if (!object_property_set_int(splitter, "num-lines", in armsse_realize()
1095 info->num_cpus, errp)) { in armsse_realize()
1101 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { in armsse_realize()
1102 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); in armsse_realize()
1112 make_alias(s, &s->alias1, &s->container, "alias 1", in armsse_realize()
1114 make_alias(s, &s->alias2, &s->container, in armsse_realize()
1121 * are per-CPU, so we must put this alias in the per-cpu containers. in armsse_realize()
1123 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1124 make_alias(s, &s->alias3[i], &s->cpu_container[i], in armsse_realize()
1129 object_property_set_int(OBJECT(&s->secctl), "sse-version", in armsse_realize()
1130 info->sse_version, &error_abort); in armsse_realize()
1131 if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) { in armsse_realize()
1134 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); in armsse_realize()
1135 dev_secctl = DEVICE(&s->secctl); in armsse_realize()
1139 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); in armsse_realize()
1140 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); in armsse_realize()
1146 if (!object_property_set_int(OBJECT(&s->sec_resp_splitter), in armsse_realize()
1147 "num-lines", 3, errp)) { in armsse_realize()
1150 if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) { in armsse_realize()
1153 dev_splitter = DEVICE(&s->sec_resp_splitter); in armsse_realize()
1158 for (i = 0; i < info->sram_banks; i++) { in armsse_realize()
1161 uint32_t sram_bank_size = 1 << s->sram_addr_width; in armsse_realize()
1163 memory_region_init_ram(&s->sram[i], NULL, ramname, in armsse_realize()
1169 object_property_set_link(OBJECT(&s->mpc[i]), "downstream", in armsse_realize()
1170 OBJECT(&s->sram[i]), &error_abort); in armsse_realize()
1171 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) { in armsse_realize()
1175 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); in armsse_realize()
1176 memory_region_add_subregion(&s->container, in armsse_realize()
1177 info->sram_bank_base + i * sram_bank_size, in armsse_realize()
1180 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, in armsse_realize()
1185 if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", in armsse_realize()
1186 IOTS_NUM_EXP_MPC + info->sram_banks, in armsse_realize()
1190 if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) { in armsse_realize()
1193 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, in armsse_realize()
1197 if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, in armsse_realize()
1201 if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) { in armsse_realize()
1204 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, in armsse_realize()
1205 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); in armsse_realize()
1207 /* The SSE-300 has a System Counter / System Timestamp Generator */ in armsse_realize()
1208 if (info->has_sse_counter) { in armsse_realize()
1209 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sse_counter); in armsse_realize()
1211 qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk); in armsse_realize()
1220 memory_region_add_subregion(&s->container, 0x58100000, in armsse_realize()
1222 memory_region_add_subregion(&s->container, 0x48101000, in armsse_realize()
1226 if (info->has_tcms) { in armsse_realize()
1227 /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */ in armsse_realize()
1228 memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, errp); in armsse_realize()
1232 memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, errp); in armsse_realize()
1236 memory_region_add_subregion(&s->container, 0x00000000, &s->itcm); in armsse_realize()
1237 memory_region_add_subregion(&s->container, 0x20000000, &s->dtcm); in armsse_realize()
1244 * 0x40003000: MHU0 (SSE-200 only) in armsse_realize()
1245 * 0x40004000: MHU1 (SSE-200 only) in armsse_realize()
1250 for (devinfo = info->devinfo; devinfo->name; devinfo++) { in armsse_realize()
1254 if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { in armsse_realize()
1255 sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]); in armsse_realize()
1258 devinfo->slowclk ? s->s32kclk : s->mainclk); in armsse_realize()
1263 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) { in armsse_realize()
1264 sbd = SYS_BUS_DEVICE(&s->dualtimer); in armsse_realize()
1266 qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk); in armsse_realize()
1271 } else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) { in armsse_realize()
1272 sbd = SYS_BUS_DEVICE(&s->sse_timer[devinfo->index]); in armsse_realize()
1274 assert(info->has_sse_counter); in armsse_realize()
1276 OBJECT(&s->sse_counter), &error_abort); in armsse_realize()
1281 } else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) { in armsse_realize()
1282 sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]); in armsse_realize()
1285 devinfo->slowclk ? s->s32kclk : s->mainclk); in armsse_realize()
1290 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) { in armsse_realize()
1291 sbd = SYS_BUS_DEVICE(&s->sysinfo); in armsse_realize()
1293 object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", in armsse_realize()
1294 info->sys_version, &error_abort); in armsse_realize()
1295 object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", in armsse_realize()
1298 object_property_set_int(OBJECT(&s->sysinfo), "sse-version", in armsse_realize()
1299 info->sse_version, &error_abort); in armsse_realize()
1300 object_property_set_int(OBJECT(&s->sysinfo), "IIDR", in armsse_realize()
1301 info->iidr, &error_abort); in armsse_realize()
1306 } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { in armsse_realize()
1308 sbd = SYS_BUS_DEVICE(&s->sysctl); in armsse_realize()
1310 object_property_set_int(OBJECT(&s->sysctl), "sse-version", in armsse_realize()
1311 info->sse_version, &error_abort); in armsse_realize()
1312 object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", in armsse_realize()
1313 info->cpuwait_rst, &error_abort); in armsse_realize()
1314 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", in armsse_realize()
1315 s->init_svtor, &error_abort); in armsse_realize()
1316 object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", in armsse_realize()
1317 s->init_svtor, &error_abort); in armsse_realize()
1322 } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { in armsse_realize()
1323 sbd = SYS_BUS_DEVICE(&s->unimp[devinfo->index]); in armsse_realize()
1325 qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name); in armsse_realize()
1326 qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size); in armsse_realize()
1335 switch (devinfo->irq) { in armsse_realize()
1339 case 0 ... NUM_SSE_IRQS - 1: in armsse_realize()
1340 irq = armsse_get_common_irq_in(s, devinfo->irq); in armsse_realize()
1344 irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate), in armsse_realize()
1345 devinfo->irq - NMI_0); in armsse_realize()
1361 if (devinfo->ppc != NO_PPC) { in armsse_realize()
1362 TZPPC *ppc = &s->apb_ppc[devinfo->ppc]; in armsse_realize()
1364 devinfo->ppc_port); in armsse_realize()
1368 memory_region_add_subregion(&s->container, devinfo->addr, mr); in armsse_realize()
1372 if (info->has_mhus) { in armsse_realize()
1374 * An SSE-200 with only one CPU should have only one MHU created, in armsse_realize()
1376 * We don't implement that SSE-200 config; if we want to support in armsse_realize()
1380 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); in armsse_realize()
1382 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { in armsse_realize()
1385 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); in armsse_realize()
1387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) { in armsse_realize()
1392 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr), in armsse_realize()
1398 * MHU 0 irq line 0 -> CPU 0 IRQ 6 in armsse_realize()
1399 * MHU 0 irq line 1 -> CPU 1 IRQ 6 in armsse_realize()
1400 * MHU 1 irq line 0 -> CPU 0 IRQ 7 in armsse_realize()
1401 * MHU 1 irq line 1 -> CPU 1 IRQ 7 in armsse_realize()
1403 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { in armsse_realize()
1404 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); in armsse_realize()
1412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { in armsse_realize()
1416 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]); in armsse_realize()
1417 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]); in armsse_realize()
1419 if (info->has_mhus) { in armsse_realize()
1421 memory_region_add_subregion(&s->container, 0x40003000, mr); in armsse_realize()
1423 memory_region_add_subregion(&s->container, 0x40004000, mr); in armsse_realize()
1447 if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate), in armsse_realize()
1448 "num-lines", NUM_PPCS, errp)) { in armsse_realize()
1451 if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) { in armsse_realize()
1454 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, in armsse_realize()
1458 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): in armsse_realize()
1459 * private per-CPU region (all these devices are SSE-200 only): in armsse_realize()
1463 * The SSE-300 has an extra: in armsse_realize()
1466 if (info->has_cachectrl) { in armsse_realize()
1467 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1470 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); in armsse_realize()
1472 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); in armsse_realize()
1473 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) { in armsse_realize()
1477 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); in armsse_realize()
1478 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); in armsse_realize()
1481 if (info->has_cpusecctrl) { in armsse_realize()
1482 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1485 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); in armsse_realize()
1487 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); in armsse_realize()
1488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) { in armsse_realize()
1492 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); in armsse_realize()
1493 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); in armsse_realize()
1496 if (info->has_cpuid) { in armsse_realize()
1497 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1499 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); in armsse_realize()
1500 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) { in armsse_realize()
1504 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); in armsse_realize()
1505 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); in armsse_realize()
1508 if (info->has_cpu_pwrctrl) { in armsse_realize()
1509 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1511 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp)) { in armsse_realize()
1515 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0); in armsse_realize()
1516 memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr); in armsse_realize()
1520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { in armsse_realize()
1524 dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]); in armsse_realize()
1544 * The ports which are connected to non-devinfo devices have in armsse_realize()
1547 for (devinfo = info->devinfo; devinfo->name; devinfo++) { in armsse_realize()
1550 if (devinfo->ppc == NO_PPC) { in armsse_realize()
1553 ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]); in armsse_realize()
1554 mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port); in armsse_realize()
1555 memory_region_add_subregion(&s->container, devinfo->addr, mr); in armsse_realize()
1558 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { in armsse_realize()
1559 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); in armsse_realize()
1561 if (!object_property_set_int(splitter, "num-lines", 2, errp)) { in armsse_realize()
1585 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); in armsse_realize()
1587 i - NUM_EXTERNAL_PPCS); in armsse_realize()
1588 TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS]; in armsse_realize()
1593 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); in armsse_realize()
1600 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { in armsse_realize()
1601 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; in armsse_realize()
1604 if (!object_property_set_int(OBJECT(splitter), "num-lines", 2, in armsse_realize()
1614 s->mpcexp_status_in[i] = qdev_get_gpio_in(devs, 0); in armsse_realize()
1620 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), in armsse_realize()
1626 i - IOTS_NUM_EXP_MPC)); in armsse_realize()
1630 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); in armsse_realize()
1653 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); in armsse_realize()
1661 * of the address bits. The NSC attribute is guest-adjustable via the in armsse_idau_check()
1668 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); in armsse_idau_check()
1690 s->nsccfg = 0; in armsse_reset()
1700 dc->realize = armsse_realize; in armsse_class_init()
1701 dc->vmsd = &armsse_vmstate; in armsse_class_init()
1702 device_class_set_props(dc, info->props); in armsse_class_init()
1704 iic->check = armsse_idau_check; in armsse_class_init()
1705 asc->info = info; in armsse_class_init()