8  * the COPYING file in the top-level directory.
15 #include "hw/qdev-clock.h"
24  * are supported in the future, add a sub-class of NRF51SoC for
47     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",  in clock_write()
64     if (!s->board_memory) {  in nrf51_soc_realize()
73     if (clock_has_source(s->sysclk)) {  in nrf51_soc_realize()
77     /* This clock doesn't need migration because it is fixed-frequency */  in nrf51_soc_realize()
78     clock_set_hz(s->sysclk, HCLK_FRQ);  in nrf51_soc_realize()
79     qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);  in nrf51_soc_realize()
81      * This SoC has no systick device, so don't connect refclk.  in nrf51_soc_realize()
82      * TODO: model the lack of systick (currently the armv7m object  in nrf51_soc_realize()
86     object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),  in nrf51_soc_realize()
88     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {  in nrf51_soc_realize()
92     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);  in nrf51_soc_realize()
94     if (!memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,  in nrf51_soc_realize()
98     memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);  in nrf51_soc_realize()
101     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {  in nrf51_soc_realize()
104     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);  in nrf51_soc_realize()
105     memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);  in nrf51_soc_realize()
106     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,  in nrf51_soc_realize()
107                        qdev_get_gpio_in(DEVICE(&s->cpu),  in nrf51_soc_realize()
111     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) {  in nrf51_soc_realize()
115     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);  in nrf51_soc_realize()
116     memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);  in nrf51_soc_realize()
117     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,  in nrf51_soc_realize()
118                        qdev_get_gpio_in(DEVICE(&s->cpu),  in nrf51_soc_realize()
122     if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size",  in nrf51_soc_realize()
123                                   s->flash_size, errp)) {  in nrf51_soc_realize()
127     if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) {  in nrf51_soc_realize()
131     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);  in nrf51_soc_realize()
132     memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);  in nrf51_soc_realize()
133     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);  in nrf51_soc_realize()
134     memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);  in nrf51_soc_realize()
135     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);  in nrf51_soc_realize()
136     memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);  in nrf51_soc_realize()
137     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);  in nrf51_soc_realize()
138     memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);  in nrf51_soc_realize()
141     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {  in nrf51_soc_realize()
145     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);  in nrf51_soc_realize()
146     memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);  in nrf51_soc_realize()
149     qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);  in nrf51_soc_realize()
153         if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) {  in nrf51_soc_realize()
156         if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {  in nrf51_soc_realize()
162         sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);  in nrf51_soc_realize()
163         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,  in nrf51_soc_realize()
164                            qdev_get_gpio_in(DEVICE(&s->cpu),  in nrf51_soc_realize()
169     memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,  in nrf51_soc_realize()
171     memory_region_add_subregion_overlap(&s->container,  in nrf51_soc_realize()
172                                         NRF51_IOMEM_BASE, &s->clock, -1);  in nrf51_soc_realize()
186     memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);  in nrf51_soc_init()
188     object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);  in nrf51_soc_init()
189     qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",  in nrf51_soc_init()
190                          ARM_CPU_TYPE_NAME("cortex-m0"));  in nrf51_soc_init()
191     qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);  in nrf51_soc_init()
193     object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);  in nrf51_soc_init()
194     object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");  in nrf51_soc_init()
196     object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);  in nrf51_soc_init()
198     object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);  in nrf51_soc_init()
200     object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);  in nrf51_soc_init()
203         object_initialize_child(obj, "timer[*]", &s->timer[i],  in nrf51_soc_init()
208     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);  in nrf51_soc_init()
214     DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
215     DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
224     dc->realize = nrf51_soc_realize;  in nrf51_soc_class_init()