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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dallwinner,sun8i-a23-prcm.yaml31 - allwinner,sun8i-a23-apb0-clk
32 - allwinner,sun8i-a23-apb0-gates-clk
53 const: allwinner,sun8i-a23-apb0-clk
75 const: allwinner,sun8i-a23-apb0-gates-clk
142 apb0: apb0_clk {
143 compatible = "allwinner,sun8i-a23-apb0-clk";
146 clock-output-names = "apb0";
150 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
152 clocks = <&apb0>;
H A Dallwinner,sun6i-a31-prcm.yaml31 - allwinner,sun6i-a31-apb0-clk
32 - allwinner,sun6i-a31-apb0-gates-clk
76 const: allwinner,sun6i-a31-apb0-clk
98 const: allwinner,sun6i-a31-apb0-gates-clk
192 apb0: apb0_clk {
193 compatible = "allwinner,sun6i-a31-apb0-clk";
196 clock-output-names = "apb0";
200 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
202 clocks = <&apb0>;
/openbmc/linux/drivers/mfd/
H A Dsun6i-prcm.c54 .name = "sun6i-a31-apb0-clk",
55 .of_compatible = "allwinner,sun6i-a31-apb0-clk",
60 .name = "sun6i-a31-apb0-gates-clk",
61 .of_compatible = "allwinner,sun6i-a31-apb0-gates-clk",
72 .name = "sun6i-a31-apb0-clock-reset",
81 .name = "sun8i-a23-apb0-clk",
82 .of_compatible = "allwinner,sun8i-a23-apb0-clk",
87 .name = "sun6i-a31-apb0-gates-clk",
88 .of_compatible = "allwinner,sun8i-a23-apb0-gates-clk",
93 .name = "sun6i-a31-apb0-clock-reset",
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-apb0-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml#
7 title: Allwinner A10 APB0 Bus Clock
20 const: allwinner,sun4i-a10-apb0-clk
42 apb0@1c20054 {
44 compatible = "allwinner,sun4i-a10-apb0-clk";
47 clock-output-names = "apb0";
H A Dallwinner,sun4i-a10-gates-clk.yaml35 - const: allwinner,sun4i-a10-apb0-gates-clk
36 - const: allwinner,sun5i-a10s-apb0-gates-clk
37 - const: allwinner,sun5i-a13-apb0-gates-clk
38 - const: allwinner,sun7i-a20-apb0-gates-clk
39 - const: allwinner,sun9i-a80-apb0-gates-clk
40 - const: allwinner,sun8i-a83t-apb0-gates-clk
59 - const: allwinner,sun8i-h3-apb0-gates-clk
139 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
141 clocks = <&apb0>;
H A Dallwinner,sun9i-a80-apb0-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
7 title: Allwinner A80 APB0 Bus Clock
21 - allwinner,sun9i-a80-apb0-clk
48 compatible = "allwinner,sun9i-a80-apb0-clk";
51 clock-output-names = "apb0";
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun8i-apb0.c6 * Allwinner A23 APB0 clock driver
8 * Based on clk-sun6i-apb0.c
9 * Allwinner A31 APB0 clock driver
36 /* The A23 APB0 clock is a standard 2 bit wide divider clock */ in sun8i_a23_apb0_register()
68 pr_err("Could not get registers for a23-apb0-clk\n"); in sun8i_a23_apb0_setup()
84 CLK_OF_DECLARE_DRIVER(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
102 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
108 .name = "sun8i-a23-apb0-clk",
H A DMakefile26 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-apb0.o
29 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0.o
30 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0-gates.o
33 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun8i-apb0.o
34 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun6i-apb0-gates.o
H A Dclk-sun6i-apb0.c7 * Allwinner A31 APB0 clock driver
16 * The APB0 clk has a configurable divisor.
58 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
64 .name = "sun6i-a31-apb0-clk",
H A Dclk-simple-gates.c95 CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
101 CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
105 CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
115 CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
127 CLK_OF_DECLARE(sun8i_a83t_apb0, "allwinner,sun8i-a83t-apb0-gates-clk",
135 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
H A Dclk-sun6i-apb0-gates.c7 * Allwinner A31 APB0 clock gates driver
30 { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
31 { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
93 .name = "sun6i-a31-apb0-gates-clk",
H A Dclk-sun9i-core.c217 pr_err("Could not get registers for a80-apb0-clk: %pOFn\n", in sun9i_a80_apb0_setup()
225 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-r.c55 static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
63 static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio",
65 static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir",
67 static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer",
69 static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb",
71 static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart",
73 static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c",
75 static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd",
H A Dccu-sun4i-a10.c281 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
389 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
391 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
393 static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
395 static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
398 static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
400 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
402 static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
404 static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
407 static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
[all …]
H A Dccu-sun5i.c228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
297 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
299 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
301 static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0",
303 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
305 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
307 static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
H A Dccu-sun9i-a80.c308 .hw.init = CLK_HW_INIT_PARENTS("apb0",
778 /* APB0 bus gates */
779 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
781 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
783 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
785 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
787 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
789 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
791 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
793 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
[all …]
H A Dccu-sun5i.h42 /* APB0 gates are exported */
H A Dccu-sun4i-a10.h43 /* APB0 gates are exported (69..78) */
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c121 int axi, ahb, apb0; in clock_set_pll1() local
136 apb0 = 2; /* Max 150MHz */ in clock_set_pll1()
138 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
151 apb0 = apb0 - 1; in clock_set_pll1()
164 apb0 << APB0_DIV_SHIFT | in clock_set_pll1()
175 apb0 << APB0_DIV_SHIFT | in clock_set_pll1()
H A Dclock_sun9i.c36 /* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */ in clock_init_safe()
49 /* APB0: 120 MHz (PLL_PERIPH0 / 8) */ in clock_init_safe()
H A Dprcm.c23 /* APB0 clock gate and reset bit offsets are the same. */
/openbmc/qemu/hw/arm/
H A Dmsf2-som.c68 * CPU clock and peripheral clocks(APB0, APB1)are configurable in emcraft_sf2_s2s010_init()
69 * in Libero. CPU clock is divided by APB0 and APB1 divisors for in emcraft_sf2_s2s010_init()
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a23-a33.dtsi585 apb0: apb0_clk { label
586 compatible = "allwinner,sun8i-a23-apb0-clk";
589 clock-output-names = "apb0";
593 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
595 clocks = <&apb0>;
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a23-a33.dtsi754 apb0: apb0_clk { label
755 compatible = "allwinner,sun8i-a23-apb0-clk";
758 clock-output-names = "apb0";
762 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
764 clocks = <&apb0>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h33 u32 apb0_cfg; /* 0x70 apb0 clock configuration */
87 u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */

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