1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c84f5683SPriit Laes /* 3c84f5683SPriit Laes * Copyright 2017 Priit Laes 4c84f5683SPriit Laes * 5c84f5683SPriit Laes * Priit Laes <plaes@plaes.org> 6c84f5683SPriit Laes */ 7c84f5683SPriit Laes 8c84f5683SPriit Laes #ifndef _CCU_SUN4I_A10_H_ 9c84f5683SPriit Laes #define _CCU_SUN4I_A10_H_ 10c84f5683SPriit Laes 11c84f5683SPriit Laes #include <dt-bindings/clock/sun4i-a10-ccu.h> 12c84f5683SPriit Laes #include <dt-bindings/clock/sun7i-a20-ccu.h> 13c84f5683SPriit Laes #include <dt-bindings/reset/sun4i-a10-ccu.h> 14c84f5683SPriit Laes 15c84f5683SPriit Laes /* The HOSC is exported */ 16c84f5683SPriit Laes #define CLK_PLL_CORE 2 17c84f5683SPriit Laes #define CLK_PLL_AUDIO_BASE 3 18c84f5683SPriit Laes #define CLK_PLL_AUDIO 4 19c84f5683SPriit Laes #define CLK_PLL_AUDIO_2X 5 20c84f5683SPriit Laes #define CLK_PLL_AUDIO_4X 6 21c84f5683SPriit Laes #define CLK_PLL_AUDIO_8X 7 22c84f5683SPriit Laes #define CLK_PLL_VIDEO0 8 234328a218SJonathan Liu /* The PLL_VIDEO0_2X clock is exported */ 24c84f5683SPriit Laes #define CLK_PLL_VE 10 25c84f5683SPriit Laes #define CLK_PLL_DDR_BASE 11 26c84f5683SPriit Laes #define CLK_PLL_DDR 12 27c84f5683SPriit Laes #define CLK_PLL_DDR_OTHER 13 28c84f5683SPriit Laes #define CLK_PLL_PERIPH_BASE 14 29c84f5683SPriit Laes #define CLK_PLL_PERIPH 15 30c84f5683SPriit Laes #define CLK_PLL_PERIPH_SATA 16 31c84f5683SPriit Laes #define CLK_PLL_VIDEO1 17 324328a218SJonathan Liu /* The PLL_VIDEO1_2X clock is exported */ 33c84f5683SPriit Laes #define CLK_PLL_GPU 19 34c84f5683SPriit Laes 35c84f5683SPriit Laes /* The CPU clock is exported */ 36c84f5683SPriit Laes #define CLK_AXI 21 37c84f5683SPriit Laes #define CLK_AXI_DRAM 22 38c84f5683SPriit Laes #define CLK_AHB 23 39c84f5683SPriit Laes #define CLK_APB0 24 40c84f5683SPriit Laes #define CLK_APB1 25 41c84f5683SPriit Laes 42c84f5683SPriit Laes /* AHB gates are exported (23..68) */ 43c84f5683SPriit Laes /* APB0 gates are exported (69..78) */ 44c84f5683SPriit Laes /* APB1 gates are exported (79..95) */ 45c84f5683SPriit Laes /* IP module clocks are exported (96..128) */ 46c84f5683SPriit Laes /* DRAM gates are exported (129..142)*/ 47c84f5683SPriit Laes /* Media (display engine clocks & etc) are exported (143..169) */ 48c84f5683SPriit Laes 49c84f5683SPriit Laes #define CLK_NUMBER_SUN4I (CLK_MBUS + 1) 50c84f5683SPriit Laes #define CLK_NUMBER_SUN7I (CLK_OUT_B + 1) 51c84f5683SPriit Laes 52c84f5683SPriit Laes #endif /* _CCU_SUN4I_A10_H_ */ 53