1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
23b2bd70fSChen-Yu Tsai /*
33b2bd70fSChen-Yu Tsai * Copyright 2014 Chen-Yu Tsai
43b2bd70fSChen-Yu Tsai *
53b2bd70fSChen-Yu Tsai * Chen-Yu Tsai <wens@csie.org>
63b2bd70fSChen-Yu Tsai */
73b2bd70fSChen-Yu Tsai
89dfefe8cSStephen Boyd #include <linux/clk.h>
93b2bd70fSChen-Yu Tsai #include <linux/clk-provider.h>
103b2bd70fSChen-Yu Tsai #include <linux/of.h>
113b2bd70fSChen-Yu Tsai #include <linux/of_address.h>
123b2bd70fSChen-Yu Tsai #include <linux/log2.h>
133b2bd70fSChen-Yu Tsai
143b2bd70fSChen-Yu Tsai #include "clk-factors.h"
153b2bd70fSChen-Yu Tsai
163b2bd70fSChen-Yu Tsai
17*dcc35457SLee Jones /*
186424e0aeSHans de Goede * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
193b2bd70fSChen-Yu Tsai * PLL4 rate is calculated as follows
203b2bd70fSChen-Yu Tsai * rate = (parent_rate * n >> p) / (m + 1);
216424e0aeSHans de Goede * parent_rate is always 24MHz
223b2bd70fSChen-Yu Tsai *
233b2bd70fSChen-Yu Tsai * p and m are named div1 and div2 in Allwinner's SDK
243b2bd70fSChen-Yu Tsai */
253b2bd70fSChen-Yu Tsai
sun9i_a80_get_pll4_factors(struct factors_request * req)26cfa63688SChen-Yu Tsai static void sun9i_a80_get_pll4_factors(struct factors_request *req)
273b2bd70fSChen-Yu Tsai {
286424e0aeSHans de Goede int n;
296424e0aeSHans de Goede int m = 1;
306424e0aeSHans de Goede int p = 1;
313b2bd70fSChen-Yu Tsai
326424e0aeSHans de Goede /* Normalize value to a 6 MHz multiple (24 MHz / 4) */
33cfa63688SChen-Yu Tsai n = DIV_ROUND_UP(req->rate, 6000000);
343b2bd70fSChen-Yu Tsai
356424e0aeSHans de Goede /* If n is too large switch to steps of 12 MHz */
366424e0aeSHans de Goede if (n > 255) {
376424e0aeSHans de Goede m = 0;
386424e0aeSHans de Goede n = (n + 1) / 2;
396424e0aeSHans de Goede }
403b2bd70fSChen-Yu Tsai
416424e0aeSHans de Goede /* If n is still too large switch to steps of 24 MHz */
426424e0aeSHans de Goede if (n > 255) {
436424e0aeSHans de Goede p = 0;
446424e0aeSHans de Goede n = (n + 1) / 2;
456424e0aeSHans de Goede }
463b2bd70fSChen-Yu Tsai
476424e0aeSHans de Goede /* n must be between 12 and 255 */
486424e0aeSHans de Goede if (n > 255)
496424e0aeSHans de Goede n = 255;
506424e0aeSHans de Goede else if (n < 12)
516424e0aeSHans de Goede n = 12;
526424e0aeSHans de Goede
53cfa63688SChen-Yu Tsai req->rate = ((24000000 * n) >> p) / (m + 1);
54cfa63688SChen-Yu Tsai req->n = n;
55cfa63688SChen-Yu Tsai req->m = m;
56cfa63688SChen-Yu Tsai req->p = p;
573b2bd70fSChen-Yu Tsai }
583b2bd70fSChen-Yu Tsai
59b3e919e0SChen-Yu Tsai static const struct clk_factors_config sun9i_a80_pll4_config = {
603b2bd70fSChen-Yu Tsai .mshift = 18,
613b2bd70fSChen-Yu Tsai .mwidth = 1,
623b2bd70fSChen-Yu Tsai .nshift = 8,
633b2bd70fSChen-Yu Tsai .nwidth = 8,
643b2bd70fSChen-Yu Tsai .pshift = 16,
653b2bd70fSChen-Yu Tsai .pwidth = 1,
663b2bd70fSChen-Yu Tsai };
673b2bd70fSChen-Yu Tsai
683b2bd70fSChen-Yu Tsai static const struct factors_data sun9i_a80_pll4_data __initconst = {
693b2bd70fSChen-Yu Tsai .enable = 31,
703b2bd70fSChen-Yu Tsai .table = &sun9i_a80_pll4_config,
713b2bd70fSChen-Yu Tsai .getter = sun9i_a80_get_pll4_factors,
723b2bd70fSChen-Yu Tsai };
733b2bd70fSChen-Yu Tsai
743b2bd70fSChen-Yu Tsai static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
753b2bd70fSChen-Yu Tsai
sun9i_a80_pll4_setup(struct device_node * node)763b2bd70fSChen-Yu Tsai static void __init sun9i_a80_pll4_setup(struct device_node *node)
773b2bd70fSChen-Yu Tsai {
7866e79cf1SChen-Yu Tsai void __iomem *reg;
7966e79cf1SChen-Yu Tsai
8066e79cf1SChen-Yu Tsai reg = of_io_request_and_map(node, 0, of_node_full_name(node));
815ac382c3SMaxime Ripard if (IS_ERR(reg)) {
82e665f029SRob Herring pr_err("Could not get registers for a80-pll4-clk: %pOFn\n",
83e665f029SRob Herring node);
8466e79cf1SChen-Yu Tsai return;
8566e79cf1SChen-Yu Tsai }
8666e79cf1SChen-Yu Tsai
8766e79cf1SChen-Yu Tsai sunxi_factors_register(node, &sun9i_a80_pll4_data,
8866e79cf1SChen-Yu Tsai &sun9i_a80_pll4_lock, reg);
893b2bd70fSChen-Yu Tsai }
903b2bd70fSChen-Yu Tsai CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
913b2bd70fSChen-Yu Tsai
923b2bd70fSChen-Yu Tsai
93*dcc35457SLee Jones /*
943b2bd70fSChen-Yu Tsai * sun9i_a80_get_gt_factors() - calculates m factor for GT
953b2bd70fSChen-Yu Tsai * GT rate is calculated as follows
963b2bd70fSChen-Yu Tsai * rate = parent_rate / (m + 1);
973b2bd70fSChen-Yu Tsai */
983b2bd70fSChen-Yu Tsai
sun9i_a80_get_gt_factors(struct factors_request * req)99cfa63688SChen-Yu Tsai static void sun9i_a80_get_gt_factors(struct factors_request *req)
1003b2bd70fSChen-Yu Tsai {
1013b2bd70fSChen-Yu Tsai u32 div;
1023b2bd70fSChen-Yu Tsai
103cfa63688SChen-Yu Tsai if (req->parent_rate < req->rate)
104cfa63688SChen-Yu Tsai req->rate = req->parent_rate;
1053b2bd70fSChen-Yu Tsai
106cfa63688SChen-Yu Tsai div = DIV_ROUND_UP(req->parent_rate, req->rate);
1073b2bd70fSChen-Yu Tsai
1083b2bd70fSChen-Yu Tsai /* maximum divider is 4 */
1093b2bd70fSChen-Yu Tsai if (div > 4)
1103b2bd70fSChen-Yu Tsai div = 4;
1113b2bd70fSChen-Yu Tsai
112cfa63688SChen-Yu Tsai req->rate = req->parent_rate / div;
113cfa63688SChen-Yu Tsai req->m = div;
1143b2bd70fSChen-Yu Tsai }
1153b2bd70fSChen-Yu Tsai
116b3e919e0SChen-Yu Tsai static const struct clk_factors_config sun9i_a80_gt_config = {
1173b2bd70fSChen-Yu Tsai .mshift = 0,
1183b2bd70fSChen-Yu Tsai .mwidth = 2,
1193b2bd70fSChen-Yu Tsai };
1203b2bd70fSChen-Yu Tsai
1213b2bd70fSChen-Yu Tsai static const struct factors_data sun9i_a80_gt_data __initconst = {
1223b2bd70fSChen-Yu Tsai .mux = 24,
1233b2bd70fSChen-Yu Tsai .muxmask = BIT(1) | BIT(0),
1243b2bd70fSChen-Yu Tsai .table = &sun9i_a80_gt_config,
1253b2bd70fSChen-Yu Tsai .getter = sun9i_a80_get_gt_factors,
1263b2bd70fSChen-Yu Tsai };
1273b2bd70fSChen-Yu Tsai
1283b2bd70fSChen-Yu Tsai static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
1293b2bd70fSChen-Yu Tsai
sun9i_a80_gt_setup(struct device_node * node)1303b2bd70fSChen-Yu Tsai static void __init sun9i_a80_gt_setup(struct device_node *node)
1313b2bd70fSChen-Yu Tsai {
13266e79cf1SChen-Yu Tsai void __iomem *reg;
13366e79cf1SChen-Yu Tsai
13466e79cf1SChen-Yu Tsai reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1355ac382c3SMaxime Ripard if (IS_ERR(reg)) {
136e665f029SRob Herring pr_err("Could not get registers for a80-gt-clk: %pOFn\n",
137e665f029SRob Herring node);
13866e79cf1SChen-Yu Tsai return;
13966e79cf1SChen-Yu Tsai }
14066e79cf1SChen-Yu Tsai
1413b2bd70fSChen-Yu Tsai /* The GT bus clock needs to be always enabled */
1429919d44fSStephen Boyd sunxi_factors_register_critical(node, &sun9i_a80_gt_data,
1439919d44fSStephen Boyd &sun9i_a80_gt_lock, reg);
1443b2bd70fSChen-Yu Tsai }
1453b2bd70fSChen-Yu Tsai CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
1463b2bd70fSChen-Yu Tsai
1473b2bd70fSChen-Yu Tsai
148*dcc35457SLee Jones /*
1493b2bd70fSChen-Yu Tsai * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
1503b2bd70fSChen-Yu Tsai * AHB rate is calculated as follows
1513b2bd70fSChen-Yu Tsai * rate = parent_rate >> p;
1523b2bd70fSChen-Yu Tsai */
1533b2bd70fSChen-Yu Tsai
sun9i_a80_get_ahb_factors(struct factors_request * req)154cfa63688SChen-Yu Tsai static void sun9i_a80_get_ahb_factors(struct factors_request *req)
1553b2bd70fSChen-Yu Tsai {
1563b2bd70fSChen-Yu Tsai u32 _p;
1573b2bd70fSChen-Yu Tsai
158cfa63688SChen-Yu Tsai if (req->parent_rate < req->rate)
159cfa63688SChen-Yu Tsai req->rate = req->parent_rate;
1603b2bd70fSChen-Yu Tsai
161cfa63688SChen-Yu Tsai _p = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
1623b2bd70fSChen-Yu Tsai
1633b2bd70fSChen-Yu Tsai /* maximum p is 3 */
1643b2bd70fSChen-Yu Tsai if (_p > 3)
1653b2bd70fSChen-Yu Tsai _p = 3;
1663b2bd70fSChen-Yu Tsai
167cfa63688SChen-Yu Tsai req->rate = req->parent_rate >> _p;
168cfa63688SChen-Yu Tsai req->p = _p;
1693b2bd70fSChen-Yu Tsai }
1703b2bd70fSChen-Yu Tsai
171b3e919e0SChen-Yu Tsai static const struct clk_factors_config sun9i_a80_ahb_config = {
1723b2bd70fSChen-Yu Tsai .pshift = 0,
1733b2bd70fSChen-Yu Tsai .pwidth = 2,
1743b2bd70fSChen-Yu Tsai };
1753b2bd70fSChen-Yu Tsai
1763b2bd70fSChen-Yu Tsai static const struct factors_data sun9i_a80_ahb_data __initconst = {
1773b2bd70fSChen-Yu Tsai .mux = 24,
1783b2bd70fSChen-Yu Tsai .muxmask = BIT(1) | BIT(0),
1793b2bd70fSChen-Yu Tsai .table = &sun9i_a80_ahb_config,
1803b2bd70fSChen-Yu Tsai .getter = sun9i_a80_get_ahb_factors,
1813b2bd70fSChen-Yu Tsai };
1823b2bd70fSChen-Yu Tsai
1833b2bd70fSChen-Yu Tsai static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
1843b2bd70fSChen-Yu Tsai
sun9i_a80_ahb_setup(struct device_node * node)1853b2bd70fSChen-Yu Tsai static void __init sun9i_a80_ahb_setup(struct device_node *node)
1863b2bd70fSChen-Yu Tsai {
18766e79cf1SChen-Yu Tsai void __iomem *reg;
18866e79cf1SChen-Yu Tsai
18966e79cf1SChen-Yu Tsai reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1905ac382c3SMaxime Ripard if (IS_ERR(reg)) {
191e665f029SRob Herring pr_err("Could not get registers for a80-ahb-clk: %pOFn\n",
192e665f029SRob Herring node);
19366e79cf1SChen-Yu Tsai return;
19466e79cf1SChen-Yu Tsai }
19566e79cf1SChen-Yu Tsai
19666e79cf1SChen-Yu Tsai sunxi_factors_register(node, &sun9i_a80_ahb_data,
19766e79cf1SChen-Yu Tsai &sun9i_a80_ahb_lock, reg);
1983b2bd70fSChen-Yu Tsai }
1993b2bd70fSChen-Yu Tsai CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
2003b2bd70fSChen-Yu Tsai
2013b2bd70fSChen-Yu Tsai
2023b2bd70fSChen-Yu Tsai static const struct factors_data sun9i_a80_apb0_data __initconst = {
2033b2bd70fSChen-Yu Tsai .mux = 24,
2043b2bd70fSChen-Yu Tsai .muxmask = BIT(0),
2053b2bd70fSChen-Yu Tsai .table = &sun9i_a80_ahb_config,
2063b2bd70fSChen-Yu Tsai .getter = sun9i_a80_get_ahb_factors,
2073b2bd70fSChen-Yu Tsai };
2083b2bd70fSChen-Yu Tsai
2093b2bd70fSChen-Yu Tsai static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
2103b2bd70fSChen-Yu Tsai
sun9i_a80_apb0_setup(struct device_node * node)2113b2bd70fSChen-Yu Tsai static void __init sun9i_a80_apb0_setup(struct device_node *node)
2123b2bd70fSChen-Yu Tsai {
21366e79cf1SChen-Yu Tsai void __iomem *reg;
21466e79cf1SChen-Yu Tsai
21566e79cf1SChen-Yu Tsai reg = of_io_request_and_map(node, 0, of_node_full_name(node));
2165ac382c3SMaxime Ripard if (IS_ERR(reg)) {
217e665f029SRob Herring pr_err("Could not get registers for a80-apb0-clk: %pOFn\n",
218e665f029SRob Herring node);
21966e79cf1SChen-Yu Tsai return;
22066e79cf1SChen-Yu Tsai }
22166e79cf1SChen-Yu Tsai
22266e79cf1SChen-Yu Tsai sunxi_factors_register(node, &sun9i_a80_apb0_data,
22366e79cf1SChen-Yu Tsai &sun9i_a80_apb0_lock, reg);
2243b2bd70fSChen-Yu Tsai }
2253b2bd70fSChen-Yu Tsai CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
2263b2bd70fSChen-Yu Tsai
2273b2bd70fSChen-Yu Tsai
228*dcc35457SLee Jones /*
2293b2bd70fSChen-Yu Tsai * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
2303b2bd70fSChen-Yu Tsai * APB1 rate is calculated as follows
2313b2bd70fSChen-Yu Tsai * rate = (parent_rate >> p) / (m + 1);
2323b2bd70fSChen-Yu Tsai */
2333b2bd70fSChen-Yu Tsai
sun9i_a80_get_apb1_factors(struct factors_request * req)234cfa63688SChen-Yu Tsai static void sun9i_a80_get_apb1_factors(struct factors_request *req)
2353b2bd70fSChen-Yu Tsai {
2363b2bd70fSChen-Yu Tsai u32 div;
2373b2bd70fSChen-Yu Tsai
238cfa63688SChen-Yu Tsai if (req->parent_rate < req->rate)
239cfa63688SChen-Yu Tsai req->rate = req->parent_rate;
2403b2bd70fSChen-Yu Tsai
241cfa63688SChen-Yu Tsai div = DIV_ROUND_UP(req->parent_rate, req->rate);
2423b2bd70fSChen-Yu Tsai
2433b2bd70fSChen-Yu Tsai /* Highest possible divider is 256 (p = 3, m = 31) */
2443b2bd70fSChen-Yu Tsai if (div > 256)
2453b2bd70fSChen-Yu Tsai div = 256;
2463b2bd70fSChen-Yu Tsai
247cfa63688SChen-Yu Tsai req->p = order_base_2(div);
248cfa63688SChen-Yu Tsai req->m = (req->parent_rate >> req->p) - 1;
249cfa63688SChen-Yu Tsai req->rate = (req->parent_rate >> req->p) / (req->m + 1);
2503b2bd70fSChen-Yu Tsai }
2513b2bd70fSChen-Yu Tsai
252b3e919e0SChen-Yu Tsai static const struct clk_factors_config sun9i_a80_apb1_config = {
2533b2bd70fSChen-Yu Tsai .mshift = 0,
2543b2bd70fSChen-Yu Tsai .mwidth = 5,
2553b2bd70fSChen-Yu Tsai .pshift = 16,
2563b2bd70fSChen-Yu Tsai .pwidth = 2,
2573b2bd70fSChen-Yu Tsai };
2583b2bd70fSChen-Yu Tsai
2593b2bd70fSChen-Yu Tsai static const struct factors_data sun9i_a80_apb1_data __initconst = {
2603b2bd70fSChen-Yu Tsai .mux = 24,
2613b2bd70fSChen-Yu Tsai .muxmask = BIT(0),
2623b2bd70fSChen-Yu Tsai .table = &sun9i_a80_apb1_config,
2633b2bd70fSChen-Yu Tsai .getter = sun9i_a80_get_apb1_factors,
2643b2bd70fSChen-Yu Tsai };
2653b2bd70fSChen-Yu Tsai
2663b2bd70fSChen-Yu Tsai static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
2673b2bd70fSChen-Yu Tsai
sun9i_a80_apb1_setup(struct device_node * node)2683b2bd70fSChen-Yu Tsai static void __init sun9i_a80_apb1_setup(struct device_node *node)
2693b2bd70fSChen-Yu Tsai {
27066e79cf1SChen-Yu Tsai void __iomem *reg;
27166e79cf1SChen-Yu Tsai
27266e79cf1SChen-Yu Tsai reg = of_io_request_and_map(node, 0, of_node_full_name(node));
2735ac382c3SMaxime Ripard if (IS_ERR(reg)) {
274e665f029SRob Herring pr_err("Could not get registers for a80-apb1-clk: %pOFn\n",
275e665f029SRob Herring node);
27666e79cf1SChen-Yu Tsai return;
27766e79cf1SChen-Yu Tsai }
27866e79cf1SChen-Yu Tsai
27966e79cf1SChen-Yu Tsai sunxi_factors_register(node, &sun9i_a80_apb1_data,
28066e79cf1SChen-Yu Tsai &sun9i_a80_apb1_lock, reg);
2813b2bd70fSChen-Yu Tsai }
2823b2bd70fSChen-Yu Tsai CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
283