Home
last modified time | relevance | path

Searched +full:rclk +full:- +full:- +full:- +full:- +full:- (Results 1 – 25 of 86) sorted by relevance

1234

/openbmc/linux/drivers/clk/qcom/
H A Dclk-regmap.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * clk_is_enabled_regmap - standard is_enabled() for regmap users
24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap() local
28 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val); in clk_is_enabled_regmap()
32 if (rclk->enable_is_inverted) in clk_is_enabled_regmap()
33 return (val & rclk->enable_mask) == 0; in clk_is_enabled_regmap()
35 return (val & rclk->enable_mask) != 0; in clk_is_enabled_regmap()
40 * clk_enable_regmap - standard enable() for regmap users
[all …]
H A Dclk-regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
12 * struct clk_regmap - regmap supporting clock
13 * @hw: handle between common and hardware-specific interfaces
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
/openbmc/u-boot/board/qualcomm/dragonboard820c/
H A Ddragonboard820c.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
8 #include <asm/arch/sysmap-apq8096.h>
9 #include <linux/arm-smccc.h>
22 gd->ram_size = PHYS_SDRAM_SIZE; in dram_init()
29 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
30 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; in dram_init_banksize()
32 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; in dram_init_banksize()
33 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; in dram_init_banksize()
85 const struct tlmm_cfg rclk[] = { in sdhci_power_init() local
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sdx75-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Imran Shaik <quic_imrashai@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
17 See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
21 const: qcom,sdx75-gcc
25 - description: Board XO source
26 - description: Sleep clock source
[all …]
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
/openbmc/linux/sound/soc/samsung/
H A Darndale.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <sound/soc-dapm.h>
27 unsigned long rclk; in arndale_rt5631_hw_params() local
31 rclk = params_rate(params) * rfs; in arndale_rt5631_hw_params()
44 ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT); in arndale_rt5631_hw_params()
60 unsigned int rfs, rclk; in arndale_wm1811_hw_params() local
70 rclk = params_rate(params) * rfs; in arndale_wm1811_hw_params()
75 * samsung/clk-exynos5250.c for list of available EPLL rates). in arndale_wm1811_hw_params()
80 rclk + 1, SND_SOC_CLOCK_IN); in arndale_wm1811_hw_params()
89 DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5631-aif1")),
[all …]
H A Dsnow.c1 // SPDX-License-Identifier: GPL-2.0
34 struct snow_priv *priv = snd_soc_card_get_drvdata(rtd->card); in snow_card_hw_params()
36 unsigned long int rclk; in snow_card_hw_params() local
37 long int freq = -EINVAL; in snow_card_hw_params()
42 dev_err(rtd->card->dev, "Invalid bit-width: %d\n", bitwidth); in snow_card_hw_params()
47 dev_err(rtd->card->dev, "Unsupported bit-width: %d\n", bitwidth); in snow_card_hw_params()
48 return -EINVAL; in snow_card_hw_params()
73 return -EINVAL; in snow_card_hw_params()
76 rclk = params_rate(params) * rfs; in snow_card_hw_params()
80 if ((pll_rate[i] - rclk * psr) <= 2) { in snow_card_hw_params()
[all …]
/openbmc/linux/drivers/net/mdio/
H A Dmdio-mux-meson-gxl.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mdio-mux.h>
59 writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4); in gxl_enable_internal_mdio()
60 writel(val, priv->regs + ETH_REG3); in gxl_enable_internal_mdio()
66 * drivers/net/phy/meson-gxl.c to properly match the PHY. in gxl_enable_internal_mdio()
69 priv->regs + ETH_REG2); in gxl_enable_internal_mdio()
73 writel(val, priv->regs + ETH_REG3); in gxl_enable_internal_mdio()
74 writel(0, priv->regs + ETH_REG4); in gxl_enable_internal_mdio()
83 writel(0, priv->regs + ETH_REG3); in gxl_enable_external_mdio()
102 return -EINVAL; in gxl_mdio_switch_fn()
[all …]
/openbmc/linux/drivers/slimbus/
H A Dqcom-ctrl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
88 /* Resource group info for manager, and non-ported generic device-components */
116 struct clk *rclk; member
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count); in qcom_slim_queue_tx()
136 spin_lock_irqsave(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { in slim_alloc_rxbuf()
138 spin_unlock_irqrestore(&ctrl->rx.lock, flags); in slim_alloc_rxbuf()
139 dev_err(ctrl->dev, "RX QUEUE full!"); in slim_alloc_rxbuf()
142 idx = ctrl->rx.tail; in slim_alloc_rxbuf()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfaraday,ftgmac100.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Po-Yu Chuang <ratbert@faraday-tech.com>
18 - const: faraday,ftgmac100
19 - items:
20 - enum:
21 - aspeed,ast2400-mac
22 - aspeed,ast2500-mac
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-portwell-neptune.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "portwell,neptune-bmc", "aspeed,ast2500";
16 stdout-path = &uart5;
25 compatible = "gpio-leds";
29 default-state = "on";
34 linux,default-trigger = "heartbeat";
40 // postcode3-7 are GPIOH3-H7
[all …]
H A Daspeed-bmc-facebook-yamp.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,yamp-bmc", "aspeed,ast2500";
23 stdout-path = &uart5;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_txd2_default
37 use-ncsi;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_rmii1_default>;
[all …]
H A Daspeed-bmc-supermicro-x11spi.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
10 compatible = "supermicro,x11spi-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
32 iio-hwmon {
[all …]
H A Daspeed-bmc-intel-s2600wf.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
9 compatible = "intel,s2600wf-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
26 no-map;
31 iio-hwmon {
[all …]
H A Daspeed-bmc-inspur-on5263m5.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "aspeed-g5.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "inspur,on5263m5-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
[all …]
H A Daspeed-bmc-arm-stardragon4800-rep2.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500";
12 stdout-path = &uart5;
20 iio-hwmon {
21 compatible = "iio-hwmon";
22 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
26 iio-hwmon-battery {
[all …]
/openbmc/linux/include/dt-bindings/sound/
H A Dsamsung-i2s.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-ast2600.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
20 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
94 * handled by using -1 as the index for the reset, and the consumer must
104 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
105 [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
106 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
107 /* vclk parent - dclk/d1clk/hclk/mclk */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dqcs404-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 stdout-path = "serial0";
22 vph_pwr: vph-pwr-regulator {
23 compatible = "regulator-fixed";
24 regulator-name = "vph_pwr";
25 regulator-always-on;
26 regulator-boot-on;
[all …]
H A Dipq9574-rdp418.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
15 compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&spi_0_pins>;
28 pinctrl-names = "default";
32 compatible = "micron,n25q128a11", "jedec,spi-nor";
[all …]
H A Dipq9574-rdp433.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
15 compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
39 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
/openbmc/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
12 #include <linux/dma-mapping.h>
93 struct clk *rclk; member
116 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
122 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
134 return -EIO; in ftgmac100_reset_mac()
[all …]

1234