1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
20d40c612SSylwester Nawrocki #ifndef _DT_BINDINGS_SAMSUNG_I2S_H
30d40c612SSylwester Nawrocki #define _DT_BINDINGS_SAMSUNG_I2S_H
40d40c612SSylwester Nawrocki 
56cc23ed2SMaciej Falkowski #define CLK_I2S_CDCLK		0 /* the CDCLK (CODECLKO) gate clock */
66cc23ed2SMaciej Falkowski 
76cc23ed2SMaciej Falkowski #define CLK_I2S_RCLK_SRC	1 /* the RCLKSRC mux clock (corresponding to
86cc23ed2SMaciej Falkowski 				   * RCLKSRC bit in IISMOD register)
96cc23ed2SMaciej Falkowski 				   */
106cc23ed2SMaciej Falkowski 
116cc23ed2SMaciej Falkowski #define CLK_I2S_RCLK_PSR	2 /* the RCLK prescaler divider clock
126cc23ed2SMaciej Falkowski 				   * (corresponding to the IISPSR register)
136cc23ed2SMaciej Falkowski 				   */
140d40c612SSylwester Nawrocki 
150d40c612SSylwester Nawrocki #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */
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