1*9a24e1ffSJerome Brunet // SPDX-License-Identifier: GPL-2.0
2*9a24e1ffSJerome Brunet /* Copyright (c) 2022 Baylibre, SAS.
3*9a24e1ffSJerome Brunet  * Author: Jerome Brunet <jbrunet@baylibre.com>
4*9a24e1ffSJerome Brunet  */
5*9a24e1ffSJerome Brunet 
6*9a24e1ffSJerome Brunet #include <linux/bitfield.h>
7*9a24e1ffSJerome Brunet #include <linux/delay.h>
8*9a24e1ffSJerome Brunet #include <linux/clk.h>
9*9a24e1ffSJerome Brunet #include <linux/io.h>
10*9a24e1ffSJerome Brunet #include <linux/mdio-mux.h>
11*9a24e1ffSJerome Brunet #include <linux/module.h>
12*9a24e1ffSJerome Brunet #include <linux/platform_device.h>
13*9a24e1ffSJerome Brunet 
14*9a24e1ffSJerome Brunet #define ETH_REG2		0x0
15*9a24e1ffSJerome Brunet #define  REG2_PHYID		GENMASK(21, 0)
16*9a24e1ffSJerome Brunet #define   EPHY_GXL_ID		0x110181
17*9a24e1ffSJerome Brunet #define  REG2_LEDACT		GENMASK(23, 22)
18*9a24e1ffSJerome Brunet #define  REG2_LEDLINK		GENMASK(25, 24)
19*9a24e1ffSJerome Brunet #define  REG2_DIV4SEL		BIT(27)
20*9a24e1ffSJerome Brunet #define  REG2_ADCBYPASS		BIT(30)
21*9a24e1ffSJerome Brunet #define  REG2_CLKINSEL		BIT(31)
22*9a24e1ffSJerome Brunet #define ETH_REG3		0x4
23*9a24e1ffSJerome Brunet #define  REG3_ENH		BIT(3)
24*9a24e1ffSJerome Brunet #define  REG3_CFGMODE		GENMASK(6, 4)
25*9a24e1ffSJerome Brunet #define  REG3_AUTOMDIX		BIT(7)
26*9a24e1ffSJerome Brunet #define  REG3_PHYADDR		GENMASK(12, 8)
27*9a24e1ffSJerome Brunet #define  REG3_PWRUPRST		BIT(21)
28*9a24e1ffSJerome Brunet #define  REG3_PWRDOWN		BIT(22)
29*9a24e1ffSJerome Brunet #define  REG3_LEDPOL		BIT(23)
30*9a24e1ffSJerome Brunet #define  REG3_PHYMDI		BIT(26)
31*9a24e1ffSJerome Brunet #define  REG3_CLKINEN		BIT(29)
32*9a24e1ffSJerome Brunet #define  REG3_PHYIP		BIT(30)
33*9a24e1ffSJerome Brunet #define  REG3_PHYEN		BIT(31)
34*9a24e1ffSJerome Brunet #define ETH_REG4		0x8
35*9a24e1ffSJerome Brunet #define  REG4_PWRUPRSTSIG	BIT(0)
36*9a24e1ffSJerome Brunet 
37*9a24e1ffSJerome Brunet #define MESON_GXL_MDIO_EXTERNAL_ID 0
38*9a24e1ffSJerome Brunet #define MESON_GXL_MDIO_INTERNAL_ID 1
39*9a24e1ffSJerome Brunet 
40*9a24e1ffSJerome Brunet struct gxl_mdio_mux {
41*9a24e1ffSJerome Brunet 	void __iomem *regs;
42*9a24e1ffSJerome Brunet 	void *mux_handle;
43*9a24e1ffSJerome Brunet };
44*9a24e1ffSJerome Brunet 
gxl_enable_internal_mdio(struct gxl_mdio_mux * priv)45*9a24e1ffSJerome Brunet static void gxl_enable_internal_mdio(struct gxl_mdio_mux *priv)
46*9a24e1ffSJerome Brunet {
47*9a24e1ffSJerome Brunet 	u32 val;
48*9a24e1ffSJerome Brunet 
49*9a24e1ffSJerome Brunet 	/* Setup the internal phy */
50*9a24e1ffSJerome Brunet 	val = (REG3_ENH |
51*9a24e1ffSJerome Brunet 	       FIELD_PREP(REG3_CFGMODE, 0x7) |
52*9a24e1ffSJerome Brunet 	       REG3_AUTOMDIX |
53*9a24e1ffSJerome Brunet 	       FIELD_PREP(REG3_PHYADDR, 8) |
54*9a24e1ffSJerome Brunet 	       REG3_LEDPOL |
55*9a24e1ffSJerome Brunet 	       REG3_PHYMDI |
56*9a24e1ffSJerome Brunet 	       REG3_CLKINEN |
57*9a24e1ffSJerome Brunet 	       REG3_PHYIP);
58*9a24e1ffSJerome Brunet 
59*9a24e1ffSJerome Brunet 	writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
60*9a24e1ffSJerome Brunet 	writel(val, priv->regs + ETH_REG3);
61*9a24e1ffSJerome Brunet 	mdelay(10);
62*9a24e1ffSJerome Brunet 
63*9a24e1ffSJerome Brunet 	/* NOTE: The HW kept the phy id configurable at runtime.
64*9a24e1ffSJerome Brunet 	 * The id below is arbitrary. It is the one used in the vendor code.
65*9a24e1ffSJerome Brunet 	 * The only constraint is that it must match the one in
66*9a24e1ffSJerome Brunet 	 * drivers/net/phy/meson-gxl.c to properly match the PHY.
67*9a24e1ffSJerome Brunet 	 */
68*9a24e1ffSJerome Brunet 	writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
69*9a24e1ffSJerome Brunet 	       priv->regs + ETH_REG2);
70*9a24e1ffSJerome Brunet 
71*9a24e1ffSJerome Brunet 	/* Enable the internal phy */
72*9a24e1ffSJerome Brunet 	val |= REG3_PHYEN;
73*9a24e1ffSJerome Brunet 	writel(val, priv->regs + ETH_REG3);
74*9a24e1ffSJerome Brunet 	writel(0, priv->regs + ETH_REG4);
75*9a24e1ffSJerome Brunet 
76*9a24e1ffSJerome Brunet 	/* The phy needs a bit of time to power up */
77*9a24e1ffSJerome Brunet 	mdelay(10);
78*9a24e1ffSJerome Brunet }
79*9a24e1ffSJerome Brunet 
gxl_enable_external_mdio(struct gxl_mdio_mux * priv)80*9a24e1ffSJerome Brunet static void gxl_enable_external_mdio(struct gxl_mdio_mux *priv)
81*9a24e1ffSJerome Brunet {
82*9a24e1ffSJerome Brunet 	/* Reset the mdio bus mux to the external phy */
83*9a24e1ffSJerome Brunet 	writel(0, priv->regs + ETH_REG3);
84*9a24e1ffSJerome Brunet }
85*9a24e1ffSJerome Brunet 
gxl_mdio_switch_fn(int current_child,int desired_child,void * data)86*9a24e1ffSJerome Brunet static int gxl_mdio_switch_fn(int current_child, int desired_child,
87*9a24e1ffSJerome Brunet 			      void *data)
88*9a24e1ffSJerome Brunet {
89*9a24e1ffSJerome Brunet 	struct gxl_mdio_mux *priv = dev_get_drvdata(data);
90*9a24e1ffSJerome Brunet 
91*9a24e1ffSJerome Brunet 	if (current_child == desired_child)
92*9a24e1ffSJerome Brunet 		return 0;
93*9a24e1ffSJerome Brunet 
94*9a24e1ffSJerome Brunet 	switch (desired_child) {
95*9a24e1ffSJerome Brunet 	case MESON_GXL_MDIO_EXTERNAL_ID:
96*9a24e1ffSJerome Brunet 		gxl_enable_external_mdio(priv);
97*9a24e1ffSJerome Brunet 		break;
98*9a24e1ffSJerome Brunet 	case MESON_GXL_MDIO_INTERNAL_ID:
99*9a24e1ffSJerome Brunet 		gxl_enable_internal_mdio(priv);
100*9a24e1ffSJerome Brunet 		break;
101*9a24e1ffSJerome Brunet 	default:
102*9a24e1ffSJerome Brunet 		return -EINVAL;
103*9a24e1ffSJerome Brunet 	}
104*9a24e1ffSJerome Brunet 
105*9a24e1ffSJerome Brunet 	return 0;
106*9a24e1ffSJerome Brunet }
107*9a24e1ffSJerome Brunet 
108*9a24e1ffSJerome Brunet static const struct of_device_id gxl_mdio_mux_match[] = {
109*9a24e1ffSJerome Brunet 	{ .compatible = "amlogic,gxl-mdio-mux", },
110*9a24e1ffSJerome Brunet 	{},
111*9a24e1ffSJerome Brunet };
112*9a24e1ffSJerome Brunet MODULE_DEVICE_TABLE(of, gxl_mdio_mux_match);
113*9a24e1ffSJerome Brunet 
gxl_mdio_mux_probe(struct platform_device * pdev)114*9a24e1ffSJerome Brunet static int gxl_mdio_mux_probe(struct platform_device *pdev)
115*9a24e1ffSJerome Brunet {
116*9a24e1ffSJerome Brunet 	struct device *dev = &pdev->dev;
117*9a24e1ffSJerome Brunet 	struct gxl_mdio_mux *priv;
118*9a24e1ffSJerome Brunet 	struct clk *rclk;
119*9a24e1ffSJerome Brunet 	int ret;
120*9a24e1ffSJerome Brunet 
121*9a24e1ffSJerome Brunet 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
122*9a24e1ffSJerome Brunet 	if (!priv)
123*9a24e1ffSJerome Brunet 		return -ENOMEM;
124*9a24e1ffSJerome Brunet 	platform_set_drvdata(pdev, priv);
125*9a24e1ffSJerome Brunet 
126*9a24e1ffSJerome Brunet 	priv->regs = devm_platform_ioremap_resource(pdev, 0);
127*9a24e1ffSJerome Brunet 	if (IS_ERR(priv->regs))
128*9a24e1ffSJerome Brunet 		return PTR_ERR(priv->regs);
129*9a24e1ffSJerome Brunet 
130*9a24e1ffSJerome Brunet 	rclk = devm_clk_get_enabled(dev, "ref");
131*9a24e1ffSJerome Brunet 	if (IS_ERR(rclk))
132*9a24e1ffSJerome Brunet 		return dev_err_probe(dev, PTR_ERR(rclk),
133*9a24e1ffSJerome Brunet 				     "failed to get reference clock\n");
134*9a24e1ffSJerome Brunet 
135*9a24e1ffSJerome Brunet 	ret = mdio_mux_init(dev, dev->of_node, gxl_mdio_switch_fn,
136*9a24e1ffSJerome Brunet 			    &priv->mux_handle, dev, NULL);
137*9a24e1ffSJerome Brunet 	if (ret)
138*9a24e1ffSJerome Brunet 		dev_err_probe(dev, ret, "mdio multiplexer init failed\n");
139*9a24e1ffSJerome Brunet 
140*9a24e1ffSJerome Brunet 	return ret;
141*9a24e1ffSJerome Brunet }
142*9a24e1ffSJerome Brunet 
gxl_mdio_mux_remove(struct platform_device * pdev)143*9a24e1ffSJerome Brunet static int gxl_mdio_mux_remove(struct platform_device *pdev)
144*9a24e1ffSJerome Brunet {
145*9a24e1ffSJerome Brunet 	struct gxl_mdio_mux *priv = platform_get_drvdata(pdev);
146*9a24e1ffSJerome Brunet 
147*9a24e1ffSJerome Brunet 	mdio_mux_uninit(priv->mux_handle);
148*9a24e1ffSJerome Brunet 
149*9a24e1ffSJerome Brunet 	return 0;
150*9a24e1ffSJerome Brunet }
151*9a24e1ffSJerome Brunet 
152*9a24e1ffSJerome Brunet static struct platform_driver gxl_mdio_mux_driver = {
153*9a24e1ffSJerome Brunet 	.probe		= gxl_mdio_mux_probe,
154*9a24e1ffSJerome Brunet 	.remove		= gxl_mdio_mux_remove,
155*9a24e1ffSJerome Brunet 	.driver		= {
156*9a24e1ffSJerome Brunet 		.name	= "gxl-mdio-mux",
157*9a24e1ffSJerome Brunet 		.of_match_table = gxl_mdio_mux_match,
158*9a24e1ffSJerome Brunet 	},
159*9a24e1ffSJerome Brunet };
160*9a24e1ffSJerome Brunet module_platform_driver(gxl_mdio_mux_driver);
161*9a24e1ffSJerome Brunet 
162*9a24e1ffSJerome Brunet MODULE_DESCRIPTION("Amlogic GXL MDIO multiplexer driver");
163*9a24e1ffSJerome Brunet MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
164*9a24e1ffSJerome Brunet MODULE_LICENSE("GPL");
165