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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-clkcfg.yaml7 title: Microchip PolarFire Clock Control Module
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
45 PolarFire clock IDs.
52 The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
56 PolarFire clock IDs.
H A Dmicrochip,mpfs-ccc.yaml7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
58 PolarFire clock IDs.
/openbmc/qemu/docs/system/riscv/
H A Dmicrochip-icicle-kit.rst1 Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
4 Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
7 For more details about Microchip PolarFire SoC, please see:
8 https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
149 .. _HSS: https://github.com/polarfire-soc/hart-software-services
/openbmc/qemu/include/hw/char/
H A Dmchp_pfsoc_mmuart.h2 * Microchip PolarFire SoC MMUART emulation
53 * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
56 * compatible with Microchip PolarFire SoC.
/openbmc/linux/drivers/clk/microchip/
H A DKconfig7 bool "Clk driver for PolarFire SoC"
12 Supports Clock Configuration for PolarFire SoC
/openbmc/linux/drivers/soc/microchip/
H A DKconfig2 tristate "Microchip PolarFire SoC (MPFS) system controller support"
5 This driver adds support for the PolarFire SoC (MPFS) system controller.
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dmicrochip.yaml7 title: Microchip PolarFire SoC-based boards
14 Microchip PolarFire SoC-based boards
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dmicrochip,mpf-spi-fpga-mgr.yaml7 title: Microchip Polarfire FPGA manager.
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
/openbmc/qemu/hw/misc/
H A Dmchp_pfsoc_ioscb.c2 * Microchip PolarFire SoC IOSCB module emulation
44 * See Microchip PolarFire SoC documentation (Register_Map.zip),
167 * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services" in mchp_pfsoc_ctrl_read()
299 dc->desc = "Microchip PolarFire SoC IOSCB modules"; in mchp_pfsoc_ioscb_class_init()
H A Dmchp_pfsoc_dmc.c2 * Microchip PolarFire SoC DDR Memory Controller module emulation
117 dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module"; in mchp_pfsoc_ddr_sgmii_phy_class_init()
199 dc->desc = "Microchip PolarFire SoC DDR CFG module"; in mchp_pfsoc_ddr_cfg_class_init()
H A Dmchp_pfsoc_sysreg.c2 * Microchip PolarFire SoC SYSREG module emulation
92 dc->desc = "Microchip PolarFire SoC SYSREG module"; in mchp_pfsoc_sysreg_class_init()
/openbmc/linux/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,mpfs-sys-controller.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
13 PolarFire SoC devices include a microcontroller acting as the system controller,
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dmicrochip,mfps-rtc.yaml8 title: Microchip PolarFire Soc (MPFS) RTC
40 on the PolarFire SoC shares it's reference with MTIMER so this will
/openbmc/qemu/hw/riscv/
H A Dmicrochip_pfsoc.c2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
59 * See https://github.com/polarfire-soc/hart-software-services
71 * The complete description of the whole PolarFire SoC memory map is scattered
74 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
78 * describes the whole picture of the PolarFire SoC memory map.
80 * 2 A zip file for PolarFire soC memory map, which can be downloaded from
82 * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
643 mc->desc = "Microchip PolarFire SoC Icicle Kit"; in microchip_icicle_kit_machine_class_init()
/openbmc/linux/arch/riscv/
H A DKconfig.socs7 bool "Microchip PolarFire SoCs"
9 This enables support for Microchip PolarFire SoC platforms.
/openbmc/linux/drivers/char/hw_random/
H A Dmpfs-rng.c3 * Microchip PolarFire SoC (MPFS) hardware random driver
103 MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmicrochip,pcie-host.yaml18 const: microchip,pcie-host-1.0 # PolarFire
31 fabric and the core complex on PolarFire SoC. The FICs require two clocks,
/openbmc/linux/drivers/usb/musb/
H A DKconfig115 tristate "Microchip PolarFire SoC platforms"
120 Say Y here to enable support for USB on Microchip's PolarFire SoC.
/openbmc/linux/drivers/reset/
H A Dreset-mpfs.c3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
155 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
/openbmc/linux/drivers/fpga/
H A Dmicrochip-spi.c3 * Microchip Polarfire FPGA programming over slave SPI interface.
379 mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager", in mpf_probe()
410 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
H A DKconfig261 tristate "Microchip Polarfire SPI FPGA manager"
264 FPGA manager driver support for Microchip Polarfire FPGAs
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dmicrochip,mpfs-can.yaml8 Microchip PolarFire SoC (MPFS) can controller
/openbmc/linux/include/soc/microchip/
H A Dmpfs.h4 * Microchip PolarFire SoC (MPFS)
/openbmc/qemu/include/hw/misc/
H A Dmchp_pfsoc_sysreg.h2 * Microchip PolarFire SoC SYSREG module emulation
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/

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