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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19 |
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ea913d88 |
| 11-Jan-2023 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: riscv: microchip: document the Aldec TySoM
The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
a Microchip PolarFire SoC MPFS250T-FCG1152.
Document rev2 of this board.
Lin
dt-bindings: riscv: microchip: document the Aldec TySoM
The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
a Microchip PolarFire SoC MPFS250T-FCG1152.
Document rev2 of this board.
Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
show more ...
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Revision tags: v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1 |
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| #
abbb388d |
| 10-Oct-2022 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: riscv: update microchip.yaml's maintainership
Daire and I are the platform maintainers for Microchip's RISC-V
FPGAs. Update the maintainers in microchip.yaml to reflect this and
explici
dt-bindings: riscv: update microchip.yaml's maintainership
Daire and I are the platform maintainers for Microchip's RISC-V
FPGAs. Update the maintainers in microchip.yaml to reflect this and
explicitly add the binding to the SoC's MAINTAINERS entry.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221010221704.2161221-3-conor@kernel.org/
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
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Revision tags: v5.15.72, v6.0, v5.15.71 |
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| #
db3d4816 |
| 27-Sep-2022 |
Shravan Chippa <shravan.chippa@microchip.com> |
dt-bindings: riscv: microchip: document the sev kit
Update devicetree bindings document with PolarFire SoC Video Kit, known
by its "sev-kit" product code.
Link: https://onlinedocs.microchip.com/pr/
dt-bindings: riscv: microchip: document the sev kit
Update devicetree bindings document with PolarFire SoC Video Kit, known
by its "sev-kit" product code.
Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
show more ...
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| #
0ebdc517 |
| 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: riscv: microchip: document the aries m100pfsevp
Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi
dt-bindings: riscv: microchip: document the aries m100pfsevp
Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
show more ...
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| #
a0d49a8f |
| 27-Sep-2022 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: riscv: microchip: document icicle reference design
The icicle kit reference design's v2022.09 release made some changes
to the memory map - including adding the ability to read the fabr
dt-bindings: riscv: microchip: document icicle reference design
The icicle kit reference design's v2022.09 release made some changes
to the memory map - including adding the ability to read the fabric
clock controllers via the system controller bus & making the PCI
controller work with upstream Linux.
While the PCI was not working in the v2022.03 design, so nothing is
broken there in terms of backwards compatibility, the fabric clocks
used in the v2022.03 design were chosen by the individual run of the
synthesis tool. In the v2022.09 reference design, the clocks are fixed
to use the "north west" fabric Clock Conditioning Circuitry.
In the v2022.10 release, the memory map on the DDR side is also
changing, so to avoid making a breaking change here twice, jump over the
v2022.09 release and straight to the v2022.10 one.
Make use of a new compatible to denote that v2022.{09,10} reference
design releases are not backwards compatible.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
show more ...
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Revision tags: v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63 |
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| #
dd3cb467 |
| 24-Aug-2022 |
Andrew Lunn <andrew@lunn.ch> |
dt-bindings: Remove 'Device Tree Bindings' from end of title:
As indicated in
link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/
DT schema files should not have 'Device Tree
dt-bindings: Remove 'Device Tree Bindings' from end of title:
As indicated in
link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/
DT schema files should not have 'Device Tree Binding' as part of there
title: line. Remove this in most .yaml files, so hopefully preventing
developers copying it into new .yaml files, and being asked to remove
it.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch
Signed-off-by: Rob Herring <robh@kernel.org>
show more ...
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Revision tags: v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39 |
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| #
b847d32a |
| 09-May-2022 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: riscv: microchip: add polarberry compatible string
Add a binding for the Sundance Polarberry board.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor
dt-bindings: riscv: microchip: add polarberry compatible string
Add a binding for the Sundance Polarberry board.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-8-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
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| #
e8c81d64 |
| 09-May-2022 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: riscv: microchip: document icicle reference design
Add a compatible for the icicle kit's reference design. This represents
the FPGA fabric's contents & is versioned to denote which rele
dt-bindings: riscv: microchip: document icicle reference design
Add a compatible for the icicle kit's reference design. This represents
the FPGA fabric's contents & is versioned to denote which release of the
reference design it applies to.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220509142610.128590-5-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
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Revision tags: v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20 |
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| #
d53b0244 |
| 03-Mar-2021 |
Atish Patra <atish.patra@wdc.com> |
dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC
Add YAML DT binding documentation for the Microchip PolarFire SoC.
It is documented at:
https://www.microsemi.com/product
dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC
Add YAML DT binding documentation for the Microchip PolarFire SoC.
It is documented at:
https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
show more ...
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