183d7b156SConor Dooley /* SPDX-License-Identifier: GPL-2.0 */ 283d7b156SConor Dooley /* 383d7b156SConor Dooley * 483d7b156SConor Dooley * Microchip PolarFire SoC (MPFS) 583d7b156SConor Dooley * 683d7b156SConor Dooley * Copyright (c) 2020 Microchip Corporation. All rights reserved. 783d7b156SConor Dooley * 883d7b156SConor Dooley * Author: Conor Dooley <conor.dooley@microchip.com> 983d7b156SConor Dooley * 1083d7b156SConor Dooley */ 1183d7b156SConor Dooley 1283d7b156SConor Dooley #ifndef __SOC_MPFS_H__ 1383d7b156SConor Dooley #define __SOC_MPFS_H__ 1483d7b156SConor Dooley 1583d7b156SConor Dooley #include <linux/types.h> 1683d7b156SConor Dooley #include <linux/of_device.h> 1783d7b156SConor Dooley 1883d7b156SConor Dooley struct mpfs_sys_controller; 1983d7b156SConor Dooley 2083d7b156SConor Dooley struct mpfs_mss_msg { 2183d7b156SConor Dooley u8 cmd_opcode; 2283d7b156SConor Dooley u16 cmd_data_size; 2383d7b156SConor Dooley struct mpfs_mss_response *response; 2483d7b156SConor Dooley u8 *cmd_data; 2583d7b156SConor Dooley u16 mbox_offset; 2683d7b156SConor Dooley u16 resp_offset; 2783d7b156SConor Dooley }; 2883d7b156SConor Dooley 2983d7b156SConor Dooley struct mpfs_mss_response { 3083d7b156SConor Dooley u32 resp_status; 3183d7b156SConor Dooley u32 *resp_msg; 3283d7b156SConor Dooley u16 resp_size; 3383d7b156SConor Dooley }; 3483d7b156SConor Dooley 3583d7b156SConor Dooley #if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) 3683d7b156SConor Dooley 37d0054a47SConor Dooley int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg); 3883d7b156SConor Dooley 39d0054a47SConor Dooley struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev); 4083d7b156SConor Dooley 4183d7b156SConor Dooley #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ 4283d7b156SConor Dooley 43*b56bae2dSConor Dooley #if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) 44*b56bae2dSConor Dooley 45*b56bae2dSConor Dooley u32 mpfs_reset_read(struct device *dev); 46*b56bae2dSConor Dooley 47*b56bae2dSConor Dooley void mpfs_reset_write(struct device *dev, u32 val); 48*b56bae2dSConor Dooley 49*b56bae2dSConor Dooley #endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */ 50*b56bae2dSConor Dooley 5183d7b156SConor Dooley #endif /* __SOC_MPFS_H__ */ 52