1a8fb0a50SBin Meng /*
2a8fb0a50SBin Meng  * Microchip PolarFire SoC MMUART emulation
3a8fb0a50SBin Meng  *
4a8fb0a50SBin Meng  * Copyright (c) 2020 Wind River Systems, Inc.
5a8fb0a50SBin Meng  *
6a8fb0a50SBin Meng  * Author:
7a8fb0a50SBin Meng  *   Bin Meng <bin.meng@windriver.com>
8a8fb0a50SBin Meng  *
9a8fb0a50SBin Meng  * Permission is hereby granted, free of charge, to any person obtaining a copy
10a8fb0a50SBin Meng  * of this software and associated documentation files (the "Software"), to deal
11a8fb0a50SBin Meng  * in the Software without restriction, including without limitation the rights
12a8fb0a50SBin Meng  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13a8fb0a50SBin Meng  * copies of the Software, and to permit persons to whom the Software is
14a8fb0a50SBin Meng  * furnished to do so, subject to the following conditions:
15a8fb0a50SBin Meng  *
16a8fb0a50SBin Meng  * The above copyright notice and this permission notice shall be included in
17a8fb0a50SBin Meng  * all copies or substantial portions of the Software.
18a8fb0a50SBin Meng  *
19a8fb0a50SBin Meng  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20a8fb0a50SBin Meng  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21a8fb0a50SBin Meng  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22a8fb0a50SBin Meng  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23a8fb0a50SBin Meng  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24a8fb0a50SBin Meng  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25a8fb0a50SBin Meng  * THE SOFTWARE.
26a8fb0a50SBin Meng  */
27a8fb0a50SBin Meng 
28a8fb0a50SBin Meng #ifndef HW_MCHP_PFSOC_MMUART_H
29a8fb0a50SBin Meng #define HW_MCHP_PFSOC_MMUART_H
30a8fb0a50SBin Meng 
31*31ca70b5SPhilippe Mathieu-Daudé #include "hw/sysbus.h"
32a8fb0a50SBin Meng #include "hw/char/serial.h"
33a8fb0a50SBin Meng 
34284a66a8SPhilippe Mathieu-Daudé #define MCHP_PFSOC_MMUART_REG_COUNT 13
35a8fb0a50SBin Meng 
36*31ca70b5SPhilippe Mathieu-Daudé #define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
37*31ca70b5SPhilippe Mathieu-Daudé OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
38*31ca70b5SPhilippe Mathieu-Daudé 
39a8fb0a50SBin Meng typedef struct MchpPfSoCMMUartState {
40*31ca70b5SPhilippe Mathieu-Daudé     /*< private >*/
41*31ca70b5SPhilippe Mathieu-Daudé     SysBusDevice parent_obj;
42*31ca70b5SPhilippe Mathieu-Daudé 
43*31ca70b5SPhilippe Mathieu-Daudé     /*< public >*/
4424ce762dSPhilippe Mathieu-Daudé     MemoryRegion container;
45a8fb0a50SBin Meng     MemoryRegion iomem;
46a8fb0a50SBin Meng 
47*31ca70b5SPhilippe Mathieu-Daudé     SerialMM serial_mm;
48a8fb0a50SBin Meng 
49284a66a8SPhilippe Mathieu-Daudé     uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
50a8fb0a50SBin Meng } MchpPfSoCMMUartState;
51a8fb0a50SBin Meng 
52a8fb0a50SBin Meng /**
53a8fb0a50SBin Meng  * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
54a8fb0a50SBin Meng  *
55a8fb0a50SBin Meng  * This is a helper routine for board to create a MMUART device that is
56a8fb0a50SBin Meng  * compatible with Microchip PolarFire SoC.
57a8fb0a50SBin Meng  *
58a8fb0a50SBin Meng  * @sysmem: system memory region to map
59a8fb0a50SBin Meng  * @base: base address of the MMUART registers
60a8fb0a50SBin Meng  * @irq: IRQ number of the MMUART device
61a8fb0a50SBin Meng  * @chr: character device to associate to
62a8fb0a50SBin Meng  *
63a8fb0a50SBin Meng  * @return: a pointer to the device specific control structure
64a8fb0a50SBin Meng  */
65a8fb0a50SBin Meng MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
66a8fb0a50SBin Meng     hwaddr base, qemu_irq irq, Chardev *chr);
67a8fb0a50SBin Meng 
68a8fb0a50SBin Meng #endif /* HW_MCHP_PFSOC_MMUART_H */
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