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Searched full:ltssm (Results 1 – 25 of 42) sorted by relevance

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/openbmc/u-boot/drivers/pci/
H A Dfsl_pci_init.c300 u16 ltssm; in fsl_pci_init() local
449 ltssm = (in_be32(&pci->pex_csr0) in fsl_pci_init()
451 enabled = (ltssm == 0x11) ? 1 : 0; in fsl_pci_init()
461 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { in fsl_pci_init()
463 &ltssm); in fsl_pci_init()
468 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */ in fsl_pci_init()
469 /* enabled = ltssm >= PCI_LTSSM_L0; */ in fsl_pci_init()
470 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); in fsl_pci_init()
471 enabled = ltssm >= PCI_LTSSM_L0; in fsl_pci_init()
474 if (ltssm == 1) { in fsl_pci_init()
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H A Dpcie_imx.c230 u32 rc, ltssm; in imx6_pcie_link_up() local
241 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). in imx6_pcie_link_up()
242 * If (MAC/LTSSM.state == Recovery.RcvrLock) in imx6_pcie_link_up()
247 ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; in imx6_pcie_link_up()
252 if (ltssm != 0x0d) in imx6_pcie_link_up()
454 * wired up for MX6QDL, we need to manually force LTSSM into "detect" in imx6_pcie_assert_core_reset()
455 * state before completely disabling LTSSM, which is a prerequisite in imx6_pcie_assert_core_reset()
639 /* LTSSM enable, starting link. */ in imx_pcie_link_up()
H A Dpcie_layerscape.c71 int ltssm; in ls_pcie_link_up() local
73 ltssm = ls_pcie_ltssm(pcie); in ls_pcie_link_up()
74 if (ltssm < LTSSM_PCIE_L0) in ls_pcie_link_up()
H A Dpcie_dw_mvebu.c396 /* Disable LTSSM state machine to enable configuration */ in pcie_dw_mvebu_pcie_link_up()
413 /* Configuration done. Start LTSSM */ in pcie_dw_mvebu_pcie_link_up()
/openbmc/linux/drivers/usb/mtu3/
H A Dmtu3_core.c73 /* If usb3_en==0, LTSSM will go to SS.Disable state */ in mtu3_ss_func_set()
184 /* Clear U3 LTSSM interrupts status */ in mtu3_intr_status_clear()
217 /* Enable U3 LTSSM interrupts */ in mtu3_intr_enable()
739 u32 ltssm; in mtu3_u3_ltssm_isr() local
741 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR); in mtu3_u3_ltssm_isr()
742 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE); in mtu3_u3_ltssm_isr()
743 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */ in mtu3_u3_ltssm_isr()
744 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm); in mtu3_u3_ltssm_isr()
745 trace_mtu3_u3_ltssm_isr(ltssm); in mtu3_u3_ltssm_isr()
747 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR)) in mtu3_u3_ltssm_isr()
[all …]
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-bt1.c265 * Enable LTSSM and make sure it was able to establish both PHY and in bt1_pcie_start_link()
275 dev_err(pci->dev, "LTSSM failed to set PHY link up\n"); in bt1_pcie_start_link()
283 dev_err(pci->dev, "LTSSM failed to set data link up\n"); in bt1_pcie_start_link()
300 dev_err(pci->dev, "LTSSM failed to get into L0 state\n"); in bt1_pcie_start_link()
380 /* Disable LTSSM for sure */ in bt1_pcie_full_stop_bus()
506 /* Make sure the state is settled (LTSSM is still disabled though) */ in bt1_pcie_cold_start_bus()
H A Dpcie-armada8k.c160 /* Start LTSSM */ in armada8k_pcie_start_link()
174 /* Disable LTSSM state machine to enable configuration */ in armada8k_pcie_host_init()
H A Dpcie-dw-rockchip.c179 * from RC, so enabling LTSSM is the just right place to release #PERST. in rockchip_pcie_start_link()
208 /* LTSSM enable control mode */ in rockchip_pcie_host_init()
H A Dpcie-fu740.c202 /* Enable LTSSM */ in fu740_pcie_start_link()
255 * Assert hold_phy_rst (hold the controller LTSSM in reset after in fu740_pcie_host_init()
H A Dpcie-spear13xx.c74 /* enable ltssm */ in spear13xx_pcie_start_link()
H A Dpcie-tegra194.c981 /* Enable LTSSM */ in tegra_pcie_dw_start_link()
1016 /* Disable LTSSM */ in tegra_pcie_dw_start_link()
1611 * PERST#. So, de-assert LTSSM to bring link to detect state. in tegra_pcie_dw_pme_turnoff()
1707 /* Disable LTSSM */ in pex_ep_event_pex_rst_assert()
1915 /* Enable LTSSM */ in pex_ep_event_pex_rst_deassert()
H A Dpci-imx6.c891 /* Start LTSSM. */ in imx6_pcie_start_link()
959 /* Turn off PCIe LTSSM */ in imx6_pcie_stop_link()
1141 /* Start LTSSM. */ in imx6_add_pcie_ep()
H A Dpci-exynos.c162 /* assert LTSSM enable */ in exynos_pcie_start_link()
H A Dpcie-histb.c175 /* assert LTSSM enable */ in histb_pcie_start_link()
/openbmc/linux/drivers/usb/gadget/udc/
H A Dmv_u3d.h173 u32 ltssm; /* LTSSM control register */ member
180 u32 ltssmstate; /* LTSSM state register */
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-cfg.yaml15 LTSSM, ASPM and so on.
H A Dbaikal,bt1-pcie.yaml102 access some additional PM, Reset-related and LTSSM signals.
H A Dmediatek-pcie.txt31 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
/openbmc/linux/Documentation/ABI/testing/
H A Dconfigfs-spear-pcie-gadget20 link used to enable ltssm and read its status.
/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.h207 /* LTSSM Capabilities register */
321 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
364 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
H A Dpcie-cadence.c17 * Set the LTSSM Detect Quiet state min. delay to 2ms. in cdns_pcie_detect_quiet_min_delay_set()
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_pci.h116 #define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
129 #define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
/openbmc/linux/drivers/pci/controller/
H A Dpci-aardvark.c172 /* LTSSM values in CFG_REG */
315 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
324 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle in advk_pcie_link_active()
325 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0, in advk_pcie_link_active()
338 * Status Mapped to the LTSSM is Link Training mapped to LTSSM in advk_pcie_link_training()
874 * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm in advk_pci_bridge_emul_pcie_conf_read()
/openbmc/linux/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst40 link gives ltssm status.
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml184 The value driven to the PHY is controlled by the LTSSM during USB3

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