15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2df2069acSChunfeng Yun /*
3df2069acSChunfeng Yun * mtu3_core.c - hardware access layer and gadget init/exit of
4df2069acSChunfeng Yun * MediaTek usb3 Dual-Role Controller Driver
5df2069acSChunfeng Yun *
6df2069acSChunfeng Yun * Copyright (C) 2016 MediaTek Inc.
7df2069acSChunfeng Yun *
8df2069acSChunfeng Yun * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9df2069acSChunfeng Yun */
10df2069acSChunfeng Yun
111a46dfeaSChunfeng Yun #include <linux/dma-mapping.h>
12df2069acSChunfeng Yun #include <linux/kernel.h>
13df2069acSChunfeng Yun #include <linux/module.h>
14df2069acSChunfeng Yun #include <linux/of_address.h>
15df2069acSChunfeng Yun #include <linux/of_irq.h>
16df2069acSChunfeng Yun #include <linux/platform_device.h>
17df2069acSChunfeng Yun
18df2069acSChunfeng Yun #include "mtu3.h"
19b26a4052SBen Dooks (Codethink) #include "mtu3_dr.h"
20ae078092SChunfeng Yun #include "mtu3_debug.h"
2183374e03SChunfeng Yun #include "mtu3_trace.h"
22df2069acSChunfeng Yun
ep_fifo_alloc(struct mtu3_ep * mep,u32 seg_size)23df2069acSChunfeng Yun static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
24df2069acSChunfeng Yun {
25df2069acSChunfeng Yun struct mtu3_fifo_info *fifo = mep->fifo;
26df2069acSChunfeng Yun u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
27df2069acSChunfeng Yun u32 start_bit;
28df2069acSChunfeng Yun
29df2069acSChunfeng Yun /* ensure that @mep->fifo_seg_size is power of two */
30df2069acSChunfeng Yun num_bits = roundup_pow_of_two(num_bits);
31df2069acSChunfeng Yun if (num_bits > fifo->limit)
32df2069acSChunfeng Yun return -EINVAL;
33df2069acSChunfeng Yun
34df2069acSChunfeng Yun mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
35df2069acSChunfeng Yun num_bits = num_bits * (mep->slot + 1);
36df2069acSChunfeng Yun start_bit = bitmap_find_next_zero_area(fifo->bitmap,
37df2069acSChunfeng Yun fifo->limit, 0, num_bits, 0);
38df2069acSChunfeng Yun if (start_bit >= fifo->limit)
39df2069acSChunfeng Yun return -EOVERFLOW;
40df2069acSChunfeng Yun
41df2069acSChunfeng Yun bitmap_set(fifo->bitmap, start_bit, num_bits);
42df2069acSChunfeng Yun mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
43df2069acSChunfeng Yun mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
44df2069acSChunfeng Yun
45df2069acSChunfeng Yun dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
46df2069acSChunfeng Yun __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
47df2069acSChunfeng Yun
48df2069acSChunfeng Yun return mep->fifo_addr;
49df2069acSChunfeng Yun }
50df2069acSChunfeng Yun
ep_fifo_free(struct mtu3_ep * mep)51df2069acSChunfeng Yun static void ep_fifo_free(struct mtu3_ep *mep)
52df2069acSChunfeng Yun {
53df2069acSChunfeng Yun struct mtu3_fifo_info *fifo = mep->fifo;
54df2069acSChunfeng Yun u32 addr = mep->fifo_addr;
55df2069acSChunfeng Yun u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
56df2069acSChunfeng Yun u32 start_bit;
57df2069acSChunfeng Yun
58df2069acSChunfeng Yun if (unlikely(addr < fifo->base || bits > fifo->limit))
59df2069acSChunfeng Yun return;
60df2069acSChunfeng Yun
61df2069acSChunfeng Yun start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
62df2069acSChunfeng Yun bitmap_clear(fifo->bitmap, start_bit, bits);
63df2069acSChunfeng Yun mep->fifo_size = 0;
64df2069acSChunfeng Yun mep->fifo_seg_size = 0;
65df2069acSChunfeng Yun
66df2069acSChunfeng Yun dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
67df2069acSChunfeng Yun __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
68df2069acSChunfeng Yun }
69df2069acSChunfeng Yun
70a29de31bSChunfeng Yun /* enable/disable U3D SS function */
mtu3_ss_func_set(struct mtu3 * mtu,bool enable)71a29de31bSChunfeng Yun static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
72a29de31bSChunfeng Yun {
73a29de31bSChunfeng Yun /* If usb3_en==0, LTSSM will go to SS.Disable state */
74a29de31bSChunfeng Yun if (enable)
75a29de31bSChunfeng Yun mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
76a29de31bSChunfeng Yun else
77a29de31bSChunfeng Yun mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
78a29de31bSChunfeng Yun
79a29de31bSChunfeng Yun dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
80a29de31bSChunfeng Yun }
81a29de31bSChunfeng Yun
82df2069acSChunfeng Yun /* set/clear U3D HS device soft connect */
mtu3_hs_softconn_set(struct mtu3 * mtu,bool enable)83a29de31bSChunfeng Yun static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
84df2069acSChunfeng Yun {
85df2069acSChunfeng Yun if (enable) {
86df2069acSChunfeng Yun mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87df2069acSChunfeng Yun SOFT_CONN | SUSPENDM_ENABLE);
88df2069acSChunfeng Yun } else {
89df2069acSChunfeng Yun mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
90df2069acSChunfeng Yun SOFT_CONN | SUSPENDM_ENABLE);
91df2069acSChunfeng Yun }
92df2069acSChunfeng Yun dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
93df2069acSChunfeng Yun }
94df2069acSChunfeng Yun
95df2069acSChunfeng Yun /* only port0 of U2/U3 supports device mode */
mtu3_device_enable(struct mtu3 * mtu)96df2069acSChunfeng Yun static int mtu3_device_enable(struct mtu3 *mtu)
97df2069acSChunfeng Yun {
98df2069acSChunfeng Yun void __iomem *ibase = mtu->ippc_base;
99df2069acSChunfeng Yun u32 check_clk = 0;
100df2069acSChunfeng Yun
101df2069acSChunfeng Yun mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
102a29de31bSChunfeng Yun
103*269f49ffSChunfeng Yun if (mtu->u3_capable) {
104a29de31bSChunfeng Yun check_clk = SSUSB_U3_MAC_RST_B_STS;
105a29de31bSChunfeng Yun mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
106a29de31bSChunfeng Yun (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
107a29de31bSChunfeng Yun SSUSB_U3_PORT_HOST_SEL));
108a29de31bSChunfeng Yun }
109df2069acSChunfeng Yun mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
110df2069acSChunfeng Yun (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
111df2069acSChunfeng Yun SSUSB_U2_PORT_HOST_SEL));
1124da72e6dSChunfeng Yun
11378af87b8SChunfeng Yun if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
114df2069acSChunfeng Yun mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
115*269f49ffSChunfeng Yun if (mtu->u3_capable)
11678af87b8SChunfeng Yun mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
11778af87b8SChunfeng Yun SSUSB_U3_PORT_DUAL_MODE);
11878af87b8SChunfeng Yun }
119df2069acSChunfeng Yun
120b3f4e727SChunfeng Yun return ssusb_check_clocks(mtu->ssusb, check_clk);
121df2069acSChunfeng Yun }
122df2069acSChunfeng Yun
mtu3_device_disable(struct mtu3 * mtu)123df2069acSChunfeng Yun static void mtu3_device_disable(struct mtu3 *mtu)
124df2069acSChunfeng Yun {
125df2069acSChunfeng Yun void __iomem *ibase = mtu->ippc_base;
126df2069acSChunfeng Yun
127*269f49ffSChunfeng Yun if (mtu->u3_capable)
128a29de31bSChunfeng Yun mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
129a29de31bSChunfeng Yun (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
130a29de31bSChunfeng Yun
131df2069acSChunfeng Yun mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
132df2069acSChunfeng Yun SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
1334da72e6dSChunfeng Yun
134f1e51e99SChunfeng Yun if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
135df2069acSChunfeng Yun mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
136*269f49ffSChunfeng Yun if (mtu->u3_capable)
137f1e51e99SChunfeng Yun mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
138f1e51e99SChunfeng Yun SSUSB_U3_PORT_DUAL_MODE);
139f1e51e99SChunfeng Yun }
1404da72e6dSChunfeng Yun
141df2069acSChunfeng Yun mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
142df2069acSChunfeng Yun }
143df2069acSChunfeng Yun
mtu3_dev_power_on(struct mtu3 * mtu)14462448315SChunfeng Yun static void mtu3_dev_power_on(struct mtu3 *mtu)
14562448315SChunfeng Yun {
14662448315SChunfeng Yun void __iomem *ibase = mtu->ippc_base;
14762448315SChunfeng Yun
14862448315SChunfeng Yun mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
149*269f49ffSChunfeng Yun if (mtu->u3_capable)
15062448315SChunfeng Yun mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
15162448315SChunfeng Yun
15262448315SChunfeng Yun mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
15362448315SChunfeng Yun }
15462448315SChunfeng Yun
mtu3_dev_power_down(struct mtu3 * mtu)15562448315SChunfeng Yun static void mtu3_dev_power_down(struct mtu3 *mtu)
15662448315SChunfeng Yun {
15762448315SChunfeng Yun void __iomem *ibase = mtu->ippc_base;
15862448315SChunfeng Yun
159*269f49ffSChunfeng Yun if (mtu->u3_capable)
16062448315SChunfeng Yun mtu3_setbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
16162448315SChunfeng Yun
16262448315SChunfeng Yun mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
16362448315SChunfeng Yun mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
16462448315SChunfeng Yun }
16562448315SChunfeng Yun
166df2069acSChunfeng Yun /* reset U3D's device module. */
mtu3_device_reset(struct mtu3 * mtu)167df2069acSChunfeng Yun static void mtu3_device_reset(struct mtu3 *mtu)
168df2069acSChunfeng Yun {
169df2069acSChunfeng Yun void __iomem *ibase = mtu->ippc_base;
170df2069acSChunfeng Yun
171df2069acSChunfeng Yun mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
172df2069acSChunfeng Yun udelay(1);
173df2069acSChunfeng Yun mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
174df2069acSChunfeng Yun }
175df2069acSChunfeng Yun
mtu3_intr_status_clear(struct mtu3 * mtu)176df2069acSChunfeng Yun static void mtu3_intr_status_clear(struct mtu3 *mtu)
177df2069acSChunfeng Yun {
178df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
179df2069acSChunfeng Yun
180df2069acSChunfeng Yun /* Clear EP0 and Tx/Rx EPn interrupts status */
181df2069acSChunfeng Yun mtu3_writel(mbase, U3D_EPISR, ~0x0);
182df2069acSChunfeng Yun /* Clear U2 USB common interrupts status */
183df2069acSChunfeng Yun mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
184a29de31bSChunfeng Yun /* Clear U3 LTSSM interrupts status */
185a29de31bSChunfeng Yun mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
186df2069acSChunfeng Yun /* Clear speed change interrupt status */
187df2069acSChunfeng Yun mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
188b7d5c3caSChunfeng Yun /* Clear QMU interrupt status */
189b7d5c3caSChunfeng Yun mtu3_writel(mbase, U3D_QISAR0, ~0x0);
190b7d5c3caSChunfeng Yun }
191b7d5c3caSChunfeng Yun
192b7d5c3caSChunfeng Yun /* disable all interrupts */
mtu3_intr_disable(struct mtu3 * mtu)193b7d5c3caSChunfeng Yun static void mtu3_intr_disable(struct mtu3 *mtu)
194b7d5c3caSChunfeng Yun {
195b7d5c3caSChunfeng Yun /* Disable level 1 interrupts */
196b7d5c3caSChunfeng Yun mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
197b7d5c3caSChunfeng Yun /* Disable endpoint interrupts */
198b7d5c3caSChunfeng Yun mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
199b7d5c3caSChunfeng Yun mtu3_intr_status_clear(mtu);
200df2069acSChunfeng Yun }
201df2069acSChunfeng Yun
202df2069acSChunfeng Yun /* enable system global interrupt */
mtu3_intr_enable(struct mtu3 * mtu)203df2069acSChunfeng Yun static void mtu3_intr_enable(struct mtu3 *mtu)
204df2069acSChunfeng Yun {
205df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
206df2069acSChunfeng Yun u32 value;
207df2069acSChunfeng Yun
208df2069acSChunfeng Yun /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
209a29de31bSChunfeng Yun value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
210df2069acSChunfeng Yun mtu3_writel(mbase, U3D_LV1IESR, value);
211df2069acSChunfeng Yun
212df2069acSChunfeng Yun /* Enable U2 common USB interrupts */
21329ae096eSChunfeng Yun value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
214df2069acSChunfeng Yun mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
215df2069acSChunfeng Yun
216*269f49ffSChunfeng Yun if (mtu->u3_capable) {
217a29de31bSChunfeng Yun /* Enable U3 LTSSM interrupts */
2180eae4958SChunfeng Yun value = HOT_RST_INTR | WARM_RST_INTR |
2190eae4958SChunfeng Yun ENTER_U3_INTR | EXIT_U3_INTR;
220a29de31bSChunfeng Yun mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
221a29de31bSChunfeng Yun }
222a29de31bSChunfeng Yun
223df2069acSChunfeng Yun /* Enable QMU interrupts. */
224df2069acSChunfeng Yun value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
225df2069acSChunfeng Yun RXQ_LENERR_INT | RXQ_ZLPERR_INT;
226df2069acSChunfeng Yun mtu3_writel(mbase, U3D_QIESR1, value);
227df2069acSChunfeng Yun
228df2069acSChunfeng Yun /* Enable speed change interrupt */
229df2069acSChunfeng Yun mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
230df2069acSChunfeng Yun }
231df2069acSChunfeng Yun
mtu3_set_speed(struct mtu3 * mtu,enum usb_device_speed speed)2322c09bdaaSChunfeng Yun static void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
233dc4c1aa7SChunfeng Yun {
234dc4c1aa7SChunfeng Yun void __iomem *mbase = mtu->mac_base;
235dc4c1aa7SChunfeng Yun
236dc4c1aa7SChunfeng Yun if (speed > mtu->max_speed)
237dc4c1aa7SChunfeng Yun speed = mtu->max_speed;
238dc4c1aa7SChunfeng Yun
239dc4c1aa7SChunfeng Yun switch (speed) {
240dc4c1aa7SChunfeng Yun case USB_SPEED_FULL:
241dc4c1aa7SChunfeng Yun /* disable U3 SS function */
242dc4c1aa7SChunfeng Yun mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
243dc4c1aa7SChunfeng Yun /* disable HS function */
244dc4c1aa7SChunfeng Yun mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
245dc4c1aa7SChunfeng Yun break;
246dc4c1aa7SChunfeng Yun case USB_SPEED_HIGH:
247dc4c1aa7SChunfeng Yun mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
248dc4c1aa7SChunfeng Yun /* HS/FS detected by HW */
249dc4c1aa7SChunfeng Yun mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
250dc4c1aa7SChunfeng Yun break;
251dc4c1aa7SChunfeng Yun case USB_SPEED_SUPER:
252e88f2851SChunfeng Yun mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
253dc4c1aa7SChunfeng Yun mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
254dc4c1aa7SChunfeng Yun SSUSB_U3_PORT_SSP_SPEED);
255dc4c1aa7SChunfeng Yun break;
256dc4c1aa7SChunfeng Yun case USB_SPEED_SUPER_PLUS:
257e88f2851SChunfeng Yun mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
258dc4c1aa7SChunfeng Yun mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
259dc4c1aa7SChunfeng Yun SSUSB_U3_PORT_SSP_SPEED);
260dc4c1aa7SChunfeng Yun break;
261dc4c1aa7SChunfeng Yun default:
262dc4c1aa7SChunfeng Yun dev_err(mtu->dev, "invalid speed: %s\n",
263dc4c1aa7SChunfeng Yun usb_speed_string(speed));
264dc4c1aa7SChunfeng Yun return;
265dc4c1aa7SChunfeng Yun }
266dc4c1aa7SChunfeng Yun
267dc4c1aa7SChunfeng Yun mtu->speed = speed;
268dc4c1aa7SChunfeng Yun dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
269dc4c1aa7SChunfeng Yun }
270f55df11eSChunfeng Yun
271f55df11eSChunfeng Yun /* CSR registers will be reset to default value if port is disabled */
mtu3_csr_init(struct mtu3 * mtu)272f55df11eSChunfeng Yun static void mtu3_csr_init(struct mtu3 *mtu)
273f55df11eSChunfeng Yun {
274f55df11eSChunfeng Yun void __iomem *mbase = mtu->mac_base;
275f55df11eSChunfeng Yun
276*269f49ffSChunfeng Yun if (mtu->u3_capable) {
277f55df11eSChunfeng Yun /* disable LGO_U1/U2 by default */
278f55df11eSChunfeng Yun mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
279f55df11eSChunfeng Yun SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
280f55df11eSChunfeng Yun /* enable accept LGO_U1/U2 link command from host */
281f55df11eSChunfeng Yun mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
282f55df11eSChunfeng Yun SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
283f55df11eSChunfeng Yun /* device responses to u3_exit from host automatically */
284f55df11eSChunfeng Yun mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
285f55df11eSChunfeng Yun /* automatically build U2 link when U3 detect fail */
286f55df11eSChunfeng Yun mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
287f55df11eSChunfeng Yun /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
288f55df11eSChunfeng Yun mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
289f55df11eSChunfeng Yun }
290f55df11eSChunfeng Yun
291f55df11eSChunfeng Yun /* delay about 0.1us from detecting reset to send chirp-K */
292f55df11eSChunfeng Yun mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
293f55df11eSChunfeng Yun /* enable automatical HWRW from L1 */
294f55df11eSChunfeng Yun mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
295f55df11eSChunfeng Yun }
296f55df11eSChunfeng Yun
2975fcdd6deSChunfeng Yun /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
mtu3_ep_reset(struct mtu3_ep * mep)2985fcdd6deSChunfeng Yun static void mtu3_ep_reset(struct mtu3_ep *mep)
2995fcdd6deSChunfeng Yun {
3005fcdd6deSChunfeng Yun struct mtu3 *mtu = mep->mtu;
3015fcdd6deSChunfeng Yun u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
3025fcdd6deSChunfeng Yun
3035fcdd6deSChunfeng Yun mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
3045fcdd6deSChunfeng Yun mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
3055fcdd6deSChunfeng Yun }
3065fcdd6deSChunfeng Yun
307df2069acSChunfeng Yun /* set/clear the stall and toggle bits for non-ep0 */
mtu3_ep_stall_set(struct mtu3_ep * mep,bool set)308df2069acSChunfeng Yun void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
309df2069acSChunfeng Yun {
310df2069acSChunfeng Yun struct mtu3 *mtu = mep->mtu;
311df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
312df2069acSChunfeng Yun u8 epnum = mep->epnum;
313df2069acSChunfeng Yun u32 csr;
314df2069acSChunfeng Yun
315df2069acSChunfeng Yun if (mep->is_in) { /* TX */
316df2069acSChunfeng Yun csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
317df2069acSChunfeng Yun if (set)
318df2069acSChunfeng Yun csr |= TX_SENDSTALL;
319df2069acSChunfeng Yun else
320df2069acSChunfeng Yun csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
321df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
322df2069acSChunfeng Yun } else { /* RX */
323df2069acSChunfeng Yun csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
324df2069acSChunfeng Yun if (set)
325df2069acSChunfeng Yun csr |= RX_SENDSTALL;
326df2069acSChunfeng Yun else
327df2069acSChunfeng Yun csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
328df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
329df2069acSChunfeng Yun }
330df2069acSChunfeng Yun
331df2069acSChunfeng Yun if (!set) {
3325fcdd6deSChunfeng Yun mtu3_ep_reset(mep);
333df2069acSChunfeng Yun mep->flags &= ~MTU3_EP_STALL;
334df2069acSChunfeng Yun } else {
335df2069acSChunfeng Yun mep->flags |= MTU3_EP_STALL;
336df2069acSChunfeng Yun }
337df2069acSChunfeng Yun
338df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s: %s\n", mep->name,
339df2069acSChunfeng Yun set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
340df2069acSChunfeng Yun }
341df2069acSChunfeng Yun
mtu3_dev_on_off(struct mtu3 * mtu,int is_on)342a29de31bSChunfeng Yun void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
343a29de31bSChunfeng Yun {
344*269f49ffSChunfeng Yun if (mtu->u3_capable && mtu->speed >= USB_SPEED_SUPER)
345a29de31bSChunfeng Yun mtu3_ss_func_set(mtu, is_on);
346a29de31bSChunfeng Yun else
347a29de31bSChunfeng Yun mtu3_hs_softconn_set(mtu, is_on);
348a29de31bSChunfeng Yun
349a29de31bSChunfeng Yun dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
350dc4c1aa7SChunfeng Yun usb_speed_string(mtu->speed), is_on ? "+" : "-");
351a29de31bSChunfeng Yun }
352a29de31bSChunfeng Yun
mtu3_start(struct mtu3 * mtu)353df2069acSChunfeng Yun void mtu3_start(struct mtu3 *mtu)
354df2069acSChunfeng Yun {
355df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
356df2069acSChunfeng Yun
357df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
358df2069acSChunfeng Yun mtu3_readl(mbase, U3D_DEVICE_CONTROL));
359df2069acSChunfeng Yun
36062448315SChunfeng Yun mtu3_dev_power_on(mtu);
361f55df11eSChunfeng Yun mtu3_csr_init(mtu);
362dc4c1aa7SChunfeng Yun mtu3_set_speed(mtu, mtu->speed);
363a29de31bSChunfeng Yun
364df2069acSChunfeng Yun /* Initialize the default interrupts */
365df2069acSChunfeng Yun mtu3_intr_enable(mtu);
366df2069acSChunfeng Yun mtu->is_active = 1;
367df2069acSChunfeng Yun
368df2069acSChunfeng Yun if (mtu->softconnect)
369a29de31bSChunfeng Yun mtu3_dev_on_off(mtu, 1);
370df2069acSChunfeng Yun }
371df2069acSChunfeng Yun
mtu3_stop(struct mtu3 * mtu)372df2069acSChunfeng Yun void mtu3_stop(struct mtu3 *mtu)
373df2069acSChunfeng Yun {
374df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s\n", __func__);
375df2069acSChunfeng Yun
376df2069acSChunfeng Yun mtu3_intr_disable(mtu);
377df2069acSChunfeng Yun
378df2069acSChunfeng Yun if (mtu->softconnect)
379a29de31bSChunfeng Yun mtu3_dev_on_off(mtu, 0);
380df2069acSChunfeng Yun
381df2069acSChunfeng Yun mtu->is_active = 0;
38262448315SChunfeng Yun mtu3_dev_power_down(mtu);
383df2069acSChunfeng Yun }
384df2069acSChunfeng Yun
mtu3_dev_suspend(struct mtu3 * mtu)385427c6642SChunfeng Yun static void mtu3_dev_suspend(struct mtu3 *mtu)
386427c6642SChunfeng Yun {
387427c6642SChunfeng Yun if (!mtu->is_active)
388427c6642SChunfeng Yun return;
389427c6642SChunfeng Yun
390427c6642SChunfeng Yun mtu3_intr_disable(mtu);
391427c6642SChunfeng Yun mtu3_dev_power_down(mtu);
392427c6642SChunfeng Yun }
393427c6642SChunfeng Yun
mtu3_dev_resume(struct mtu3 * mtu)394427c6642SChunfeng Yun static void mtu3_dev_resume(struct mtu3 *mtu)
395427c6642SChunfeng Yun {
396427c6642SChunfeng Yun if (!mtu->is_active)
397427c6642SChunfeng Yun return;
398427c6642SChunfeng Yun
399427c6642SChunfeng Yun mtu3_dev_power_on(mtu);
400427c6642SChunfeng Yun mtu3_intr_enable(mtu);
401427c6642SChunfeng Yun }
402427c6642SChunfeng Yun
403df2069acSChunfeng Yun /* for non-ep0 */
mtu3_config_ep(struct mtu3 * mtu,struct mtu3_ep * mep,int interval,int burst,int mult)404df2069acSChunfeng Yun int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
405df2069acSChunfeng Yun int interval, int burst, int mult)
406df2069acSChunfeng Yun {
407df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
4084c5964b4SChunfeng Yun bool gen2cp = mtu->gen2cp;
409df2069acSChunfeng Yun int epnum = mep->epnum;
410df2069acSChunfeng Yun u32 csr0, csr1, csr2;
411df2069acSChunfeng Yun int fifo_sgsz, fifo_addr;
412df2069acSChunfeng Yun int num_pkts;
413df2069acSChunfeng Yun
414df2069acSChunfeng Yun fifo_addr = ep_fifo_alloc(mep, mep->maxp);
415df2069acSChunfeng Yun if (fifo_addr < 0) {
416df2069acSChunfeng Yun dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
417df2069acSChunfeng Yun return -ENOMEM;
418df2069acSChunfeng Yun }
419df2069acSChunfeng Yun fifo_sgsz = ilog2(mep->fifo_seg_size);
420df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
421df2069acSChunfeng Yun mep->fifo_seg_size, mep->fifo_size);
422df2069acSChunfeng Yun
423df2069acSChunfeng Yun if (mep->is_in) {
424df2069acSChunfeng Yun csr0 = TX_TXMAXPKTSZ(mep->maxp);
425df2069acSChunfeng Yun csr0 |= TX_DMAREQEN;
426df2069acSChunfeng Yun
427df2069acSChunfeng Yun num_pkts = (burst + 1) * (mult + 1) - 1;
428df2069acSChunfeng Yun csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
4294c5964b4SChunfeng Yun csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
430df2069acSChunfeng Yun
431df2069acSChunfeng Yun csr2 = TX_FIFOADDR(fifo_addr >> 4);
432df2069acSChunfeng Yun csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
433df2069acSChunfeng Yun
434df2069acSChunfeng Yun switch (mep->type) {
435df2069acSChunfeng Yun case USB_ENDPOINT_XFER_BULK:
436df2069acSChunfeng Yun csr1 |= TX_TYPE(TYPE_BULK);
437df2069acSChunfeng Yun break;
438df2069acSChunfeng Yun case USB_ENDPOINT_XFER_ISOC:
439df2069acSChunfeng Yun csr1 |= TX_TYPE(TYPE_ISO);
440df2069acSChunfeng Yun csr2 |= TX_BINTERVAL(interval);
441df2069acSChunfeng Yun break;
442df2069acSChunfeng Yun case USB_ENDPOINT_XFER_INT:
443df2069acSChunfeng Yun csr1 |= TX_TYPE(TYPE_INT);
444df2069acSChunfeng Yun csr2 |= TX_BINTERVAL(interval);
445df2069acSChunfeng Yun break;
446df2069acSChunfeng Yun }
447df2069acSChunfeng Yun
448df2069acSChunfeng Yun /* Enable QMU Done interrupt */
449df2069acSChunfeng Yun mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
450df2069acSChunfeng Yun
451df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
452df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
453df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
454df2069acSChunfeng Yun
455df2069acSChunfeng Yun dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
456df2069acSChunfeng Yun epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
457df2069acSChunfeng Yun mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
458df2069acSChunfeng Yun mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
459df2069acSChunfeng Yun } else {
460df2069acSChunfeng Yun csr0 = RX_RXMAXPKTSZ(mep->maxp);
461df2069acSChunfeng Yun csr0 |= RX_DMAREQEN;
462df2069acSChunfeng Yun
463df2069acSChunfeng Yun num_pkts = (burst + 1) * (mult + 1) - 1;
464df2069acSChunfeng Yun csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
4654c5964b4SChunfeng Yun csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
466df2069acSChunfeng Yun
467df2069acSChunfeng Yun csr2 = RX_FIFOADDR(fifo_addr >> 4);
468df2069acSChunfeng Yun csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
469df2069acSChunfeng Yun
470df2069acSChunfeng Yun switch (mep->type) {
471df2069acSChunfeng Yun case USB_ENDPOINT_XFER_BULK:
472df2069acSChunfeng Yun csr1 |= RX_TYPE(TYPE_BULK);
473df2069acSChunfeng Yun break;
474df2069acSChunfeng Yun case USB_ENDPOINT_XFER_ISOC:
475df2069acSChunfeng Yun csr1 |= RX_TYPE(TYPE_ISO);
476df2069acSChunfeng Yun csr2 |= RX_BINTERVAL(interval);
477df2069acSChunfeng Yun break;
478df2069acSChunfeng Yun case USB_ENDPOINT_XFER_INT:
479df2069acSChunfeng Yun csr1 |= RX_TYPE(TYPE_INT);
480df2069acSChunfeng Yun csr2 |= RX_BINTERVAL(interval);
481df2069acSChunfeng Yun break;
482df2069acSChunfeng Yun }
483df2069acSChunfeng Yun
484df2069acSChunfeng Yun /*Enable QMU Done interrupt */
485df2069acSChunfeng Yun mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
486df2069acSChunfeng Yun
487df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
488df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
489df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
490df2069acSChunfeng Yun
491df2069acSChunfeng Yun dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
492df2069acSChunfeng Yun epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
493df2069acSChunfeng Yun mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
494df2069acSChunfeng Yun mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
495df2069acSChunfeng Yun }
496df2069acSChunfeng Yun
497df2069acSChunfeng Yun dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
498df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
499df2069acSChunfeng Yun __func__, mep->name, mep->fifo_addr, mep->fifo_size,
500df2069acSChunfeng Yun fifo_sgsz, mep->fifo_seg_size);
501df2069acSChunfeng Yun
502df2069acSChunfeng Yun return 0;
503df2069acSChunfeng Yun }
504df2069acSChunfeng Yun
505df2069acSChunfeng Yun /* for non-ep0 */
mtu3_deconfig_ep(struct mtu3 * mtu,struct mtu3_ep * mep)506df2069acSChunfeng Yun void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
507df2069acSChunfeng Yun {
508df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
509df2069acSChunfeng Yun int epnum = mep->epnum;
510df2069acSChunfeng Yun
511df2069acSChunfeng Yun if (mep->is_in) {
512df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
513df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
514df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
515df2069acSChunfeng Yun mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
516df2069acSChunfeng Yun } else {
517df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
518df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
519df2069acSChunfeng Yun mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
520df2069acSChunfeng Yun mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
521df2069acSChunfeng Yun }
522df2069acSChunfeng Yun
5235fcdd6deSChunfeng Yun mtu3_ep_reset(mep);
524df2069acSChunfeng Yun ep_fifo_free(mep);
525df2069acSChunfeng Yun
526df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
527df2069acSChunfeng Yun }
528df2069acSChunfeng Yun
529df2069acSChunfeng Yun /*
530a29de31bSChunfeng Yun * Two scenarios:
531a29de31bSChunfeng Yun * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
532a29de31bSChunfeng Yun * are separated;
533a29de31bSChunfeng Yun * 2. when supports only HS, the fifo is shared for all EPs, and
534df2069acSChunfeng Yun * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
535df2069acSChunfeng Yun * the total fifo size of non-ep0, and ep0's is fixed to 64B,
536df2069acSChunfeng Yun * so the total fifo size is 64B + @EPNTXFFSZ;
537df2069acSChunfeng Yun * Due to the first 64B should be reserved for EP0, non-ep0's fifo
538df2069acSChunfeng Yun * starts from offset 64 and are divided into two equal parts for
539df2069acSChunfeng Yun * TX or RX EPs for simplification.
540df2069acSChunfeng Yun */
get_ep_fifo_config(struct mtu3 * mtu)541df2069acSChunfeng Yun static void get_ep_fifo_config(struct mtu3 *mtu)
542df2069acSChunfeng Yun {
543df2069acSChunfeng Yun struct mtu3_fifo_info *tx_fifo;
544df2069acSChunfeng Yun struct mtu3_fifo_info *rx_fifo;
545df2069acSChunfeng Yun u32 fifosize;
546df2069acSChunfeng Yun
547*269f49ffSChunfeng Yun if (mtu->separate_fifo) {
548a29de31bSChunfeng Yun fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
549a29de31bSChunfeng Yun tx_fifo = &mtu->tx_fifo;
550a29de31bSChunfeng Yun tx_fifo->base = 0;
551a29de31bSChunfeng Yun tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
552a29de31bSChunfeng Yun bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
553a29de31bSChunfeng Yun
554a29de31bSChunfeng Yun fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
555a29de31bSChunfeng Yun rx_fifo = &mtu->rx_fifo;
556a29de31bSChunfeng Yun rx_fifo->base = 0;
557a29de31bSChunfeng Yun rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
558a29de31bSChunfeng Yun bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
559a29de31bSChunfeng Yun mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
560a29de31bSChunfeng Yun } else {
561df2069acSChunfeng Yun fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
562df2069acSChunfeng Yun tx_fifo = &mtu->tx_fifo;
563df2069acSChunfeng Yun tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
564df2069acSChunfeng Yun tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
565df2069acSChunfeng Yun bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
566df2069acSChunfeng Yun
567df2069acSChunfeng Yun rx_fifo = &mtu->rx_fifo;
568df2069acSChunfeng Yun rx_fifo->base =
569df2069acSChunfeng Yun tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
570df2069acSChunfeng Yun rx_fifo->limit = tx_fifo->limit;
571df2069acSChunfeng Yun bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
572df2069acSChunfeng Yun mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
573a29de31bSChunfeng Yun }
574df2069acSChunfeng Yun
575df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
576df2069acSChunfeng Yun __func__, tx_fifo->base, tx_fifo->limit,
577df2069acSChunfeng Yun rx_fifo->base, rx_fifo->limit);
578df2069acSChunfeng Yun }
579df2069acSChunfeng Yun
mtu3_ep0_setup(struct mtu3 * mtu)58032ab701dSChunfeng Yun static void mtu3_ep0_setup(struct mtu3 *mtu)
581df2069acSChunfeng Yun {
582df2069acSChunfeng Yun u32 maxpacket = mtu->g.ep0->maxpacket;
583df2069acSChunfeng Yun u32 csr;
584df2069acSChunfeng Yun
585df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
586df2069acSChunfeng Yun
587df2069acSChunfeng Yun csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
588df2069acSChunfeng Yun csr &= ~EP0_MAXPKTSZ_MSK;
589df2069acSChunfeng Yun csr |= EP0_MAXPKTSZ(maxpacket);
590df2069acSChunfeng Yun csr &= EP0_W1C_BITS;
591df2069acSChunfeng Yun mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
592df2069acSChunfeng Yun
593df2069acSChunfeng Yun /* Enable EP0 interrupt */
59494552090SChunfeng Yun mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
595df2069acSChunfeng Yun }
596df2069acSChunfeng Yun
mtu3_mem_alloc(struct mtu3 * mtu)597df2069acSChunfeng Yun static int mtu3_mem_alloc(struct mtu3 *mtu)
598df2069acSChunfeng Yun {
599df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
600df2069acSChunfeng Yun struct mtu3_ep *ep_array;
601df2069acSChunfeng Yun int in_ep_num, out_ep_num;
602220d88eaSChunfeng Yun u32 cap_epinfo;
603df2069acSChunfeng Yun int ret;
604df2069acSChunfeng Yun int i;
605df2069acSChunfeng Yun
606df2069acSChunfeng Yun cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
607df2069acSChunfeng Yun in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
608df2069acSChunfeng Yun out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
609df2069acSChunfeng Yun
610df2069acSChunfeng Yun dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
611df2069acSChunfeng Yun mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
612df2069acSChunfeng Yun mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
613df2069acSChunfeng Yun
614df2069acSChunfeng Yun /* one for ep0, another is reserved */
615df2069acSChunfeng Yun mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
616df2069acSChunfeng Yun ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
617df2069acSChunfeng Yun if (ep_array == NULL)
618df2069acSChunfeng Yun return -ENOMEM;
619df2069acSChunfeng Yun
620df2069acSChunfeng Yun mtu->ep_array = ep_array;
621df2069acSChunfeng Yun mtu->in_eps = ep_array;
622df2069acSChunfeng Yun mtu->out_eps = &ep_array[mtu->num_eps];
623df2069acSChunfeng Yun /* ep0 uses in_eps[0], out_eps[0] is reserved */
624df2069acSChunfeng Yun mtu->ep0 = mtu->in_eps;
625df2069acSChunfeng Yun mtu->ep0->mtu = mtu;
626df2069acSChunfeng Yun mtu->ep0->epnum = 0;
627df2069acSChunfeng Yun
628df2069acSChunfeng Yun for (i = 1; i < mtu->num_eps; i++) {
629df2069acSChunfeng Yun struct mtu3_ep *mep = mtu->in_eps + i;
630df2069acSChunfeng Yun
631df2069acSChunfeng Yun mep->fifo = &mtu->tx_fifo;
632df2069acSChunfeng Yun mep = mtu->out_eps + i;
633df2069acSChunfeng Yun mep->fifo = &mtu->rx_fifo;
634df2069acSChunfeng Yun }
635df2069acSChunfeng Yun
636df2069acSChunfeng Yun get_ep_fifo_config(mtu);
637df2069acSChunfeng Yun
638df2069acSChunfeng Yun ret = mtu3_qmu_init(mtu);
639df2069acSChunfeng Yun if (ret)
640df2069acSChunfeng Yun kfree(mtu->ep_array);
641df2069acSChunfeng Yun
642df2069acSChunfeng Yun return ret;
643df2069acSChunfeng Yun }
644df2069acSChunfeng Yun
mtu3_mem_free(struct mtu3 * mtu)645df2069acSChunfeng Yun static void mtu3_mem_free(struct mtu3 *mtu)
646df2069acSChunfeng Yun {
647df2069acSChunfeng Yun mtu3_qmu_exit(mtu);
648df2069acSChunfeng Yun kfree(mtu->ep_array);
649df2069acSChunfeng Yun }
650df2069acSChunfeng Yun
mtu3_regs_init(struct mtu3 * mtu)651df2069acSChunfeng Yun static void mtu3_regs_init(struct mtu3 *mtu)
652df2069acSChunfeng Yun {
653df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
654df2069acSChunfeng Yun
655df2069acSChunfeng Yun /* be sure interrupts are disabled before registration of ISR */
656df2069acSChunfeng Yun mtu3_intr_disable(mtu);
657df2069acSChunfeng Yun
658f55df11eSChunfeng Yun mtu3_csr_init(mtu);
659a29de31bSChunfeng Yun
660df2069acSChunfeng Yun /* U2/U3 detected by HW */
661df2069acSChunfeng Yun mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
662df2069acSChunfeng Yun /* vbus detected by HW */
663df2069acSChunfeng Yun mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
66448e0d373SChunfeng Yun /* use new QMU format when HW version >= 0x1003 */
66548e0d373SChunfeng Yun if (mtu->gen2cp)
66648e0d373SChunfeng Yun mtu3_writel(mbase, U3D_QFCR, ~0x0);
667df2069acSChunfeng Yun }
668df2069acSChunfeng Yun
mtu3_link_isr(struct mtu3 * mtu)669df2069acSChunfeng Yun static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
670df2069acSChunfeng Yun {
671df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
672df2069acSChunfeng Yun enum usb_device_speed udev_speed;
673df2069acSChunfeng Yun u32 maxpkt = 64;
674df2069acSChunfeng Yun u32 link;
675df2069acSChunfeng Yun u32 speed;
676df2069acSChunfeng Yun
677df2069acSChunfeng Yun link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
678df2069acSChunfeng Yun link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
679df2069acSChunfeng Yun mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
680df2069acSChunfeng Yun dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
681df2069acSChunfeng Yun
682df2069acSChunfeng Yun if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
683df2069acSChunfeng Yun return IRQ_NONE;
684df2069acSChunfeng Yun
685df2069acSChunfeng Yun speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
686df2069acSChunfeng Yun
687df2069acSChunfeng Yun switch (speed) {
688df2069acSChunfeng Yun case MTU3_SPEED_FULL:
689df2069acSChunfeng Yun udev_speed = USB_SPEED_FULL;
690df2069acSChunfeng Yun /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
691df2069acSChunfeng Yun mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
692df2069acSChunfeng Yun | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
693df2069acSChunfeng Yun mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
694df2069acSChunfeng Yun LPM_BESL_STALL | LPM_BESLD_STALL);
695df2069acSChunfeng Yun break;
696df2069acSChunfeng Yun case MTU3_SPEED_HIGH:
697df2069acSChunfeng Yun udev_speed = USB_SPEED_HIGH;
698df2069acSChunfeng Yun /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
699df2069acSChunfeng Yun mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
700df2069acSChunfeng Yun | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
701df2069acSChunfeng Yun mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
702df2069acSChunfeng Yun LPM_BESL_STALL | LPM_BESLD_STALL);
703df2069acSChunfeng Yun break;
704a29de31bSChunfeng Yun case MTU3_SPEED_SUPER:
705a29de31bSChunfeng Yun udev_speed = USB_SPEED_SUPER;
706a29de31bSChunfeng Yun maxpkt = 512;
707a29de31bSChunfeng Yun break;
7084d79e042SChunfeng Yun case MTU3_SPEED_SUPER_PLUS:
7094d79e042SChunfeng Yun udev_speed = USB_SPEED_SUPER_PLUS;
7104d79e042SChunfeng Yun maxpkt = 512;
7114d79e042SChunfeng Yun break;
712df2069acSChunfeng Yun default:
713df2069acSChunfeng Yun udev_speed = USB_SPEED_UNKNOWN;
714df2069acSChunfeng Yun break;
715df2069acSChunfeng Yun }
716df2069acSChunfeng Yun dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
71783374e03SChunfeng Yun mtu3_dbg_trace(mtu->dev, "link speed %s",
71883374e03SChunfeng Yun usb_speed_string(udev_speed));
719df2069acSChunfeng Yun
720df2069acSChunfeng Yun mtu->g.speed = udev_speed;
721df2069acSChunfeng Yun mtu->g.ep0->maxpacket = maxpkt;
722df2069acSChunfeng Yun mtu->ep0_state = MU3D_EP0_STATE_SETUP;
723427c6642SChunfeng Yun mtu->connected = !!(udev_speed != USB_SPEED_UNKNOWN);
724df2069acSChunfeng Yun
725427c6642SChunfeng Yun if (udev_speed == USB_SPEED_UNKNOWN) {
726df2069acSChunfeng Yun mtu3_gadget_disconnect(mtu);
727427c6642SChunfeng Yun pm_runtime_put(mtu->dev);
728427c6642SChunfeng Yun } else {
729427c6642SChunfeng Yun pm_runtime_get(mtu->dev);
730df2069acSChunfeng Yun mtu3_ep0_setup(mtu);
731427c6642SChunfeng Yun }
732df2069acSChunfeng Yun
733df2069acSChunfeng Yun return IRQ_HANDLED;
734df2069acSChunfeng Yun }
735df2069acSChunfeng Yun
mtu3_u3_ltssm_isr(struct mtu3 * mtu)736a29de31bSChunfeng Yun static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
737a29de31bSChunfeng Yun {
738a29de31bSChunfeng Yun void __iomem *mbase = mtu->mac_base;
739a29de31bSChunfeng Yun u32 ltssm;
740a29de31bSChunfeng Yun
741a29de31bSChunfeng Yun ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
742a29de31bSChunfeng Yun ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
743a29de31bSChunfeng Yun mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
744a29de31bSChunfeng Yun dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
74583374e03SChunfeng Yun trace_mtu3_u3_ltssm_isr(ltssm);
746a29de31bSChunfeng Yun
747a29de31bSChunfeng Yun if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
748a29de31bSChunfeng Yun mtu3_gadget_reset(mtu);
749a29de31bSChunfeng Yun
7504f9f032cSChunfeng Yun if (ltssm & VBUS_FALL_INTR) {
751a29de31bSChunfeng Yun mtu3_ss_func_set(mtu, false);
7524f9f032cSChunfeng Yun mtu3_gadget_reset(mtu);
7534f9f032cSChunfeng Yun }
754a29de31bSChunfeng Yun
755a29de31bSChunfeng Yun if (ltssm & VBUS_RISE_INTR)
756a29de31bSChunfeng Yun mtu3_ss_func_set(mtu, true);
757a29de31bSChunfeng Yun
758a29de31bSChunfeng Yun if (ltssm & EXIT_U3_INTR)
759a29de31bSChunfeng Yun mtu3_gadget_resume(mtu);
760a29de31bSChunfeng Yun
761a29de31bSChunfeng Yun if (ltssm & ENTER_U3_INTR)
762a29de31bSChunfeng Yun mtu3_gadget_suspend(mtu);
763a29de31bSChunfeng Yun
764a29de31bSChunfeng Yun return IRQ_HANDLED;
765a29de31bSChunfeng Yun }
766a29de31bSChunfeng Yun
mtu3_u2_common_isr(struct mtu3 * mtu)767df2069acSChunfeng Yun static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
768df2069acSChunfeng Yun {
769df2069acSChunfeng Yun void __iomem *mbase = mtu->mac_base;
770df2069acSChunfeng Yun u32 u2comm;
771df2069acSChunfeng Yun
772df2069acSChunfeng Yun u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
773df2069acSChunfeng Yun u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
774df2069acSChunfeng Yun mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
775df2069acSChunfeng Yun dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
77683374e03SChunfeng Yun trace_mtu3_u2_common_isr(u2comm);
777df2069acSChunfeng Yun
778df2069acSChunfeng Yun if (u2comm & SUSPEND_INTR)
779df2069acSChunfeng Yun mtu3_gadget_suspend(mtu);
780df2069acSChunfeng Yun
781df2069acSChunfeng Yun if (u2comm & RESUME_INTR)
782df2069acSChunfeng Yun mtu3_gadget_resume(mtu);
783df2069acSChunfeng Yun
784df2069acSChunfeng Yun if (u2comm & RESET_INTR)
785df2069acSChunfeng Yun mtu3_gadget_reset(mtu);
786df2069acSChunfeng Yun
787df2069acSChunfeng Yun return IRQ_HANDLED;
788df2069acSChunfeng Yun }
789df2069acSChunfeng Yun
mtu3_irq(int irq,void * data)790a8bac371SSudip Mukherjee static irqreturn_t mtu3_irq(int irq, void *data)
791df2069acSChunfeng Yun {
792df2069acSChunfeng Yun struct mtu3 *mtu = (struct mtu3 *)data;
793df2069acSChunfeng Yun unsigned long flags;
794df2069acSChunfeng Yun u32 level1;
795df2069acSChunfeng Yun
796df2069acSChunfeng Yun spin_lock_irqsave(&mtu->lock, flags);
797df2069acSChunfeng Yun
798df2069acSChunfeng Yun /* U3D_LV1ISR is RU */
799df2069acSChunfeng Yun level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
800df2069acSChunfeng Yun level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
801df2069acSChunfeng Yun
802df2069acSChunfeng Yun if (level1 & EP_CTRL_INTR)
803df2069acSChunfeng Yun mtu3_link_isr(mtu);
804df2069acSChunfeng Yun
805df2069acSChunfeng Yun if (level1 & MAC2_INTR)
806df2069acSChunfeng Yun mtu3_u2_common_isr(mtu);
807df2069acSChunfeng Yun
808a29de31bSChunfeng Yun if (level1 & MAC3_INTR)
809a29de31bSChunfeng Yun mtu3_u3_ltssm_isr(mtu);
810a29de31bSChunfeng Yun
811df2069acSChunfeng Yun if (level1 & BMU_INTR)
812df2069acSChunfeng Yun mtu3_ep0_isr(mtu);
813df2069acSChunfeng Yun
814df2069acSChunfeng Yun if (level1 & QMU_INTR)
815df2069acSChunfeng Yun mtu3_qmu_isr(mtu);
816df2069acSChunfeng Yun
817df2069acSChunfeng Yun spin_unlock_irqrestore(&mtu->lock, flags);
818df2069acSChunfeng Yun
819df2069acSChunfeng Yun return IRQ_HANDLED;
820df2069acSChunfeng Yun }
821df2069acSChunfeng Yun
mtu3_check_params(struct mtu3 * mtu)8221258450eSChunfeng Yun static void mtu3_check_params(struct mtu3 *mtu)
8231258450eSChunfeng Yun {
824*269f49ffSChunfeng Yun /* device's u3 port (port0) is disabled */
825*269f49ffSChunfeng Yun if (mtu->u3_capable && (mtu->ssusb->u3p_dis_msk & BIT(0)))
826*269f49ffSChunfeng Yun mtu->u3_capable = 0;
827*269f49ffSChunfeng Yun
8281258450eSChunfeng Yun /* check the max_speed parameter */
8291258450eSChunfeng Yun switch (mtu->max_speed) {
8301258450eSChunfeng Yun case USB_SPEED_FULL:
8311258450eSChunfeng Yun case USB_SPEED_HIGH:
8321258450eSChunfeng Yun case USB_SPEED_SUPER:
8331258450eSChunfeng Yun case USB_SPEED_SUPER_PLUS:
8341258450eSChunfeng Yun break;
8351258450eSChunfeng Yun default:
8361258450eSChunfeng Yun dev_err(mtu->dev, "invalid max_speed: %s\n",
8371258450eSChunfeng Yun usb_speed_string(mtu->max_speed));
8381258450eSChunfeng Yun fallthrough;
8391258450eSChunfeng Yun case USB_SPEED_UNKNOWN:
8401258450eSChunfeng Yun /* default as SSP */
8411258450eSChunfeng Yun mtu->max_speed = USB_SPEED_SUPER_PLUS;
8421258450eSChunfeng Yun break;
8431258450eSChunfeng Yun }
8441258450eSChunfeng Yun
845*269f49ffSChunfeng Yun if (!mtu->u3_capable && (mtu->max_speed > USB_SPEED_HIGH))
8461258450eSChunfeng Yun mtu->max_speed = USB_SPEED_HIGH;
8471258450eSChunfeng Yun
848dc4c1aa7SChunfeng Yun mtu->speed = mtu->max_speed;
849dc4c1aa7SChunfeng Yun
8501258450eSChunfeng Yun dev_info(mtu->dev, "max_speed: %s\n",
8511258450eSChunfeng Yun usb_speed_string(mtu->max_speed));
8521258450eSChunfeng Yun }
8531258450eSChunfeng Yun
mtu3_hw_init(struct mtu3 * mtu)854df2069acSChunfeng Yun static int mtu3_hw_init(struct mtu3 *mtu)
855df2069acSChunfeng Yun {
8564c5964b4SChunfeng Yun u32 value;
857df2069acSChunfeng Yun int ret;
858df2069acSChunfeng Yun
8594c5964b4SChunfeng Yun value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
8604c5964b4SChunfeng Yun mtu->hw_version = IP_TRUNK_VERS(value);
86148e0d373SChunfeng Yun mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
862220d88eaSChunfeng Yun
8634c5964b4SChunfeng Yun value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
864*269f49ffSChunfeng Yun mtu->u3_capable = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
865*269f49ffSChunfeng Yun /* usb3 ip uses separate fifo */
866*269f49ffSChunfeng Yun mtu->separate_fifo = mtu->u3_capable;
867220d88eaSChunfeng Yun
868220d88eaSChunfeng Yun dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
869*269f49ffSChunfeng Yun mtu->u3_capable ? "U3" : "U2");
870220d88eaSChunfeng Yun
8711258450eSChunfeng Yun mtu3_check_params(mtu);
8721258450eSChunfeng Yun
873df2069acSChunfeng Yun mtu3_device_reset(mtu);
874df2069acSChunfeng Yun
875df2069acSChunfeng Yun ret = mtu3_device_enable(mtu);
876df2069acSChunfeng Yun if (ret) {
877df2069acSChunfeng Yun dev_err(mtu->dev, "device enable failed %d\n", ret);
878df2069acSChunfeng Yun return ret;
879df2069acSChunfeng Yun }
880df2069acSChunfeng Yun
881df2069acSChunfeng Yun ret = mtu3_mem_alloc(mtu);
882df2069acSChunfeng Yun if (ret)
883df2069acSChunfeng Yun return -ENOMEM;
884df2069acSChunfeng Yun
885df2069acSChunfeng Yun mtu3_regs_init(mtu);
886df2069acSChunfeng Yun
887df2069acSChunfeng Yun return 0;
888df2069acSChunfeng Yun }
889df2069acSChunfeng Yun
mtu3_hw_exit(struct mtu3 * mtu)890df2069acSChunfeng Yun static void mtu3_hw_exit(struct mtu3 *mtu)
891df2069acSChunfeng Yun {
892df2069acSChunfeng Yun mtu3_device_disable(mtu);
893df2069acSChunfeng Yun mtu3_mem_free(mtu);
894df2069acSChunfeng Yun }
895df2069acSChunfeng Yun
8968709e367SLee Jones /*
8971a46dfeaSChunfeng Yun * we set 32-bit DMA mask by default, here check whether the controller
8981a46dfeaSChunfeng Yun * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
8991a46dfeaSChunfeng Yun */
mtu3_set_dma_mask(struct mtu3 * mtu)9001a46dfeaSChunfeng Yun static int mtu3_set_dma_mask(struct mtu3 *mtu)
9011a46dfeaSChunfeng Yun {
9021a46dfeaSChunfeng Yun struct device *dev = mtu->dev;
9031a46dfeaSChunfeng Yun bool is_36bit = false;
9041a46dfeaSChunfeng Yun int ret = 0;
9051a46dfeaSChunfeng Yun u32 value;
9061a46dfeaSChunfeng Yun
9071a46dfeaSChunfeng Yun value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
9081a46dfeaSChunfeng Yun if (value & DMA_ADDR_36BIT) {
9091a46dfeaSChunfeng Yun is_36bit = true;
9101a46dfeaSChunfeng Yun ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
9111a46dfeaSChunfeng Yun /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
9121a46dfeaSChunfeng Yun if (ret) {
9131a46dfeaSChunfeng Yun is_36bit = false;
9141a46dfeaSChunfeng Yun ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
9151a46dfeaSChunfeng Yun }
9161a46dfeaSChunfeng Yun }
9171a46dfeaSChunfeng Yun dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
9181a46dfeaSChunfeng Yun
9191a46dfeaSChunfeng Yun return ret;
9201a46dfeaSChunfeng Yun }
921df2069acSChunfeng Yun
ssusb_gadget_init(struct ssusb_mtk * ssusb)922b3f4e727SChunfeng Yun int ssusb_gadget_init(struct ssusb_mtk *ssusb)
923df2069acSChunfeng Yun {
924b3f4e727SChunfeng Yun struct device *dev = ssusb->dev;
925b3f4e727SChunfeng Yun struct platform_device *pdev = to_platform_device(dev);
926b3f4e727SChunfeng Yun struct mtu3 *mtu = NULL;
927b3f4e727SChunfeng Yun int ret = -ENOMEM;
928df2069acSChunfeng Yun
929b3f4e727SChunfeng Yun mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
930b3f4e727SChunfeng Yun if (mtu == NULL)
931b3f4e727SChunfeng Yun return -ENOMEM;
932b3f4e727SChunfeng Yun
933fa6f59e2SChunfeng Yun mtu->irq = platform_get_irq_byname_optional(pdev, "device");
934fa6f59e2SChunfeng Yun if (mtu->irq < 0) {
935fa6f59e2SChunfeng Yun if (mtu->irq == -EPROBE_DEFER)
936fa6f59e2SChunfeng Yun return mtu->irq;
937fa6f59e2SChunfeng Yun
938fa6f59e2SChunfeng Yun /* for backward compatibility */
939b3f4e727SChunfeng Yun mtu->irq = platform_get_irq(pdev, 0);
940b33f3706SStephen Boyd if (mtu->irq < 0)
941c162ff0aSChunfeng Yun return mtu->irq;
942fa6f59e2SChunfeng Yun }
943b3f4e727SChunfeng Yun dev_info(dev, "irq %d\n", mtu->irq);
944b3f4e727SChunfeng Yun
9455ad91812SChunfeng Yun mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
946b3f4e727SChunfeng Yun if (IS_ERR(mtu->mac_base)) {
947b3f4e727SChunfeng Yun dev_err(dev, "error mapping memory for dev mac\n");
948b3f4e727SChunfeng Yun return PTR_ERR(mtu->mac_base);
949b3f4e727SChunfeng Yun }
950b3f4e727SChunfeng Yun
951b3f4e727SChunfeng Yun spin_lock_init(&mtu->lock);
952b3f4e727SChunfeng Yun mtu->dev = dev;
953b3f4e727SChunfeng Yun mtu->ippc_base = ssusb->ippc_base;
954b3f4e727SChunfeng Yun ssusb->mac_base = mtu->mac_base;
955b3f4e727SChunfeng Yun ssusb->u3d = mtu;
956b3f4e727SChunfeng Yun mtu->ssusb = ssusb;
957a29de31bSChunfeng Yun mtu->max_speed = usb_get_maximum_speed(dev);
958a29de31bSChunfeng Yun
959a29de31bSChunfeng Yun dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
960a29de31bSChunfeng Yun mtu->mac_base, mtu->ippc_base);
961a29de31bSChunfeng Yun
962df2069acSChunfeng Yun ret = mtu3_hw_init(mtu);
963df2069acSChunfeng Yun if (ret) {
964df2069acSChunfeng Yun dev_err(dev, "mtu3 hw init failed:%d\n", ret);
965df2069acSChunfeng Yun return ret;
966df2069acSChunfeng Yun }
967df2069acSChunfeng Yun
9681a46dfeaSChunfeng Yun ret = mtu3_set_dma_mask(mtu);
9691a46dfeaSChunfeng Yun if (ret) {
9701a46dfeaSChunfeng Yun dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
9711a46dfeaSChunfeng Yun goto dma_mask_err;
9721a46dfeaSChunfeng Yun }
9731a46dfeaSChunfeng Yun
97413118959SChunfeng Yun ret = devm_request_threaded_irq(dev, mtu->irq, NULL, mtu3_irq,
97513118959SChunfeng Yun IRQF_ONESHOT, dev_name(dev), mtu);
976df2069acSChunfeng Yun if (ret) {
977df2069acSChunfeng Yun dev_err(dev, "request irq %d failed!\n", mtu->irq);
978df2069acSChunfeng Yun goto irq_err;
979df2069acSChunfeng Yun }
980df2069acSChunfeng Yun
981b057da6dSChunfeng Yun /* power down device IP for power saving by default */
982b057da6dSChunfeng Yun mtu3_stop(mtu);
983b057da6dSChunfeng Yun
984df2069acSChunfeng Yun ret = mtu3_gadget_setup(mtu);
985df2069acSChunfeng Yun if (ret) {
986df2069acSChunfeng Yun dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
987df2069acSChunfeng Yun goto gadget_err;
988df2069acSChunfeng Yun }
989df2069acSChunfeng Yun
990ae078092SChunfeng Yun ssusb_dev_debugfs_init(ssusb);
991ae078092SChunfeng Yun
992df2069acSChunfeng Yun dev_dbg(dev, " %s() done...\n", __func__);
993df2069acSChunfeng Yun
994df2069acSChunfeng Yun return 0;
995df2069acSChunfeng Yun
996df2069acSChunfeng Yun gadget_err:
997df2069acSChunfeng Yun device_init_wakeup(dev, false);
998df2069acSChunfeng Yun
9991a46dfeaSChunfeng Yun dma_mask_err:
1000df2069acSChunfeng Yun irq_err:
1001df2069acSChunfeng Yun mtu3_hw_exit(mtu);
1002b3f4e727SChunfeng Yun ssusb->u3d = NULL;
1003df2069acSChunfeng Yun dev_err(dev, " %s() fail...\n", __func__);
1004df2069acSChunfeng Yun
1005df2069acSChunfeng Yun return ret;
1006df2069acSChunfeng Yun }
1007df2069acSChunfeng Yun
ssusb_gadget_exit(struct ssusb_mtk * ssusb)1008b3f4e727SChunfeng Yun void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
1009df2069acSChunfeng Yun {
1010b3f4e727SChunfeng Yun struct mtu3 *mtu = ssusb->u3d;
1011b3f4e727SChunfeng Yun
1012df2069acSChunfeng Yun mtu3_gadget_cleanup(mtu);
1013b3f4e727SChunfeng Yun device_init_wakeup(ssusb->dev, false);
1014df2069acSChunfeng Yun mtu3_hw_exit(mtu);
1015df2069acSChunfeng Yun }
1016427c6642SChunfeng Yun
ssusb_gadget_ip_sleep_check(struct ssusb_mtk * ssusb)10176b587394SChunfeng Yun bool ssusb_gadget_ip_sleep_check(struct ssusb_mtk *ssusb)
10186b587394SChunfeng Yun {
10196b587394SChunfeng Yun struct mtu3 *mtu = ssusb->u3d;
10206b587394SChunfeng Yun
10216b587394SChunfeng Yun /* host only, should wait for ip sleep */
10226b587394SChunfeng Yun if (!mtu)
10236b587394SChunfeng Yun return true;
10246b587394SChunfeng Yun
10256b587394SChunfeng Yun /* device is started and pullup D+, ip can sleep */
10266b587394SChunfeng Yun if (mtu->is_active && mtu->softconnect)
10276b587394SChunfeng Yun return true;
10286b587394SChunfeng Yun
10296b587394SChunfeng Yun /* ip can't sleep if not pullup D+ when support device mode */
10306b587394SChunfeng Yun return false;
10316b587394SChunfeng Yun }
10326b587394SChunfeng Yun
ssusb_gadget_suspend(struct ssusb_mtk * ssusb,pm_message_t msg)1033427c6642SChunfeng Yun int ssusb_gadget_suspend(struct ssusb_mtk *ssusb, pm_message_t msg)
1034427c6642SChunfeng Yun {
1035427c6642SChunfeng Yun struct mtu3 *mtu = ssusb->u3d;
1036427c6642SChunfeng Yun
1037427c6642SChunfeng Yun if (!mtu->gadget_driver)
1038427c6642SChunfeng Yun return 0;
1039427c6642SChunfeng Yun
1040427c6642SChunfeng Yun if (mtu->connected)
1041427c6642SChunfeng Yun return -EBUSY;
1042427c6642SChunfeng Yun
1043427c6642SChunfeng Yun mtu3_dev_suspend(mtu);
1044427c6642SChunfeng Yun synchronize_irq(mtu->irq);
1045427c6642SChunfeng Yun
10466b587394SChunfeng Yun return 0;
1047427c6642SChunfeng Yun }
1048427c6642SChunfeng Yun
ssusb_gadget_resume(struct ssusb_mtk * ssusb,pm_message_t msg)1049427c6642SChunfeng Yun int ssusb_gadget_resume(struct ssusb_mtk *ssusb, pm_message_t msg)
1050427c6642SChunfeng Yun {
1051427c6642SChunfeng Yun struct mtu3 *mtu = ssusb->u3d;
1052427c6642SChunfeng Yun
1053427c6642SChunfeng Yun if (!mtu->gadget_driver)
1054427c6642SChunfeng Yun return 0;
1055427c6642SChunfeng Yun
1056427c6642SChunfeng Yun mtu3_dev_resume(mtu);
1057427c6642SChunfeng Yun
1058427c6642SChunfeng Yun return 0;
1059427c6642SChunfeng Yun }
1060