| /openbmc/u-boot/arch/arm/dts/ |
| H A D | exynos5250-pinctrl.dtsi | 21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
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| H A D | exynos4x12-pinctrl.dtsi | 21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
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| H A D | exynos54xx-pinctrl.dtsi | 23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
32 interrupt-parent = <&combiner>;
33 #interrupt-cells = <2>;
42 interrupt-controller;
43 interrupt-parent = <&combiner>;
44 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
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| H A D | exynos4210-pinctrl.dtsi | 23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
32 #interrupt-cells = <2>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
47 interrupt-controller;
48 #interrupt-cells = <2>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
[all …]
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| H A D | exynos4.dtsi | 23 combiner: interrupt-controller@10440000 {
25 #interrupt-cells = <2>;
26 interrupt-controller;
30 gic: interrupt-controller@10490000 {
32 #interrupt-cells = <3>;
33 interrupt-controller;
73 interrupt-parent = <&gic>;
82 interrupt-parent = <&gic>;
91 interrupt-parent = <&gic>;
100 interrupt-parent = <&gic>;
[all …]
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| H A D | zynqmp.dtsi | 107 interrupt-parent = <&gic>;
122 interrupt-parent = <&gic>;
128 interrupt-parent = <&gic>;
219 gic: interrupt-controller@f9010000 {
221 #interrupt-cells = <3>;
226 interrupt-controller;
227 interrupt-parent = <&gic>;
245 interrupt-parent = <&gic>;
256 interrupt-parent = <&gic>;
271 interrupt-parent = <&gic>;
[all …]
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| /openbmc/qemu/hw/intc/ |
| H A D | imx_avic.c | 2 * i.MX31 Vectored Interrupt Controller
76 * Take interrupt if there's a pending interrupt with in imx_avic_update()
119 case 1: /* Normal Interrupt Mask Register, NIMASK */ in imx_avic_read()
122 case 2: /* Interrupt Enable Number Register, INTENNUM */ in imx_avic_read()
123 case 3: /* Interrupt Disable Number Register, INTDISNUM */ in imx_avic_read()
126 case 4: /* Interrupt Enabled Number Register High */ in imx_avic_read()
129 case 5: /* Interrupt Enabled Number Register Low */ in imx_avic_read()
132 case 6: /* Interrupt Type Register High */ in imx_avic_read()
135 case 7: /* Interrupt Type Register Low */ in imx_avic_read()
138 case 8: /* Normal Interrupt Priority Register 7 */ in imx_avic_read()
[all …]
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| H A D | aspeed_vic.c | 2 * ASPEED Interrupt Controller (New)
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
66 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", in aspeed_vic_set_irq()
131 case 0x90: /* Raw Interrupt Status */ in aspeed_vic_read()
135 case 0x98: /* Interrupt Selection */ in aspeed_vic_read()
139 case 0xa0: /* Interrupt Enable */ in aspeed_vic_read()
143 case 0xb0: /* Software Interrupt */ in aspeed_vic_read()
147 case 0xc0: /* Interrupt Sensitivity */ in aspeed_vic_read()
151 case 0xc8: /* Interrupt Both Edge Trigger Control */ in aspeed_vic_read()
155 case 0xd0: /* Interrupt Event */ in aspeed_vic_read()
[all …]
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| /openbmc/u-boot/arch/mips/dts/ |
| H A D | img,boston.dts | 5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
34 gic: interrupt-controller {
37 interrupt-controller;
38 #interrupt-cells = <3>;
55 #interrupt-cells = <1>;
57 interrupt-parent = <&gic>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 1 &pci0_intc 0>,
69 pci0_intc: interrupt-controller {
[all …]
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| H A D | jz4780.dtsi | 10 cpuintc: interrupt-controller {
12 #interrupt-cells = <1>;
13 interrupt-controller;
14 compatible = "mti,cpu-interrupt-controller";
17 intc: interrupt-controller@10001000 {
21 interrupt-controller;
22 #interrupt-cells = <1>;
24 interrupt-parent = <&cpuintc>;
74 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
[all …]
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| H A D | mt7628a.dtsi | 24 cpuintc: interrupt-controller {
26 #interrupt-cells = <1>;
27 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller";
58 interrupt-parent = <&intc>;
62 intc: interrupt-controller@200 {
66 interrupt-controller;
67 #interrupt-cells = <1>;
72 interrupt-parent = <&cpuintc>;
92 interrupt-parent = <&intc>;
[all …]
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| /openbmc/u-boot/arch/microblaze/include/asm/ |
| H A D | microblaze_intc.h | 9 int isr; /* interrupt status register */
10 int ipr; /* interrupt pending register */
11 int ier; /* interrupt enable register */
12 int iar; /* interrupt acknowledge register */
13 int sie; /* set interrupt enable bits */
14 int cie; /* clear interrupt enable bits */
15 int ivr; /* interrupt vector register */
20 interrupt_handler_t *handler; /* pointer to interrupt rutine */
22 int count; /* number of interrupt */
26 * Register and unregister interrupt handler rutines
[all …]
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| /openbmc/u-boot/arch/riscv/dts/ |
| H A D | ae350_64.dts | 33 CPU0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
52 plic0: interrupt-controller@e4000000 {
55 #interrupt-cells = <2>;
56 interrupt-controller;
62 plic1: interrupt-controller@e6400000 {
65 #interrupt-cells = <2>;
66 interrupt-controller;
90 interrupt-parent = <&plic0>;
[all …]
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| H A D | ae350_32.dts | 33 CPU0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 interrupt-controller;
52 plic0: interrupt-controller@e4000000 {
55 #interrupt-cells = <1>;
56 interrupt-controller;
62 plic1: interrupt-controller@e6400000 {
65 #interrupt-cells = <1>;
66 interrupt-controller;
90 interrupt-parent = <&plic0>;
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | gpio-pcf857x.txt | 46 an interrupt controller. When the expander interrupt line is connected all the
48 interrupt controller device tree bindings documentation available at
49 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
51 - interrupt-controller: Identifies the node as an interrupt controller.
52 - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
53 - interrupt-parent: phandle of the parent interrupt controller.
54 - interrupts: Interrupt specifier for the controllers interrupt.
65 interrupt-parent = <&irqpin2>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
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| /openbmc/u-boot/include/usb/ |
| H A D | fotg210.h | 25 uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
26 uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
28 uint32_t isr; /* 0xC0: Global Interrupt Status Register */
29 uint32_t imr; /* 0xC4: Global Interrupt Mask Register */
42 uint32_t gimr; /* 0x130: Group Interrupt Mask Register */
43 uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
44 uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
45 uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
46 uint32_t gisr; /* 0x140: Group Interrupt Status Register */
47 uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
[all …]
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| /openbmc/qemu/docs/specs/ |
| H A D | edu.rst | 63 raise interrupt after finishing factorial computation
65 0x24 (RO) : interrupt status register
66 It contains values which raised the interrupt (see interrupt raise
69 0x60 (WO) : interrupt raise register
70 Raise an interrupt. The value will be put to the interrupt status
73 0x64 (WO) : interrupt acknowledge register
74 Clear an interrupt. The value will be cleared from the interrupt
95 raise interrupt 0x100 after finishing the DMA
100 An IRQ is generated when written to the interrupt raise register. The value
101 appears in interrupt status register when the interrupt is raised and has to
[all …]
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| H A D | ppc-xive.rst | 2 POWER9 XIVE interrupt controller
5 The POWER9 processor comes with a new interrupt controller
6 architecture, called XIVE as "eXternal Interrupt Virtualization
10 XIVE are to support a larger number of interrupt sources and to
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
29 Controller (VC). It handles event coalescing and perform interrupt
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
33 Controller (PC). It maintains the interrupt context state of each
34 thread and handles the delivery of the external interrupt to the
[all …]
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| H A D | ivshmem-spec.rst | 14 In the latter case, the device can additionally interrupt its peers, and
41 - If you additionally need the capability for peers to interrupt each
64 0 4 read/write 0 Interrupt Mask
65 bit 0: peer interrupt (rev 0)
68 4 4 read/write 0 Interrupt Status
69 bit 0: peer interrupt (rev 0)
82 In revision 0 of the device, Interrupt Status and Mask Register
83 together control the legacy INTx interrupt when the device has no
85 Mask is non-zero and the device has no MSI-X capability. Interrupt
86 Status Register bit 0 becomes 1 when an interrupt request from a peer
[all …]
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| /openbmc/qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 52 UIC0: interrupt-controller0 {
54 interrupt-controller;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
64 interrupt-controller;
69 #interrupt-cells = <2>;
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
76 interrupt-controller;
81 #interrupt-cells = <2>;
[all …]
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| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | intctrl.h | 3 * Interrupt Controller Memory Map
19 /* Interrupt Controller 0 */
33 u8 simr0; /* 0x1C Set Interrupt Mask */
34 u8 cimr0; /* 0x1D Clear Interrupt Mask */
41 u8 swiack0; /* 0xE0 Software Interrupt ack */
43 u8 L1iack0; /* 0xE4 Level n interrupt ack */
45 u8 L2iack0; /* 0xE8 Level n interrupt ack */
47 u8 L3iack0; /* 0xEC Level n interrupt ack */
49 u8 L4iack0; /* 0xF0 Level n interrupt ack */
51 u8 L5iack0; /* 0xF4 Level n interrupt ack */
[all …]
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| /openbmc/qemu/tests/tcg/xtensa/ |
| H A D | test_timer.S | 66 rsr a2, interrupt
77 rsr a3, interrupt
83 rsr a2, interrupt
91 rsr a2, interrupt
104 rsr a3, interrupt
106 rsr a5, interrupt
119 rsr a2, interrupt
133 rsr a2, interrupt
156 rsr a2, interrupt
168 rsr a2, interrupt
[all …]
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| /openbmc/qemu/rust/qemu-api/src/ |
| H A D | irq.rs | 5 //! Bindings for interrupt sources
25 /// Interrupt sources are used by devices to pass changes to a value (typically
26 /// a boolean). The interrupt sink is usually an interrupt controller or
29 /// As far as devices are concerned, interrupt sources are always active-high:
33 /// device and the interrupt controller.
35 /// Interrupts are implemented as a pointer to the interrupt "sink", which has
39 /// interrupt. To connect it, whoever creates the device fills the pointer with
41 /// devices are generally shared objects, interrupt sources are an example of
44 /// Interrupt sources can only be triggered under the Big QEMU Lock; `BqlCell`
60 /// Send a low (`false`) value to the interrupt sink.
[all …]
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| /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | interrupts.c | 17 * CPM interrupt vector functions.
66 * Read Interrupt Mask Register and Mask Interrupts in external_interrupt()
71 if (!(irq & 0x1)) { /* External Interrupt ? */ in external_interrupt()
75 * Read Interrupt Edge/Level Register in external_interrupt()
79 if (siel & v_bit) { /* edge triggered interrupt ? */ in external_interrupt()
81 * Rewrite SIPEND Register to clear interrupt in external_interrupt()
90 printf("\nBogus External Interrupt IRQ %d Vector %ld\n", in external_interrupt()
92 /* turn off the bogus interrupt to avoid it from now */ in external_interrupt()
96 * Re-Enable old Interrupt Mask in external_interrupt()
104 * CPM interrupt handler
[all …]
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| /openbmc/qemu/tests/qtest/ |
| H A D | stm32l4x5_exti-test.c | 177 * Testing interrupt line EXTI0 in test_software_interrupt()
184 /* Check that this specific interrupt isn't pending in NVIC */ in test_software_interrupt()
187 /* Enable interrupt line EXTI0 */ in test_software_interrupt()
197 /* Check that the corresponding interrupt is pending in the NVIC */ in test_software_interrupt()
207 /* Check that the interrupt is still pending in the NVIC */ in test_software_interrupt()
211 * Testing interrupt line EXTI35 in test_software_interrupt()
220 /* Enable interrupt line EXTI0 */ in test_software_interrupt()
230 /* Check that the corresponding interrupt is pending in the NVIC */ in test_software_interrupt()
240 /* Check that the interrupt is still pending in the NVIC */ in test_software_interrupt()
347 * Testing interrupt line EXTI0 in test_no_software_interrupt()
[all …]
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