Home
last modified time | relevance | path

Searched full:interrupt (Results 1 – 25 of 7600) sorted by relevance

12345678910>>...304

/openbmc/u-boot/arch/arm/dts/
H A Dexynos5250-pinctrl.dtsi21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
H A Dexynos4x12-pinctrl.dtsi21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
H A Dexynos54xx-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
32 interrupt-parent = <&combiner>;
33 #interrupt-cells = <2>;
42 interrupt-controller;
43 interrupt-parent = <&combiner>;
44 #interrupt-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
H A Dexynos4210-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
32 #interrupt-cells = <2>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
47 interrupt-controller;
48 #interrupt-cells = <2>;
55 interrupt-controller;
56 #interrupt-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,rzg2l-irqc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
31 '#interrupt-cells':
33 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
40 interrupt-controller: true
48 - description: NMI interrupt
49 - description: IRQ0 interrupt
[all …]
H A Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
[all …]
H A Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
[all …]
H A Dsamsung,exynos4210-combiner.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
[all …]
H A Dmarvell,orion-intc.txt1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
[all …]
H A Dbrcm,bcm7120-l2-intc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
22 directly output an interrupt signal towards the interrupt controller parent,
23 or if they will output an interrupt signal at this 2nd level interrupt
30 - not all bits within the interrupt controller actually map to an interrupt
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
[all …]
H A Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath11k.yaml32 interrupt-names:
101 - description: misc-pulse1 interrupt events
102 - description: misc-latch interrupt events
103 - description: sw exception interrupt events
104 - description: watchdog interrupt events
105 - description: interrupt event for ring CE0
106 - description: interrupt event for ring CE1
107 - description: interrupt event for ring CE2
108 - description: interrupt event for ring CE3
109 - description: interrupt event for ring CE4
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dfsp2.dts64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
/openbmc/linux/drivers/net/ipa/
H A Dipa_interrupt.c9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
23 #include <linux/interrupt.h>
35 * struct ipa_interrupt - IPA interrupt information
46 /* Process a particular interrupt type that has been received */
47 static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) in ipa_interrupt_process() argument
49 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_process()
60 /* For microcontroller interrupts, clear the interrupt right in ipa_interrupt_process()
68 /* Clearing the SUSPEND_TX interrupt also clears the in ipa_interrupt_process()
70 * caused the interrupt, so defer clearing until after in ipa_interrupt_process()
[all …]
H A Dipa_interrupt.h18 * @interrupt: IPA interrupt structure
19 * @endpoint_id: Endpoint whose interrupt should be enabled
22 * A TX_SUSPEND interrupt arrives on an AP RX enpoint when packet data can't
26 void ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt,
31 * @interrupt: IPA interrupt structure
32 * @endpoint_id: Endpoint whose interrupt should be disabled
34 void ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt,
39 * @interrupt: IPA interrupt structure
41 * Clear the TX_SUSPEND interrupt for all endpoints that signaled it.
43 void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt);
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm7358.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
H A Dbcm7360.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
H A Dbcm7346.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
H A Dbcm7362.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dls7a-pch.dtsi13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
89 interrupt-parent = <&pic>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxlnx,nwl-pcie.yaml14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
34 - description: interrupt asserted when miscellaneous interrupt is received
35 - description: unused interrupt(dummy)
36 - description: interrupt asserted when a legacy interrupt is received
37 - description: msi1 interrupt asserted when an MSI is received
38 - description: msi0 interrupt asserted when an MSI is received
40 interrupt-names:
48 interrupt-map-mask:
55 "#interrupt-cells":
61 interrupt-map:
[all …]
/openbmc/linux/include/linux/pds/
H A Dpds_intr.h8 * Interrupt control register
16 * When an interrupt is sent the interrupt
22 * interrupt coalescing is effectively disabled
23 * and every interrupt assert results in an
24 * interrupt. Reset value: 0
25 * @mask: Interrupt mask. When @mask=1 the interrupt
26 * resource will not send an interrupt. When
27 * @mask=0 the interrupt resource will send an
28 * interrupt if an interrupt event is pending
29 * or on the next interrupt assertion event.
[all …]

12345678910>>...304