2  * ASPEED Interrupt Controller (New)
24  * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
66         qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",  in aspeed_vic_set_irq()
131     case 0x90: /* Raw Interrupt Status */  in aspeed_vic_read()
135     case 0x98: /* Interrupt Selection */  in aspeed_vic_read()
139     case 0xa0: /* Interrupt Enable */  in aspeed_vic_read()
143     case 0xb0: /* Software Interrupt */  in aspeed_vic_read()
147     case 0xc0: /* Interrupt Sensitivity */  in aspeed_vic_read()
151     case 0xc8: /* Interrupt Both Edge Trigger Control */  in aspeed_vic_read()
155     case 0xd0: /* Interrupt Event */  in aspeed_vic_read()
159     case 0xe0: /* Edge Triggered Interrupt Status */  in aspeed_vic_read()
163     case 0xa8: /* Interrupt Enable Clear */  in aspeed_vic_read()
164     case 0xb8: /* Software Interrupt Clear */  in aspeed_vic_read()
165     case 0xd8: /* Edge Triggered Interrupt Clear */  in aspeed_vic_read()
216     case 0x98: /* Interrupt Selection */  in aspeed_vic_write()
226     case 0xa0: /* Interrupt Enable */  in aspeed_vic_write()
230     case 0xa8: /* Interrupt Enable Clear */  in aspeed_vic_write()
234     case 0xb0: /* Software Interrupt */  in aspeed_vic_write()
239     case 0xb8: /* Software Interrupt Clear */  in aspeed_vic_write()
244     case 0xd0: /* Interrupt Event */  in aspeed_vic_write()
253                           "Ignoring invalid write to interrupt event register");  in aspeed_vic_write()
256     case 0xd8: /* Edge Triggered Interrupt Clear */  in aspeed_vic_write()
264     case 0x90: /* Raw Interrupt Status */  in aspeed_vic_write()
266     case 0xc0: /* Interrupt Sensitivity */  in aspeed_vic_write()
268     case 0xc8: /* Interrupt Both Edge Trigger Control */  in aspeed_vic_write()
270     case 0xe0: /* Edge Triggered Interrupt Status */  in aspeed_vic_write()
347     dc->desc = "ASPEED Interrupt Controller (New)";  in aspeed_vic_class_init()